1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include <dt-bindings/display/media-bus-format.h> 10*4882a593Smuzhiyun#include "rk3588s-evb3-lp4x.dtsi" 11*4882a593Smuzhiyun#include "rk3588-android.dtsi" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun model = "Rockchip RK3588S EVB3 LP4 V10 Board + Rockchip RK3588S EVB V10 Extboard2"; 15*4882a593Smuzhiyun compatible = "rockchip,rk3588s-evb3-lp4x-v10-sii9022-bt1120-to-hdmi", "rockchip,rk3588"; 16*4882a593Smuzhiyun}; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun&dsi0_in_vp3 { 19*4882a593Smuzhiyun status = "disabled"; 20*4882a593Smuzhiyun}; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun&i2c4 { 23*4882a593Smuzhiyun clock-frequency = <400000>; 24*4882a593Smuzhiyun status = "okay"; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun sii9022: sii9022@39 { 27*4882a593Smuzhiyun compatible = "sil,sii9022"; 28*4882a593Smuzhiyun reg = <0x39>; 29*4882a593Smuzhiyun pinctrl-names = "default"; 30*4882a593Smuzhiyun pinctrl-0 = <&sii902x_hdmi_int>; 31*4882a593Smuzhiyun interrupt-parent = <&gpio3>; 32*4882a593Smuzhiyun interrupts = <RK_PC0 IRQ_TYPE_LEVEL_HIGH>; 33*4882a593Smuzhiyun reset-gpio = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>; 34*4882a593Smuzhiyun enable-gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; 35*4882a593Smuzhiyun bus-format = <MEDIA_BUS_FMT_UYVY8_1X16>; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun ports { 38*4882a593Smuzhiyun #address-cells = <1>; 39*4882a593Smuzhiyun #size-cells = <0>; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun port@0 { 42*4882a593Smuzhiyun reg = <0>; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun sii9022_in_rgb: endpoint { 45*4882a593Smuzhiyun remote-endpoint = <&rgb_out_sii9022>; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun}; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun&pinctrl { 53*4882a593Smuzhiyun sii902x { 54*4882a593Smuzhiyun sii902x_hdmi_int: sii902x-hdmi-int { 55*4882a593Smuzhiyun rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun}; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun&rgb { 61*4882a593Smuzhiyun status = "okay"; 62*4882a593Smuzhiyun pinctrl-names = "default"; 63*4882a593Smuzhiyun pinctrl-0 = <&bt1120_pins>; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun ports { 66*4882a593Smuzhiyun port@1 { 67*4882a593Smuzhiyun reg = <1>; 68*4882a593Smuzhiyun #address-cells = <1>; 69*4882a593Smuzhiyun #size-cells = <0>; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun rgb_out_sii9022: endpoint@0 { 72*4882a593Smuzhiyun reg = <0>; 73*4882a593Smuzhiyun remote-endpoint = <&sii9022_in_rgb>; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun}; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun&rgb_in_vp3 { 80*4882a593Smuzhiyun status = "okay"; 81*4882a593Smuzhiyun}; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun&vop { 84*4882a593Smuzhiyun status = "okay"; 85*4882a593Smuzhiyun}; 86