1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include <dt-bindings/display/media-bus-format.h> 10*4882a593Smuzhiyun#include "rk3588s-evb3-lp4x.dtsi" 11*4882a593Smuzhiyun#include "rk3588-android.dtsi" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun model = "Rockchip RK3588S EVB3 LP4 V10 Board + Rockchip RK3588S EVB V10 Extboard"; 15*4882a593Smuzhiyun compatible = "rockchip,rk3588s-evb3-lp4x-v10-nvp6158-ahd-to-bt1120", "rockchip,rk3588"; 16*4882a593Smuzhiyun}; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun&i2c2 { 19*4882a593Smuzhiyun status = "okay"; 20*4882a593Smuzhiyun pinctrl-names = "default"; 21*4882a593Smuzhiyun pinctrl-0 = <&i2c2m4_xfer>; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun nvp6158: nvp6158@30 { 24*4882a593Smuzhiyun compatible = "nvp6158-v4l2"; 25*4882a593Smuzhiyun status = "okay"; 26*4882a593Smuzhiyun reg = <0x30>; 27*4882a593Smuzhiyun clocks = <&cru CLK_CIFOUT_OUT>; 28*4882a593Smuzhiyun clock-names = "xvclk"; 29*4882a593Smuzhiyun power-domains = <&power RK3588_PD_VI>; 30*4882a593Smuzhiyun pinctrl-names = "default"; 31*4882a593Smuzhiyun pinctrl-0 = <&cif_clk &cif_dvp_clk &cif_dvp_bus8 &cif_dvp_bus16>; 32*4882a593Smuzhiyun // pwr-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; 33*4882a593Smuzhiyun pwr2-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>; 34*4882a593Smuzhiyun rst-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; 35*4882a593Smuzhiyun // rst2-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; 36*4882a593Smuzhiyun // pwdn-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; 37*4882a593Smuzhiyun // pwdn2-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; 38*4882a593Smuzhiyun rockchip,camera-module-index = <0>; 39*4882a593Smuzhiyun rockchip,camera-module-facing = "back"; 40*4882a593Smuzhiyun rockchip,camera-module-name = "default"; 41*4882a593Smuzhiyun rockchip,camera-module-lens-name = "default"; 42*4882a593Smuzhiyun rockchip,dvp_mode = "BT1120"; //BT656 or BT1120 or BT656_TEST 43*4882a593Smuzhiyun rockchip,channel_nums = <4>; //channel nums, 1/2/4 44*4882a593Smuzhiyun rockchip,dual_edge = <1>; // pclk dual edge, 0/1 45*4882a593Smuzhiyun rockchip,default_rect= <1920 1080>; // default resolution 46*4882a593Smuzhiyun port { 47*4882a593Smuzhiyun nvp6158_out: endpoint { 48*4882a593Smuzhiyun remote-endpoint = <&dvp_in_bcam1>; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun}; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun&rkcif { 55*4882a593Smuzhiyun status = "okay"; 56*4882a593Smuzhiyun}; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun&rkcif_dvp { 59*4882a593Smuzhiyun status = "okay"; 60*4882a593Smuzhiyun ports { 61*4882a593Smuzhiyun #address-cells = <1>; 62*4882a593Smuzhiyun #size-cells = <0>; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun port@0 { 65*4882a593Smuzhiyun #address-cells = <1>; 66*4882a593Smuzhiyun #size-cells = <0>; 67*4882a593Smuzhiyun /* Parallel bus endpoint */ 68*4882a593Smuzhiyun dvp_in_bcam1: endpoint@1 { 69*4882a593Smuzhiyun reg = <1>; 70*4882a593Smuzhiyun remote-endpoint = <&nvp6158_out>; 71*4882a593Smuzhiyun bus-width = <16>; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun}; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun&rkcif_mmu { 78*4882a593Smuzhiyun status = "okay"; 79*4882a593Smuzhiyun}; 80