1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 8*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h> 9*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h> 10*4882a593Smuzhiyun#include <dt-bindings/input/rk-input.h> 11*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h> 12*4882a593Smuzhiyun#include <dt-bindings/display/rockchip_vop.h> 13*4882a593Smuzhiyun#include <dt-bindings/sensor-dev.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun/ { 16*4882a593Smuzhiyun adc_keys: adc-keys { 17*4882a593Smuzhiyun compatible = "adc-keys"; 18*4882a593Smuzhiyun io-channels = <&saradc 1>; 19*4882a593Smuzhiyun io-channel-names = "buttons"; 20*4882a593Smuzhiyun keyup-threshold-microvolt = <1800000>; 21*4882a593Smuzhiyun poll-interval = <100>; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun vol-up-key { 24*4882a593Smuzhiyun label = "volume up"; 25*4882a593Smuzhiyun linux,code = <KEY_VOLUMEUP>; 26*4882a593Smuzhiyun press-threshold-microvolt = <17000>; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun vol-down-key { 30*4882a593Smuzhiyun label = "volume down"; 31*4882a593Smuzhiyun linux,code = <KEY_VOLUMEDOWN>; 32*4882a593Smuzhiyun press-threshold-microvolt = <417000>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun menu-key { 36*4882a593Smuzhiyun label = "menu"; 37*4882a593Smuzhiyun linux,code = <KEY_MENU>; 38*4882a593Smuzhiyun press-threshold-microvolt = <890000>; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun back-key { 42*4882a593Smuzhiyun label = "back"; 43*4882a593Smuzhiyun linux,code = <KEY_BACK>; 44*4882a593Smuzhiyun press-threshold-microvolt = <1235000>; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun backlight: backlight { 49*4882a593Smuzhiyun compatible = "pwm-backlight"; 50*4882a593Smuzhiyun brightness-levels = < 51*4882a593Smuzhiyun 0 20 20 21 21 22 22 23 52*4882a593Smuzhiyun 23 24 24 25 25 26 26 27 53*4882a593Smuzhiyun 27 28 28 29 29 30 30 31 54*4882a593Smuzhiyun 31 32 32 33 33 34 34 35 55*4882a593Smuzhiyun 35 36 36 37 37 38 38 39 56*4882a593Smuzhiyun 40 41 42 43 44 45 46 47 57*4882a593Smuzhiyun 48 49 50 51 52 53 54 55 58*4882a593Smuzhiyun 56 57 58 59 60 61 62 63 59*4882a593Smuzhiyun 64 65 66 67 68 69 70 71 60*4882a593Smuzhiyun 72 73 74 75 76 77 78 79 61*4882a593Smuzhiyun 80 81 82 83 84 85 86 87 62*4882a593Smuzhiyun 88 89 90 91 92 93 94 95 63*4882a593Smuzhiyun 96 97 98 99 100 101 102 103 64*4882a593Smuzhiyun 104 105 106 107 108 109 110 111 65*4882a593Smuzhiyun 112 113 114 115 116 117 118 119 66*4882a593Smuzhiyun 120 121 122 123 124 125 126 127 67*4882a593Smuzhiyun 128 129 130 131 132 133 134 135 68*4882a593Smuzhiyun 136 137 138 139 140 141 142 143 69*4882a593Smuzhiyun 144 145 146 147 148 149 150 151 70*4882a593Smuzhiyun 152 153 154 155 156 157 158 159 71*4882a593Smuzhiyun 160 161 162 163 164 165 166 167 72*4882a593Smuzhiyun 168 169 170 171 172 173 174 175 73*4882a593Smuzhiyun 176 177 178 179 180 181 182 183 74*4882a593Smuzhiyun 184 185 186 187 188 189 190 191 75*4882a593Smuzhiyun 192 193 194 195 196 197 198 199 76*4882a593Smuzhiyun 200 201 202 203 204 205 206 207 77*4882a593Smuzhiyun 208 209 210 211 212 213 214 215 78*4882a593Smuzhiyun 216 217 218 219 220 221 222 223 79*4882a593Smuzhiyun 224 225 226 227 228 229 230 231 80*4882a593Smuzhiyun 232 233 234 235 236 237 238 239 81*4882a593Smuzhiyun 240 241 242 243 244 245 246 247 82*4882a593Smuzhiyun 248 249 250 251 252 253 254 255 83*4882a593Smuzhiyun >; 84*4882a593Smuzhiyun default-brightness-level = <200>; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun dp0_sound: dp0-sound { 88*4882a593Smuzhiyun status = "disabled"; 89*4882a593Smuzhiyun compatible = "rockchip,hdmi"; 90*4882a593Smuzhiyun rockchip,card-name= "rockchip-dp0"; 91*4882a593Smuzhiyun rockchip,mclk-fs = <512>; 92*4882a593Smuzhiyun rockchip,cpu = <&spdif_tx2>; 93*4882a593Smuzhiyun rockchip,codec = <&dp0 1>; 94*4882a593Smuzhiyun rockchip,jack-det; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun hdmi0_sound: hdmi0-sound { 98*4882a593Smuzhiyun status = "disabled"; 99*4882a593Smuzhiyun compatible = "rockchip,hdmi"; 100*4882a593Smuzhiyun rockchip,mclk-fs = <128>; 101*4882a593Smuzhiyun rockchip,card-name = "rockchip-hdmi0"; 102*4882a593Smuzhiyun rockchip,cpu = <&i2s5_8ch>; 103*4882a593Smuzhiyun rockchip,codec = <&hdmi0>; 104*4882a593Smuzhiyun rockchip,jack-det; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun spdif_tx1_dc: spdif-tx1-dc { 108*4882a593Smuzhiyun status = "disabled"; 109*4882a593Smuzhiyun compatible = "linux,spdif-dit"; 110*4882a593Smuzhiyun #sound-dai-cells = <0>; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun spdif_tx1_sound: spdif-tx1-sound { 114*4882a593Smuzhiyun status = "disabled"; 115*4882a593Smuzhiyun compatible = "simple-audio-card"; 116*4882a593Smuzhiyun simple-audio-card,name = "rockchip,spdif-tx1"; 117*4882a593Smuzhiyun simple-audio-card,mclk-fs = <128>; 118*4882a593Smuzhiyun simple-audio-card,cpu { 119*4882a593Smuzhiyun sound-dai = <&spdif_tx1>; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun simple-audio-card,codec { 122*4882a593Smuzhiyun sound-dai = <&spdif_tx1_dc>; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun test-power { 127*4882a593Smuzhiyun status = "okay"; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun vcc12v_dcin: vcc12v-dcin { 131*4882a593Smuzhiyun compatible = "regulator-fixed"; 132*4882a593Smuzhiyun regulator-name = "vcc12v_dcin"; 133*4882a593Smuzhiyun regulator-always-on; 134*4882a593Smuzhiyun regulator-boot-on; 135*4882a593Smuzhiyun regulator-min-microvolt = <12000000>; 136*4882a593Smuzhiyun regulator-max-microvolt = <12000000>; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun vcc5v0_sys: vcc5v0-sys { 140*4882a593Smuzhiyun compatible = "regulator-fixed"; 141*4882a593Smuzhiyun regulator-name = "vcc5v0_sys"; 142*4882a593Smuzhiyun regulator-always-on; 143*4882a593Smuzhiyun regulator-boot-on; 144*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 145*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 146*4882a593Smuzhiyun vin-supply = <&vcc12v_dcin>; 147*4882a593Smuzhiyun }; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun vcc5v0_usbdcin: vcc5v0-usbdcin { 150*4882a593Smuzhiyun compatible = "regulator-fixed"; 151*4882a593Smuzhiyun regulator-name = "vcc5v0_usbdcin"; 152*4882a593Smuzhiyun regulator-always-on; 153*4882a593Smuzhiyun regulator-boot-on; 154*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 155*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 156*4882a593Smuzhiyun vin-supply = <&vcc12v_dcin>; 157*4882a593Smuzhiyun }; 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun vcc5v0_usb: vcc5v0-usb { 160*4882a593Smuzhiyun compatible = "regulator-fixed"; 161*4882a593Smuzhiyun regulator-name = "vcc5v0_usb"; 162*4882a593Smuzhiyun regulator-always-on; 163*4882a593Smuzhiyun regulator-boot-on; 164*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 165*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 166*4882a593Smuzhiyun vin-supply = <&vcc5v0_usbdcin>; 167*4882a593Smuzhiyun }; 168*4882a593Smuzhiyun}; 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun&av1d_mmu { 171*4882a593Smuzhiyun status = "okay"; 172*4882a593Smuzhiyun}; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun&combphy0_ps { 175*4882a593Smuzhiyun status = "okay"; 176*4882a593Smuzhiyun}; 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun&combphy2_psu { 179*4882a593Smuzhiyun status = "okay"; 180*4882a593Smuzhiyun}; 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun&cpu_l0 { 183*4882a593Smuzhiyun cpu-supply = <&vdd_cpu_lit_s0>; 184*4882a593Smuzhiyun mem-supply = <&vdd_cpu_lit_mem_s0>; 185*4882a593Smuzhiyun}; 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun&cpu_b0 { 188*4882a593Smuzhiyun cpu-supply = <&vdd_cpu_big0_s0>; 189*4882a593Smuzhiyun mem-supply = <&vdd_cpu_big0_mem_s0>; 190*4882a593Smuzhiyun}; 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun&cpu_b2 { 193*4882a593Smuzhiyun cpu-supply = <&vdd_cpu_big1_s0>; 194*4882a593Smuzhiyun mem-supply = <&vdd_cpu_big1_mem_s0>; 195*4882a593Smuzhiyun}; 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun&dsi0 { 198*4882a593Smuzhiyun status = "disabled"; 199*4882a593Smuzhiyun //rockchip,lane-rate = <1000>; 200*4882a593Smuzhiyun dsi0_panel: panel@0 { 201*4882a593Smuzhiyun status = "okay"; 202*4882a593Smuzhiyun compatible = "simple-panel-dsi"; 203*4882a593Smuzhiyun reg = <0>; 204*4882a593Smuzhiyun backlight = <&backlight>; 205*4882a593Smuzhiyun reset-delay-ms = <60>; 206*4882a593Smuzhiyun enable-delay-ms = <60>; 207*4882a593Smuzhiyun prepare-delay-ms = <60>; 208*4882a593Smuzhiyun unprepare-delay-ms = <60>; 209*4882a593Smuzhiyun disable-delay-ms = <60>; 210*4882a593Smuzhiyun dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 211*4882a593Smuzhiyun MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; 212*4882a593Smuzhiyun dsi,format = <MIPI_DSI_FMT_RGB888>; 213*4882a593Smuzhiyun dsi,lanes = <4>; 214*4882a593Smuzhiyun panel-init-sequence = [ 215*4882a593Smuzhiyun 23 00 02 FE 21 216*4882a593Smuzhiyun 23 00 02 04 00 217*4882a593Smuzhiyun 23 00 02 00 64 218*4882a593Smuzhiyun 23 00 02 2A 00 219*4882a593Smuzhiyun 23 00 02 26 64 220*4882a593Smuzhiyun 23 00 02 54 00 221*4882a593Smuzhiyun 23 00 02 50 64 222*4882a593Smuzhiyun 23 00 02 7B 00 223*4882a593Smuzhiyun 23 00 02 77 64 224*4882a593Smuzhiyun 23 00 02 A2 00 225*4882a593Smuzhiyun 23 00 02 9D 64 226*4882a593Smuzhiyun 23 00 02 C9 00 227*4882a593Smuzhiyun 23 00 02 C5 64 228*4882a593Smuzhiyun 23 00 02 01 71 229*4882a593Smuzhiyun 23 00 02 27 71 230*4882a593Smuzhiyun 23 00 02 51 71 231*4882a593Smuzhiyun 23 00 02 78 71 232*4882a593Smuzhiyun 23 00 02 9E 71 233*4882a593Smuzhiyun 23 00 02 C6 71 234*4882a593Smuzhiyun 23 00 02 02 89 235*4882a593Smuzhiyun 23 00 02 28 89 236*4882a593Smuzhiyun 23 00 02 52 89 237*4882a593Smuzhiyun 23 00 02 79 89 238*4882a593Smuzhiyun 23 00 02 9F 89 239*4882a593Smuzhiyun 23 00 02 C7 89 240*4882a593Smuzhiyun 23 00 02 03 9E 241*4882a593Smuzhiyun 23 00 02 29 9E 242*4882a593Smuzhiyun 23 00 02 53 9E 243*4882a593Smuzhiyun 23 00 02 7A 9E 244*4882a593Smuzhiyun 23 00 02 A0 9E 245*4882a593Smuzhiyun 23 00 02 C8 9E 246*4882a593Smuzhiyun 23 00 02 09 00 247*4882a593Smuzhiyun 23 00 02 05 B0 248*4882a593Smuzhiyun 23 00 02 31 00 249*4882a593Smuzhiyun 23 00 02 2B B0 250*4882a593Smuzhiyun 23 00 02 5A 00 251*4882a593Smuzhiyun 23 00 02 55 B0 252*4882a593Smuzhiyun 23 00 02 80 00 253*4882a593Smuzhiyun 23 00 02 7C B0 254*4882a593Smuzhiyun 23 00 02 A7 00 255*4882a593Smuzhiyun 23 00 02 A3 B0 256*4882a593Smuzhiyun 23 00 02 CE 00 257*4882a593Smuzhiyun 23 00 02 CA B0 258*4882a593Smuzhiyun 23 00 02 06 C0 259*4882a593Smuzhiyun 23 00 02 2D C0 260*4882a593Smuzhiyun 23 00 02 56 C0 261*4882a593Smuzhiyun 23 00 02 7D C0 262*4882a593Smuzhiyun 23 00 02 A4 C0 263*4882a593Smuzhiyun 23 00 02 CB C0 264*4882a593Smuzhiyun 23 00 02 07 CF 265*4882a593Smuzhiyun 23 00 02 2F CF 266*4882a593Smuzhiyun 23 00 02 58 CF 267*4882a593Smuzhiyun 23 00 02 7E CF 268*4882a593Smuzhiyun 23 00 02 A5 CF 269*4882a593Smuzhiyun 23 00 02 CC CF 270*4882a593Smuzhiyun 23 00 02 08 DD 271*4882a593Smuzhiyun 23 00 02 30 DD 272*4882a593Smuzhiyun 23 00 02 59 DD 273*4882a593Smuzhiyun 23 00 02 7F DD 274*4882a593Smuzhiyun 23 00 02 A6 DD 275*4882a593Smuzhiyun 23 00 02 CD DD 276*4882a593Smuzhiyun 23 00 02 0E 15 277*4882a593Smuzhiyun 23 00 02 0A E9 278*4882a593Smuzhiyun 23 00 02 36 15 279*4882a593Smuzhiyun 23 00 02 32 E9 280*4882a593Smuzhiyun 23 00 02 5F 15 281*4882a593Smuzhiyun 23 00 02 5B E9 282*4882a593Smuzhiyun 23 00 02 85 15 283*4882a593Smuzhiyun 23 00 02 81 E9 284*4882a593Smuzhiyun 23 00 02 AD 15 285*4882a593Smuzhiyun 23 00 02 A9 E9 286*4882a593Smuzhiyun 23 00 02 D3 15 287*4882a593Smuzhiyun 23 00 02 CF E9 288*4882a593Smuzhiyun 23 00 02 0B 14 289*4882a593Smuzhiyun 23 00 02 33 14 290*4882a593Smuzhiyun 23 00 02 5C 14 291*4882a593Smuzhiyun 23 00 02 82 14 292*4882a593Smuzhiyun 23 00 02 AA 14 293*4882a593Smuzhiyun 23 00 02 D0 14 294*4882a593Smuzhiyun 23 00 02 0C 36 295*4882a593Smuzhiyun 23 00 02 34 36 296*4882a593Smuzhiyun 23 00 02 5D 36 297*4882a593Smuzhiyun 23 00 02 83 36 298*4882a593Smuzhiyun 23 00 02 AB 36 299*4882a593Smuzhiyun 23 00 02 D1 36 300*4882a593Smuzhiyun 23 00 02 0D 6B 301*4882a593Smuzhiyun 23 00 02 35 6B 302*4882a593Smuzhiyun 23 00 02 5E 6B 303*4882a593Smuzhiyun 23 00 02 84 6B 304*4882a593Smuzhiyun 23 00 02 AC 6B 305*4882a593Smuzhiyun 23 00 02 D2 6B 306*4882a593Smuzhiyun 23 00 02 13 5A 307*4882a593Smuzhiyun 23 00 02 0F 94 308*4882a593Smuzhiyun 23 00 02 3B 5A 309*4882a593Smuzhiyun 23 00 02 37 94 310*4882a593Smuzhiyun 23 00 02 64 5A 311*4882a593Smuzhiyun 23 00 02 60 94 312*4882a593Smuzhiyun 23 00 02 8A 5A 313*4882a593Smuzhiyun 23 00 02 86 94 314*4882a593Smuzhiyun 23 00 02 B2 5A 315*4882a593Smuzhiyun 23 00 02 AE 94 316*4882a593Smuzhiyun 23 00 02 D8 5A 317*4882a593Smuzhiyun 23 00 02 D4 94 318*4882a593Smuzhiyun 23 00 02 10 D1 319*4882a593Smuzhiyun 23 00 02 38 D1 320*4882a593Smuzhiyun 23 00 02 61 D1 321*4882a593Smuzhiyun 23 00 02 87 D1 322*4882a593Smuzhiyun 23 00 02 AF D1 323*4882a593Smuzhiyun 23 00 02 D5 D1 324*4882a593Smuzhiyun 23 00 02 11 04 325*4882a593Smuzhiyun 23 00 02 39 04 326*4882a593Smuzhiyun 23 00 02 62 04 327*4882a593Smuzhiyun 23 00 02 88 04 328*4882a593Smuzhiyun 23 00 02 B0 04 329*4882a593Smuzhiyun 23 00 02 D6 04 330*4882a593Smuzhiyun 23 00 02 12 05 331*4882a593Smuzhiyun 23 00 02 3A 05 332*4882a593Smuzhiyun 23 00 02 63 05 333*4882a593Smuzhiyun 23 00 02 89 05 334*4882a593Smuzhiyun 23 00 02 B1 05 335*4882a593Smuzhiyun 23 00 02 D7 05 336*4882a593Smuzhiyun 23 00 02 18 AA 337*4882a593Smuzhiyun 23 00 02 14 36 338*4882a593Smuzhiyun 23 00 02 42 AA 339*4882a593Smuzhiyun 23 00 02 3D 36 340*4882a593Smuzhiyun 23 00 02 69 AA 341*4882a593Smuzhiyun 23 00 02 65 36 342*4882a593Smuzhiyun 23 00 02 8F AA 343*4882a593Smuzhiyun 23 00 02 8B 36 344*4882a593Smuzhiyun 23 00 02 B7 AA 345*4882a593Smuzhiyun 23 00 02 B3 36 346*4882a593Smuzhiyun 23 00 02 DD AA 347*4882a593Smuzhiyun 23 00 02 D9 36 348*4882a593Smuzhiyun 23 00 02 15 74 349*4882a593Smuzhiyun 23 00 02 3F 74 350*4882a593Smuzhiyun 23 00 02 66 74 351*4882a593Smuzhiyun 23 00 02 8C 74 352*4882a593Smuzhiyun 23 00 02 B4 74 353*4882a593Smuzhiyun 23 00 02 DA 74 354*4882a593Smuzhiyun 23 00 02 16 9F 355*4882a593Smuzhiyun 23 00 02 40 9F 356*4882a593Smuzhiyun 23 00 02 67 9F 357*4882a593Smuzhiyun 23 00 02 8D 9F 358*4882a593Smuzhiyun 23 00 02 B5 9F 359*4882a593Smuzhiyun 23 00 02 DB 9F 360*4882a593Smuzhiyun 23 00 02 17 DC 361*4882a593Smuzhiyun 23 00 02 41 DC 362*4882a593Smuzhiyun 23 00 02 68 DC 363*4882a593Smuzhiyun 23 00 02 8E DC 364*4882a593Smuzhiyun 23 00 02 B6 DC 365*4882a593Smuzhiyun 23 00 02 DC DC 366*4882a593Smuzhiyun 23 00 02 1D FF 367*4882a593Smuzhiyun 23 00 02 19 03 368*4882a593Smuzhiyun 23 00 02 47 FF 369*4882a593Smuzhiyun 23 00 02 43 03 370*4882a593Smuzhiyun 23 00 02 6E FF 371*4882a593Smuzhiyun 23 00 02 6A 03 372*4882a593Smuzhiyun 23 00 02 94 FF 373*4882a593Smuzhiyun 23 00 02 90 03 374*4882a593Smuzhiyun 23 00 02 BC FF 375*4882a593Smuzhiyun 23 00 02 B8 03 376*4882a593Smuzhiyun 23 00 02 E2 FF 377*4882a593Smuzhiyun 23 00 02 DE 03 378*4882a593Smuzhiyun 23 00 02 1A 35 379*4882a593Smuzhiyun 23 00 02 44 35 380*4882a593Smuzhiyun 23 00 02 6B 35 381*4882a593Smuzhiyun 23 00 02 91 35 382*4882a593Smuzhiyun 23 00 02 B9 35 383*4882a593Smuzhiyun 23 00 02 DF 35 384*4882a593Smuzhiyun 23 00 02 1B 45 385*4882a593Smuzhiyun 23 00 02 45 45 386*4882a593Smuzhiyun 23 00 02 6C 45 387*4882a593Smuzhiyun 23 00 02 92 45 388*4882a593Smuzhiyun 23 00 02 BA 45 389*4882a593Smuzhiyun 23 00 02 E0 45 390*4882a593Smuzhiyun 23 00 02 1C 55 391*4882a593Smuzhiyun 23 00 02 46 55 392*4882a593Smuzhiyun 23 00 02 6D 55 393*4882a593Smuzhiyun 23 00 02 93 55 394*4882a593Smuzhiyun 23 00 02 BB 55 395*4882a593Smuzhiyun 23 00 02 E1 55 396*4882a593Smuzhiyun 23 00 02 22 FF 397*4882a593Smuzhiyun 23 00 02 1E 68 398*4882a593Smuzhiyun 23 00 02 4C FF 399*4882a593Smuzhiyun 23 00 02 48 68 400*4882a593Smuzhiyun 23 00 02 73 FF 401*4882a593Smuzhiyun 23 00 02 6F 68 402*4882a593Smuzhiyun 23 00 02 99 FF 403*4882a593Smuzhiyun 23 00 02 95 68 404*4882a593Smuzhiyun 23 00 02 C1 FF 405*4882a593Smuzhiyun 23 00 02 BD 68 406*4882a593Smuzhiyun 23 00 02 E7 FF 407*4882a593Smuzhiyun 23 00 02 E3 68 408*4882a593Smuzhiyun 23 00 02 1F 7E 409*4882a593Smuzhiyun 23 00 02 49 7E 410*4882a593Smuzhiyun 23 00 02 70 7E 411*4882a593Smuzhiyun 23 00 02 96 7E 412*4882a593Smuzhiyun 23 00 02 BE 7E 413*4882a593Smuzhiyun 23 00 02 E4 7E 414*4882a593Smuzhiyun 23 00 02 20 97 415*4882a593Smuzhiyun 23 00 02 4A 97 416*4882a593Smuzhiyun 23 00 02 71 97 417*4882a593Smuzhiyun 23 00 02 97 97 418*4882a593Smuzhiyun 23 00 02 BF 97 419*4882a593Smuzhiyun 23 00 02 E5 97 420*4882a593Smuzhiyun 23 00 02 21 B5 421*4882a593Smuzhiyun 23 00 02 4B B5 422*4882a593Smuzhiyun 23 00 02 72 B5 423*4882a593Smuzhiyun 23 00 02 98 B5 424*4882a593Smuzhiyun 23 00 02 C0 B5 425*4882a593Smuzhiyun 23 00 02 E6 B5 426*4882a593Smuzhiyun 23 00 02 25 F0 427*4882a593Smuzhiyun 23 00 02 23 E8 428*4882a593Smuzhiyun 23 00 02 4F F0 429*4882a593Smuzhiyun 23 00 02 4D E8 430*4882a593Smuzhiyun 23 00 02 76 F0 431*4882a593Smuzhiyun 23 00 02 74 E8 432*4882a593Smuzhiyun 23 00 02 9C F0 433*4882a593Smuzhiyun 23 00 02 9A E8 434*4882a593Smuzhiyun 23 00 02 C4 F0 435*4882a593Smuzhiyun 23 00 02 C2 E8 436*4882a593Smuzhiyun 23 00 02 EA F0 437*4882a593Smuzhiyun 23 00 02 E8 E8 438*4882a593Smuzhiyun 23 00 02 24 FF 439*4882a593Smuzhiyun 23 00 02 4E FF 440*4882a593Smuzhiyun 23 00 02 75 FF 441*4882a593Smuzhiyun 23 00 02 9B FF 442*4882a593Smuzhiyun 23 00 02 C3 FF 443*4882a593Smuzhiyun 23 00 02 E9 FF 444*4882a593Smuzhiyun 23 00 02 FE 3D 445*4882a593Smuzhiyun 23 00 02 00 04 446*4882a593Smuzhiyun 23 00 02 FE 23 447*4882a593Smuzhiyun 23 00 02 08 82 448*4882a593Smuzhiyun 23 00 02 0A 00 449*4882a593Smuzhiyun 23 00 02 0B 00 450*4882a593Smuzhiyun 23 00 02 0C 01 451*4882a593Smuzhiyun 23 00 02 16 00 452*4882a593Smuzhiyun 23 00 02 18 02 453*4882a593Smuzhiyun 23 00 02 1B 04 454*4882a593Smuzhiyun 23 00 02 19 04 455*4882a593Smuzhiyun 23 00 02 1C 81 456*4882a593Smuzhiyun 23 00 02 1F 00 457*4882a593Smuzhiyun 23 00 02 20 03 458*4882a593Smuzhiyun 23 00 02 23 04 459*4882a593Smuzhiyun 23 00 02 21 01 460*4882a593Smuzhiyun 23 00 02 54 63 461*4882a593Smuzhiyun 23 00 02 55 54 462*4882a593Smuzhiyun 23 00 02 6E 45 463*4882a593Smuzhiyun 23 00 02 6D 36 464*4882a593Smuzhiyun 23 00 02 FE 3D 465*4882a593Smuzhiyun 23 00 02 55 78 466*4882a593Smuzhiyun 23 00 02 FE 20 467*4882a593Smuzhiyun 23 00 02 26 30 468*4882a593Smuzhiyun 23 00 02 FE 3D 469*4882a593Smuzhiyun 23 00 02 20 71 470*4882a593Smuzhiyun 23 00 02 50 8F 471*4882a593Smuzhiyun 23 00 02 51 8F 472*4882a593Smuzhiyun 23 00 02 FE 00 473*4882a593Smuzhiyun 23 00 02 35 00 474*4882a593Smuzhiyun 05 78 01 11 475*4882a593Smuzhiyun 05 1E 01 29 476*4882a593Smuzhiyun ]; 477*4882a593Smuzhiyun 478*4882a593Smuzhiyun panel-exit-sequence = [ 479*4882a593Smuzhiyun 05 00 01 28 480*4882a593Smuzhiyun 05 00 01 10 481*4882a593Smuzhiyun ]; 482*4882a593Smuzhiyun 483*4882a593Smuzhiyun disp_timings0: display-timings { 484*4882a593Smuzhiyun native-mode = <&dsi0_timing0>; 485*4882a593Smuzhiyun dsi0_timing0: timing0 { 486*4882a593Smuzhiyun clock-frequency = <132000000>; 487*4882a593Smuzhiyun hactive = <1080>; 488*4882a593Smuzhiyun vactive = <1920>; 489*4882a593Smuzhiyun hfront-porch = <15>; 490*4882a593Smuzhiyun hsync-len = <4>; 491*4882a593Smuzhiyun hback-porch = <30>; 492*4882a593Smuzhiyun vfront-porch = <15>; 493*4882a593Smuzhiyun vsync-len = <2>; 494*4882a593Smuzhiyun vback-porch = <15>; 495*4882a593Smuzhiyun hsync-active = <0>; 496*4882a593Smuzhiyun vsync-active = <0>; 497*4882a593Smuzhiyun de-active = <0>; 498*4882a593Smuzhiyun pixelclk-active = <0>; 499*4882a593Smuzhiyun }; 500*4882a593Smuzhiyun }; 501*4882a593Smuzhiyun 502*4882a593Smuzhiyun ports { 503*4882a593Smuzhiyun #address-cells = <1>; 504*4882a593Smuzhiyun #size-cells = <0>; 505*4882a593Smuzhiyun 506*4882a593Smuzhiyun port@0 { 507*4882a593Smuzhiyun reg = <0>; 508*4882a593Smuzhiyun panel_in_dsi: endpoint { 509*4882a593Smuzhiyun remote-endpoint = <&dsi_out_panel>; 510*4882a593Smuzhiyun }; 511*4882a593Smuzhiyun }; 512*4882a593Smuzhiyun }; 513*4882a593Smuzhiyun }; 514*4882a593Smuzhiyun 515*4882a593Smuzhiyun ports { 516*4882a593Smuzhiyun #address-cells = <1>; 517*4882a593Smuzhiyun #size-cells = <0>; 518*4882a593Smuzhiyun 519*4882a593Smuzhiyun port@1 { 520*4882a593Smuzhiyun reg = <1>; 521*4882a593Smuzhiyun dsi_out_panel: endpoint { 522*4882a593Smuzhiyun remote-endpoint = <&panel_in_dsi>; 523*4882a593Smuzhiyun }; 524*4882a593Smuzhiyun }; 525*4882a593Smuzhiyun }; 526*4882a593Smuzhiyun 527*4882a593Smuzhiyun}; 528*4882a593Smuzhiyun 529*4882a593Smuzhiyun&dsi1 { 530*4882a593Smuzhiyun status = "disabled"; 531*4882a593Smuzhiyun //rockchip,lane-rate = <1000>; 532*4882a593Smuzhiyun dsi1_panel: panel@0 { 533*4882a593Smuzhiyun status = "okay"; 534*4882a593Smuzhiyun compatible = "simple-panel-dsi"; 535*4882a593Smuzhiyun reg = <0>; 536*4882a593Smuzhiyun backlight = <&backlight>; 537*4882a593Smuzhiyun reset-delay-ms = <60>; 538*4882a593Smuzhiyun enable-delay-ms = <60>; 539*4882a593Smuzhiyun prepare-delay-ms = <60>; 540*4882a593Smuzhiyun unprepare-delay-ms = <60>; 541*4882a593Smuzhiyun disable-delay-ms = <60>; 542*4882a593Smuzhiyun dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 543*4882a593Smuzhiyun MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; 544*4882a593Smuzhiyun dsi,format = <MIPI_DSI_FMT_RGB888>; 545*4882a593Smuzhiyun dsi,lanes = <4>; 546*4882a593Smuzhiyun panel-init-sequence = [ 547*4882a593Smuzhiyun 23 00 02 FE 21 548*4882a593Smuzhiyun 23 00 02 04 00 549*4882a593Smuzhiyun 23 00 02 00 64 550*4882a593Smuzhiyun 23 00 02 2A 00 551*4882a593Smuzhiyun 23 00 02 26 64 552*4882a593Smuzhiyun 23 00 02 54 00 553*4882a593Smuzhiyun 23 00 02 50 64 554*4882a593Smuzhiyun 23 00 02 7B 00 555*4882a593Smuzhiyun 23 00 02 77 64 556*4882a593Smuzhiyun 23 00 02 A2 00 557*4882a593Smuzhiyun 23 00 02 9D 64 558*4882a593Smuzhiyun 23 00 02 C9 00 559*4882a593Smuzhiyun 23 00 02 C5 64 560*4882a593Smuzhiyun 23 00 02 01 71 561*4882a593Smuzhiyun 23 00 02 27 71 562*4882a593Smuzhiyun 23 00 02 51 71 563*4882a593Smuzhiyun 23 00 02 78 71 564*4882a593Smuzhiyun 23 00 02 9E 71 565*4882a593Smuzhiyun 23 00 02 C6 71 566*4882a593Smuzhiyun 23 00 02 02 89 567*4882a593Smuzhiyun 23 00 02 28 89 568*4882a593Smuzhiyun 23 00 02 52 89 569*4882a593Smuzhiyun 23 00 02 79 89 570*4882a593Smuzhiyun 23 00 02 9F 89 571*4882a593Smuzhiyun 23 00 02 C7 89 572*4882a593Smuzhiyun 23 00 02 03 9E 573*4882a593Smuzhiyun 23 00 02 29 9E 574*4882a593Smuzhiyun 23 00 02 53 9E 575*4882a593Smuzhiyun 23 00 02 7A 9E 576*4882a593Smuzhiyun 23 00 02 A0 9E 577*4882a593Smuzhiyun 23 00 02 C8 9E 578*4882a593Smuzhiyun 23 00 02 09 00 579*4882a593Smuzhiyun 23 00 02 05 B0 580*4882a593Smuzhiyun 23 00 02 31 00 581*4882a593Smuzhiyun 23 00 02 2B B0 582*4882a593Smuzhiyun 23 00 02 5A 00 583*4882a593Smuzhiyun 23 00 02 55 B0 584*4882a593Smuzhiyun 23 00 02 80 00 585*4882a593Smuzhiyun 23 00 02 7C B0 586*4882a593Smuzhiyun 23 00 02 A7 00 587*4882a593Smuzhiyun 23 00 02 A3 B0 588*4882a593Smuzhiyun 23 00 02 CE 00 589*4882a593Smuzhiyun 23 00 02 CA B0 590*4882a593Smuzhiyun 23 00 02 06 C0 591*4882a593Smuzhiyun 23 00 02 2D C0 592*4882a593Smuzhiyun 23 00 02 56 C0 593*4882a593Smuzhiyun 23 00 02 7D C0 594*4882a593Smuzhiyun 23 00 02 A4 C0 595*4882a593Smuzhiyun 23 00 02 CB C0 596*4882a593Smuzhiyun 23 00 02 07 CF 597*4882a593Smuzhiyun 23 00 02 2F CF 598*4882a593Smuzhiyun 23 00 02 58 CF 599*4882a593Smuzhiyun 23 00 02 7E CF 600*4882a593Smuzhiyun 23 00 02 A5 CF 601*4882a593Smuzhiyun 23 00 02 CC CF 602*4882a593Smuzhiyun 23 00 02 08 DD 603*4882a593Smuzhiyun 23 00 02 30 DD 604*4882a593Smuzhiyun 23 00 02 59 DD 605*4882a593Smuzhiyun 23 00 02 7F DD 606*4882a593Smuzhiyun 23 00 02 A6 DD 607*4882a593Smuzhiyun 23 00 02 CD DD 608*4882a593Smuzhiyun 23 00 02 0E 15 609*4882a593Smuzhiyun 23 00 02 0A E9 610*4882a593Smuzhiyun 23 00 02 36 15 611*4882a593Smuzhiyun 23 00 02 32 E9 612*4882a593Smuzhiyun 23 00 02 5F 15 613*4882a593Smuzhiyun 23 00 02 5B E9 614*4882a593Smuzhiyun 23 00 02 85 15 615*4882a593Smuzhiyun 23 00 02 81 E9 616*4882a593Smuzhiyun 23 00 02 AD 15 617*4882a593Smuzhiyun 23 00 02 A9 E9 618*4882a593Smuzhiyun 23 00 02 D3 15 619*4882a593Smuzhiyun 23 00 02 CF E9 620*4882a593Smuzhiyun 23 00 02 0B 14 621*4882a593Smuzhiyun 23 00 02 33 14 622*4882a593Smuzhiyun 23 00 02 5C 14 623*4882a593Smuzhiyun 23 00 02 82 14 624*4882a593Smuzhiyun 23 00 02 AA 14 625*4882a593Smuzhiyun 23 00 02 D0 14 626*4882a593Smuzhiyun 23 00 02 0C 36 627*4882a593Smuzhiyun 23 00 02 34 36 628*4882a593Smuzhiyun 23 00 02 5D 36 629*4882a593Smuzhiyun 23 00 02 83 36 630*4882a593Smuzhiyun 23 00 02 AB 36 631*4882a593Smuzhiyun 23 00 02 D1 36 632*4882a593Smuzhiyun 23 00 02 0D 6B 633*4882a593Smuzhiyun 23 00 02 35 6B 634*4882a593Smuzhiyun 23 00 02 5E 6B 635*4882a593Smuzhiyun 23 00 02 84 6B 636*4882a593Smuzhiyun 23 00 02 AC 6B 637*4882a593Smuzhiyun 23 00 02 D2 6B 638*4882a593Smuzhiyun 23 00 02 13 5A 639*4882a593Smuzhiyun 23 00 02 0F 94 640*4882a593Smuzhiyun 23 00 02 3B 5A 641*4882a593Smuzhiyun 23 00 02 37 94 642*4882a593Smuzhiyun 23 00 02 64 5A 643*4882a593Smuzhiyun 23 00 02 60 94 644*4882a593Smuzhiyun 23 00 02 8A 5A 645*4882a593Smuzhiyun 23 00 02 86 94 646*4882a593Smuzhiyun 23 00 02 B2 5A 647*4882a593Smuzhiyun 23 00 02 AE 94 648*4882a593Smuzhiyun 23 00 02 D8 5A 649*4882a593Smuzhiyun 23 00 02 D4 94 650*4882a593Smuzhiyun 23 00 02 10 D1 651*4882a593Smuzhiyun 23 00 02 38 D1 652*4882a593Smuzhiyun 23 00 02 61 D1 653*4882a593Smuzhiyun 23 00 02 87 D1 654*4882a593Smuzhiyun 23 00 02 AF D1 655*4882a593Smuzhiyun 23 00 02 D5 D1 656*4882a593Smuzhiyun 23 00 02 11 04 657*4882a593Smuzhiyun 23 00 02 39 04 658*4882a593Smuzhiyun 23 00 02 62 04 659*4882a593Smuzhiyun 23 00 02 88 04 660*4882a593Smuzhiyun 23 00 02 B0 04 661*4882a593Smuzhiyun 23 00 02 D6 04 662*4882a593Smuzhiyun 23 00 02 12 05 663*4882a593Smuzhiyun 23 00 02 3A 05 664*4882a593Smuzhiyun 23 00 02 63 05 665*4882a593Smuzhiyun 23 00 02 89 05 666*4882a593Smuzhiyun 23 00 02 B1 05 667*4882a593Smuzhiyun 23 00 02 D7 05 668*4882a593Smuzhiyun 23 00 02 18 AA 669*4882a593Smuzhiyun 23 00 02 14 36 670*4882a593Smuzhiyun 23 00 02 42 AA 671*4882a593Smuzhiyun 23 00 02 3D 36 672*4882a593Smuzhiyun 23 00 02 69 AA 673*4882a593Smuzhiyun 23 00 02 65 36 674*4882a593Smuzhiyun 23 00 02 8F AA 675*4882a593Smuzhiyun 23 00 02 8B 36 676*4882a593Smuzhiyun 23 00 02 B7 AA 677*4882a593Smuzhiyun 23 00 02 B3 36 678*4882a593Smuzhiyun 23 00 02 DD AA 679*4882a593Smuzhiyun 23 00 02 D9 36 680*4882a593Smuzhiyun 23 00 02 15 74 681*4882a593Smuzhiyun 23 00 02 3F 74 682*4882a593Smuzhiyun 23 00 02 66 74 683*4882a593Smuzhiyun 23 00 02 8C 74 684*4882a593Smuzhiyun 23 00 02 B4 74 685*4882a593Smuzhiyun 23 00 02 DA 74 686*4882a593Smuzhiyun 23 00 02 16 9F 687*4882a593Smuzhiyun 23 00 02 40 9F 688*4882a593Smuzhiyun 23 00 02 67 9F 689*4882a593Smuzhiyun 23 00 02 8D 9F 690*4882a593Smuzhiyun 23 00 02 B5 9F 691*4882a593Smuzhiyun 23 00 02 DB 9F 692*4882a593Smuzhiyun 23 00 02 17 DC 693*4882a593Smuzhiyun 23 00 02 41 DC 694*4882a593Smuzhiyun 23 00 02 68 DC 695*4882a593Smuzhiyun 23 00 02 8E DC 696*4882a593Smuzhiyun 23 00 02 B6 DC 697*4882a593Smuzhiyun 23 00 02 DC DC 698*4882a593Smuzhiyun 23 00 02 1D FF 699*4882a593Smuzhiyun 23 00 02 19 03 700*4882a593Smuzhiyun 23 00 02 47 FF 701*4882a593Smuzhiyun 23 00 02 43 03 702*4882a593Smuzhiyun 23 00 02 6E FF 703*4882a593Smuzhiyun 23 00 02 6A 03 704*4882a593Smuzhiyun 23 00 02 94 FF 705*4882a593Smuzhiyun 23 00 02 90 03 706*4882a593Smuzhiyun 23 00 02 BC FF 707*4882a593Smuzhiyun 23 00 02 B8 03 708*4882a593Smuzhiyun 23 00 02 E2 FF 709*4882a593Smuzhiyun 23 00 02 DE 03 710*4882a593Smuzhiyun 23 00 02 1A 35 711*4882a593Smuzhiyun 23 00 02 44 35 712*4882a593Smuzhiyun 23 00 02 6B 35 713*4882a593Smuzhiyun 23 00 02 91 35 714*4882a593Smuzhiyun 23 00 02 B9 35 715*4882a593Smuzhiyun 23 00 02 DF 35 716*4882a593Smuzhiyun 23 00 02 1B 45 717*4882a593Smuzhiyun 23 00 02 45 45 718*4882a593Smuzhiyun 23 00 02 6C 45 719*4882a593Smuzhiyun 23 00 02 92 45 720*4882a593Smuzhiyun 23 00 02 BA 45 721*4882a593Smuzhiyun 23 00 02 E0 45 722*4882a593Smuzhiyun 23 00 02 1C 55 723*4882a593Smuzhiyun 23 00 02 46 55 724*4882a593Smuzhiyun 23 00 02 6D 55 725*4882a593Smuzhiyun 23 00 02 93 55 726*4882a593Smuzhiyun 23 00 02 BB 55 727*4882a593Smuzhiyun 23 00 02 E1 55 728*4882a593Smuzhiyun 23 00 02 22 FF 729*4882a593Smuzhiyun 23 00 02 1E 68 730*4882a593Smuzhiyun 23 00 02 4C FF 731*4882a593Smuzhiyun 23 00 02 48 68 732*4882a593Smuzhiyun 23 00 02 73 FF 733*4882a593Smuzhiyun 23 00 02 6F 68 734*4882a593Smuzhiyun 23 00 02 99 FF 735*4882a593Smuzhiyun 23 00 02 95 68 736*4882a593Smuzhiyun 23 00 02 C1 FF 737*4882a593Smuzhiyun 23 00 02 BD 68 738*4882a593Smuzhiyun 23 00 02 E7 FF 739*4882a593Smuzhiyun 23 00 02 E3 68 740*4882a593Smuzhiyun 23 00 02 1F 7E 741*4882a593Smuzhiyun 23 00 02 49 7E 742*4882a593Smuzhiyun 23 00 02 70 7E 743*4882a593Smuzhiyun 23 00 02 96 7E 744*4882a593Smuzhiyun 23 00 02 BE 7E 745*4882a593Smuzhiyun 23 00 02 E4 7E 746*4882a593Smuzhiyun 23 00 02 20 97 747*4882a593Smuzhiyun 23 00 02 4A 97 748*4882a593Smuzhiyun 23 00 02 71 97 749*4882a593Smuzhiyun 23 00 02 97 97 750*4882a593Smuzhiyun 23 00 02 BF 97 751*4882a593Smuzhiyun 23 00 02 E5 97 752*4882a593Smuzhiyun 23 00 02 21 B5 753*4882a593Smuzhiyun 23 00 02 4B B5 754*4882a593Smuzhiyun 23 00 02 72 B5 755*4882a593Smuzhiyun 23 00 02 98 B5 756*4882a593Smuzhiyun 23 00 02 C0 B5 757*4882a593Smuzhiyun 23 00 02 E6 B5 758*4882a593Smuzhiyun 23 00 02 25 F0 759*4882a593Smuzhiyun 23 00 02 23 E8 760*4882a593Smuzhiyun 23 00 02 4F F0 761*4882a593Smuzhiyun 23 00 02 4D E8 762*4882a593Smuzhiyun 23 00 02 76 F0 763*4882a593Smuzhiyun 23 00 02 74 E8 764*4882a593Smuzhiyun 23 00 02 9C F0 765*4882a593Smuzhiyun 23 00 02 9A E8 766*4882a593Smuzhiyun 23 00 02 C4 F0 767*4882a593Smuzhiyun 23 00 02 C2 E8 768*4882a593Smuzhiyun 23 00 02 EA F0 769*4882a593Smuzhiyun 23 00 02 E8 E8 770*4882a593Smuzhiyun 23 00 02 24 FF 771*4882a593Smuzhiyun 23 00 02 4E FF 772*4882a593Smuzhiyun 23 00 02 75 FF 773*4882a593Smuzhiyun 23 00 02 9B FF 774*4882a593Smuzhiyun 23 00 02 C3 FF 775*4882a593Smuzhiyun 23 00 02 E9 FF 776*4882a593Smuzhiyun 23 00 02 FE 3D 777*4882a593Smuzhiyun 23 00 02 00 04 778*4882a593Smuzhiyun 23 00 02 FE 23 779*4882a593Smuzhiyun 23 00 02 08 82 780*4882a593Smuzhiyun 23 00 02 0A 00 781*4882a593Smuzhiyun 23 00 02 0B 00 782*4882a593Smuzhiyun 23 00 02 0C 01 783*4882a593Smuzhiyun 23 00 02 16 00 784*4882a593Smuzhiyun 23 00 02 18 02 785*4882a593Smuzhiyun 23 00 02 1B 04 786*4882a593Smuzhiyun 23 00 02 19 04 787*4882a593Smuzhiyun 23 00 02 1C 81 788*4882a593Smuzhiyun 23 00 02 1F 00 789*4882a593Smuzhiyun 23 00 02 20 03 790*4882a593Smuzhiyun 23 00 02 23 04 791*4882a593Smuzhiyun 23 00 02 21 01 792*4882a593Smuzhiyun 23 00 02 54 63 793*4882a593Smuzhiyun 23 00 02 55 54 794*4882a593Smuzhiyun 23 00 02 6E 45 795*4882a593Smuzhiyun 23 00 02 6D 36 796*4882a593Smuzhiyun 23 00 02 FE 3D 797*4882a593Smuzhiyun 23 00 02 55 78 798*4882a593Smuzhiyun 23 00 02 FE 20 799*4882a593Smuzhiyun 23 00 02 26 30 800*4882a593Smuzhiyun 23 00 02 FE 3D 801*4882a593Smuzhiyun 23 00 02 20 71 802*4882a593Smuzhiyun 23 00 02 50 8F 803*4882a593Smuzhiyun 23 00 02 51 8F 804*4882a593Smuzhiyun 23 00 02 FE 00 805*4882a593Smuzhiyun 23 00 02 35 00 806*4882a593Smuzhiyun 05 78 01 11 807*4882a593Smuzhiyun 05 1E 01 29 808*4882a593Smuzhiyun ]; 809*4882a593Smuzhiyun 810*4882a593Smuzhiyun panel-exit-sequence = [ 811*4882a593Smuzhiyun 05 00 01 28 812*4882a593Smuzhiyun 05 00 01 10 813*4882a593Smuzhiyun ]; 814*4882a593Smuzhiyun 815*4882a593Smuzhiyun disp_timings1: display-timings { 816*4882a593Smuzhiyun native-mode = <&dsi1_timing0>; 817*4882a593Smuzhiyun dsi1_timing0: timing0 { 818*4882a593Smuzhiyun clock-frequency = <132000000>; 819*4882a593Smuzhiyun hactive = <1080>; 820*4882a593Smuzhiyun vactive = <1920>; 821*4882a593Smuzhiyun hfront-porch = <15>; 822*4882a593Smuzhiyun hsync-len = <4>; 823*4882a593Smuzhiyun hback-porch = <30>; 824*4882a593Smuzhiyun vfront-porch = <15>; 825*4882a593Smuzhiyun vsync-len = <2>; 826*4882a593Smuzhiyun vback-porch = <15>; 827*4882a593Smuzhiyun hsync-active = <0>; 828*4882a593Smuzhiyun vsync-active = <0>; 829*4882a593Smuzhiyun de-active = <0>; 830*4882a593Smuzhiyun pixelclk-active = <0>; 831*4882a593Smuzhiyun }; 832*4882a593Smuzhiyun }; 833*4882a593Smuzhiyun 834*4882a593Smuzhiyun ports { 835*4882a593Smuzhiyun #address-cells = <1>; 836*4882a593Smuzhiyun #size-cells = <0>; 837*4882a593Smuzhiyun 838*4882a593Smuzhiyun port@0 { 839*4882a593Smuzhiyun reg = <0>; 840*4882a593Smuzhiyun panel_in_dsi1: endpoint { 841*4882a593Smuzhiyun remote-endpoint = <&dsi1_out_panel>; 842*4882a593Smuzhiyun }; 843*4882a593Smuzhiyun }; 844*4882a593Smuzhiyun }; 845*4882a593Smuzhiyun }; 846*4882a593Smuzhiyun 847*4882a593Smuzhiyun ports { 848*4882a593Smuzhiyun #address-cells = <1>; 849*4882a593Smuzhiyun #size-cells = <0>; 850*4882a593Smuzhiyun 851*4882a593Smuzhiyun port@1 { 852*4882a593Smuzhiyun reg = <1>; 853*4882a593Smuzhiyun dsi1_out_panel: endpoint { 854*4882a593Smuzhiyun remote-endpoint = <&panel_in_dsi1>; 855*4882a593Smuzhiyun }; 856*4882a593Smuzhiyun }; 857*4882a593Smuzhiyun }; 858*4882a593Smuzhiyun 859*4882a593Smuzhiyun}; 860*4882a593Smuzhiyun 861*4882a593Smuzhiyun&gpu { 862*4882a593Smuzhiyun mali-supply = <&vdd_gpu_s0>; 863*4882a593Smuzhiyun mem-supply = <&vdd_gpu_mem_s0>; 864*4882a593Smuzhiyun status = "okay"; 865*4882a593Smuzhiyun}; 866*4882a593Smuzhiyun 867*4882a593Smuzhiyun&i2s0_8ch { 868*4882a593Smuzhiyun status = "okay"; 869*4882a593Smuzhiyun pinctrl-0 = <&i2s0_lrck 870*4882a593Smuzhiyun &i2s0_sclk 871*4882a593Smuzhiyun &i2s0_sdi0 872*4882a593Smuzhiyun &i2s0_sdo0>; 873*4882a593Smuzhiyun}; 874*4882a593Smuzhiyun 875*4882a593Smuzhiyun&iep { 876*4882a593Smuzhiyun status = "okay"; 877*4882a593Smuzhiyun}; 878*4882a593Smuzhiyun 879*4882a593Smuzhiyun&iep_mmu { 880*4882a593Smuzhiyun status = "okay"; 881*4882a593Smuzhiyun}; 882*4882a593Smuzhiyun 883*4882a593Smuzhiyun&jpegd { 884*4882a593Smuzhiyun status = "okay"; 885*4882a593Smuzhiyun}; 886*4882a593Smuzhiyun 887*4882a593Smuzhiyun&jpegd_mmu { 888*4882a593Smuzhiyun status = "okay"; 889*4882a593Smuzhiyun}; 890*4882a593Smuzhiyun 891*4882a593Smuzhiyun&jpege_ccu { 892*4882a593Smuzhiyun status = "okay"; 893*4882a593Smuzhiyun}; 894*4882a593Smuzhiyun 895*4882a593Smuzhiyun&jpege0 { 896*4882a593Smuzhiyun status = "okay"; 897*4882a593Smuzhiyun}; 898*4882a593Smuzhiyun 899*4882a593Smuzhiyun&jpege0_mmu { 900*4882a593Smuzhiyun status = "okay"; 901*4882a593Smuzhiyun}; 902*4882a593Smuzhiyun 903*4882a593Smuzhiyun&jpege1 { 904*4882a593Smuzhiyun status = "okay"; 905*4882a593Smuzhiyun}; 906*4882a593Smuzhiyun 907*4882a593Smuzhiyun&jpege1_mmu { 908*4882a593Smuzhiyun status = "okay"; 909*4882a593Smuzhiyun}; 910*4882a593Smuzhiyun 911*4882a593Smuzhiyun&jpege2 { 912*4882a593Smuzhiyun status = "okay"; 913*4882a593Smuzhiyun}; 914*4882a593Smuzhiyun 915*4882a593Smuzhiyun&jpege2_mmu { 916*4882a593Smuzhiyun status = "okay"; 917*4882a593Smuzhiyun}; 918*4882a593Smuzhiyun 919*4882a593Smuzhiyun&jpege3 { 920*4882a593Smuzhiyun status = "okay"; 921*4882a593Smuzhiyun}; 922*4882a593Smuzhiyun 923*4882a593Smuzhiyun&jpege3_mmu { 924*4882a593Smuzhiyun status = "okay"; 925*4882a593Smuzhiyun}; 926*4882a593Smuzhiyun 927*4882a593Smuzhiyun&mpp_srv { 928*4882a593Smuzhiyun status = "okay"; 929*4882a593Smuzhiyun}; 930*4882a593Smuzhiyun 931*4882a593Smuzhiyun&rga3_core0 { 932*4882a593Smuzhiyun status = "okay"; 933*4882a593Smuzhiyun}; 934*4882a593Smuzhiyun 935*4882a593Smuzhiyun&rga3_0_mmu { 936*4882a593Smuzhiyun status = "okay"; 937*4882a593Smuzhiyun}; 938*4882a593Smuzhiyun 939*4882a593Smuzhiyun&rga3_core1 { 940*4882a593Smuzhiyun status = "okay"; 941*4882a593Smuzhiyun}; 942*4882a593Smuzhiyun 943*4882a593Smuzhiyun&rga3_1_mmu { 944*4882a593Smuzhiyun status = "okay"; 945*4882a593Smuzhiyun}; 946*4882a593Smuzhiyun 947*4882a593Smuzhiyun&rga2 { 948*4882a593Smuzhiyun status = "okay"; 949*4882a593Smuzhiyun}; 950*4882a593Smuzhiyun 951*4882a593Smuzhiyun&rknpu { 952*4882a593Smuzhiyun rknpu-supply = <&vdd_npu_s0>; 953*4882a593Smuzhiyun mem-supply = <&vdd_npu_mem_s0>; 954*4882a593Smuzhiyun status = "okay"; 955*4882a593Smuzhiyun}; 956*4882a593Smuzhiyun 957*4882a593Smuzhiyun&rknpu_mmu { 958*4882a593Smuzhiyun status = "okay"; 959*4882a593Smuzhiyun}; 960*4882a593Smuzhiyun 961*4882a593Smuzhiyun&rkvdec_ccu { 962*4882a593Smuzhiyun status = "okay"; 963*4882a593Smuzhiyun}; 964*4882a593Smuzhiyun 965*4882a593Smuzhiyun&rkvdec0 { 966*4882a593Smuzhiyun status = "okay"; 967*4882a593Smuzhiyun}; 968*4882a593Smuzhiyun 969*4882a593Smuzhiyun&rkvdec0_mmu { 970*4882a593Smuzhiyun status = "okay"; 971*4882a593Smuzhiyun}; 972*4882a593Smuzhiyun 973*4882a593Smuzhiyun&rkvdec1 { 974*4882a593Smuzhiyun status = "okay"; 975*4882a593Smuzhiyun}; 976*4882a593Smuzhiyun 977*4882a593Smuzhiyun&rkvdec1_mmu { 978*4882a593Smuzhiyun status = "okay"; 979*4882a593Smuzhiyun}; 980*4882a593Smuzhiyun 981*4882a593Smuzhiyun&rkvenc_ccu { 982*4882a593Smuzhiyun status = "okay"; 983*4882a593Smuzhiyun}; 984*4882a593Smuzhiyun 985*4882a593Smuzhiyun&rkvenc0 { 986*4882a593Smuzhiyun venc-supply = <&vdd_vdenc_s0>; 987*4882a593Smuzhiyun mem-supply = <&vdd_vdenc_mem_s0>; 988*4882a593Smuzhiyun status = "okay"; 989*4882a593Smuzhiyun}; 990*4882a593Smuzhiyun 991*4882a593Smuzhiyun&rkvenc0_mmu { 992*4882a593Smuzhiyun status = "okay"; 993*4882a593Smuzhiyun}; 994*4882a593Smuzhiyun 995*4882a593Smuzhiyun&rkvenc1 { 996*4882a593Smuzhiyun venc-supply = <&vdd_vdenc_s0>; 997*4882a593Smuzhiyun mem-supply = <&vdd_vdenc_mem_s0>; 998*4882a593Smuzhiyun status = "okay"; 999*4882a593Smuzhiyun}; 1000*4882a593Smuzhiyun 1001*4882a593Smuzhiyun&rkvenc1_mmu { 1002*4882a593Smuzhiyun status = "okay"; 1003*4882a593Smuzhiyun}; 1004*4882a593Smuzhiyun 1005*4882a593Smuzhiyun&rockchip_suspend { 1006*4882a593Smuzhiyun status = "okay"; 1007*4882a593Smuzhiyun rockchip,sleep-debug-en = <1>; 1008*4882a593Smuzhiyun}; 1009*4882a593Smuzhiyun 1010*4882a593Smuzhiyun&saradc { 1011*4882a593Smuzhiyun status = "okay"; 1012*4882a593Smuzhiyun vref-supply = <&vcc_1v8_s0>; 1013*4882a593Smuzhiyun}; 1014*4882a593Smuzhiyun 1015*4882a593Smuzhiyun&sdhci { 1016*4882a593Smuzhiyun bus-width = <8>; 1017*4882a593Smuzhiyun no-sdio; 1018*4882a593Smuzhiyun no-sd; 1019*4882a593Smuzhiyun non-removable; 1020*4882a593Smuzhiyun max-frequency = <200000000>; 1021*4882a593Smuzhiyun mmc-hs400-1_8v; 1022*4882a593Smuzhiyun mmc-hs400-enhanced-strobe; 1023*4882a593Smuzhiyun full-pwr-cycle-in-suspend; 1024*4882a593Smuzhiyun status = "okay"; 1025*4882a593Smuzhiyun}; 1026*4882a593Smuzhiyun 1027*4882a593Smuzhiyun&sdmmc { 1028*4882a593Smuzhiyun max-frequency = <150000000>; 1029*4882a593Smuzhiyun no-sdio; 1030*4882a593Smuzhiyun no-mmc; 1031*4882a593Smuzhiyun bus-width = <4>; 1032*4882a593Smuzhiyun cap-mmc-highspeed; 1033*4882a593Smuzhiyun cap-sd-highspeed; 1034*4882a593Smuzhiyun disable-wp; 1035*4882a593Smuzhiyun sd-uhs-sdr104; 1036*4882a593Smuzhiyun vmmc-supply = <&vcc_3v3_sd_s0>; 1037*4882a593Smuzhiyun vqmmc-supply = <&vccio_sd_s0>; 1038*4882a593Smuzhiyun status = "disabled"; 1039*4882a593Smuzhiyun}; 1040*4882a593Smuzhiyun 1041*4882a593Smuzhiyun&tsadc { 1042*4882a593Smuzhiyun status = "okay"; 1043*4882a593Smuzhiyun}; 1044*4882a593Smuzhiyun 1045*4882a593Smuzhiyun&u2phy0 { 1046*4882a593Smuzhiyun status = "okay"; 1047*4882a593Smuzhiyun}; 1048*4882a593Smuzhiyun 1049*4882a593Smuzhiyun&u2phy2 { 1050*4882a593Smuzhiyun status = "okay"; 1051*4882a593Smuzhiyun}; 1052*4882a593Smuzhiyun 1053*4882a593Smuzhiyun&u2phy3 { 1054*4882a593Smuzhiyun status = "okay"; 1055*4882a593Smuzhiyun}; 1056*4882a593Smuzhiyun 1057*4882a593Smuzhiyun&u2phy0_otg { 1058*4882a593Smuzhiyun status = "okay"; 1059*4882a593Smuzhiyun}; 1060*4882a593Smuzhiyun 1061*4882a593Smuzhiyun&u2phy2_host { 1062*4882a593Smuzhiyun status = "okay"; 1063*4882a593Smuzhiyun}; 1064*4882a593Smuzhiyun 1065*4882a593Smuzhiyun&u2phy3_host { 1066*4882a593Smuzhiyun status = "okay"; 1067*4882a593Smuzhiyun}; 1068*4882a593Smuzhiyun 1069*4882a593Smuzhiyun&usb_host0_ehci { 1070*4882a593Smuzhiyun status = "okay"; 1071*4882a593Smuzhiyun}; 1072*4882a593Smuzhiyun 1073*4882a593Smuzhiyun&usb_host0_ohci { 1074*4882a593Smuzhiyun status = "okay"; 1075*4882a593Smuzhiyun}; 1076*4882a593Smuzhiyun 1077*4882a593Smuzhiyun&usb_host1_ehci { 1078*4882a593Smuzhiyun status = "okay"; 1079*4882a593Smuzhiyun}; 1080*4882a593Smuzhiyun 1081*4882a593Smuzhiyun&usb_host1_ohci { 1082*4882a593Smuzhiyun status = "okay"; 1083*4882a593Smuzhiyun}; 1084*4882a593Smuzhiyun 1085*4882a593Smuzhiyun&usbdp_phy0 { 1086*4882a593Smuzhiyun status = "okay"; 1087*4882a593Smuzhiyun}; 1088*4882a593Smuzhiyun 1089*4882a593Smuzhiyun&usbdp_phy0_dp { 1090*4882a593Smuzhiyun status = "okay"; 1091*4882a593Smuzhiyun}; 1092*4882a593Smuzhiyun 1093*4882a593Smuzhiyun&usbdp_phy0_u3 { 1094*4882a593Smuzhiyun status = "okay"; 1095*4882a593Smuzhiyun}; 1096*4882a593Smuzhiyun 1097*4882a593Smuzhiyun&usbdrd3_0 { 1098*4882a593Smuzhiyun status = "okay"; 1099*4882a593Smuzhiyun}; 1100*4882a593Smuzhiyun 1101*4882a593Smuzhiyun&usbdrd_dwc3_0 { 1102*4882a593Smuzhiyun dr_mode = "otg"; 1103*4882a593Smuzhiyun status = "okay"; 1104*4882a593Smuzhiyun}; 1105*4882a593Smuzhiyun 1106*4882a593Smuzhiyun&usbhost3_0 { 1107*4882a593Smuzhiyun status = "okay"; 1108*4882a593Smuzhiyun}; 1109*4882a593Smuzhiyun 1110*4882a593Smuzhiyun&usbhost_dwc3_0 { 1111*4882a593Smuzhiyun status = "okay"; 1112*4882a593Smuzhiyun}; 1113*4882a593Smuzhiyun 1114*4882a593Smuzhiyun&vdpu { 1115*4882a593Smuzhiyun status = "okay"; 1116*4882a593Smuzhiyun}; 1117*4882a593Smuzhiyun 1118*4882a593Smuzhiyun&vdpu_mmu { 1119*4882a593Smuzhiyun status = "okay"; 1120*4882a593Smuzhiyun}; 1121*4882a593Smuzhiyun 1122*4882a593Smuzhiyun&vepu { 1123*4882a593Smuzhiyun status = "okay"; 1124*4882a593Smuzhiyun}; 1125*4882a593Smuzhiyun 1126*4882a593Smuzhiyun&vop { 1127*4882a593Smuzhiyun status = "okay"; 1128*4882a593Smuzhiyun}; 1129*4882a593Smuzhiyun 1130*4882a593Smuzhiyun&vop_mmu { 1131*4882a593Smuzhiyun status = "okay"; 1132*4882a593Smuzhiyun}; 1133*4882a593Smuzhiyun 1134*4882a593Smuzhiyun/* vp0 & vp1 splice for 8K output */ 1135*4882a593Smuzhiyun&vp0 { 1136*4882a593Smuzhiyun rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; 1137*4882a593Smuzhiyun rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART0>; 1138*4882a593Smuzhiyun}; 1139*4882a593Smuzhiyun 1140*4882a593Smuzhiyun&vp1 { 1141*4882a593Smuzhiyun rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; 1142*4882a593Smuzhiyun rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART1>; 1143*4882a593Smuzhiyun}; 1144*4882a593Smuzhiyun 1145*4882a593Smuzhiyun&vp2 { 1146*4882a593Smuzhiyun rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; 1147*4882a593Smuzhiyun rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART2>; 1148*4882a593Smuzhiyun}; 1149*4882a593Smuzhiyun 1150*4882a593Smuzhiyun&vp3 { 1151*4882a593Smuzhiyun rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; 1152*4882a593Smuzhiyun rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART3>; 1153*4882a593Smuzhiyun}; 1154