1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 8*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h> 9*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h> 10*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h> 11*4882a593Smuzhiyun#include <dt-bindings/display/rockchip_vop.h> 12*4882a593Smuzhiyun#include <dt-bindings/sensor-dev.h> 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun backlight: backlight { 15*4882a593Smuzhiyun compatible = "pwm-backlight"; 16*4882a593Smuzhiyun brightness-levels = < 17*4882a593Smuzhiyun 0 20 20 21 21 22 22 23 18*4882a593Smuzhiyun 23 24 24 25 25 26 26 27 19*4882a593Smuzhiyun 27 28 28 29 29 30 30 31 20*4882a593Smuzhiyun 31 32 32 33 33 34 34 35 21*4882a593Smuzhiyun 35 36 36 37 37 38 38 39 22*4882a593Smuzhiyun 40 41 42 43 44 45 46 47 23*4882a593Smuzhiyun 48 49 50 51 52 53 54 55 24*4882a593Smuzhiyun 56 57 58 59 60 61 62 63 25*4882a593Smuzhiyun 64 65 66 67 68 69 70 71 26*4882a593Smuzhiyun 72 73 74 75 76 77 78 79 27*4882a593Smuzhiyun 80 81 82 83 84 85 86 87 28*4882a593Smuzhiyun 88 89 90 91 92 93 94 95 29*4882a593Smuzhiyun 96 97 98 99 100 101 102 103 30*4882a593Smuzhiyun 104 105 106 107 108 109 110 111 31*4882a593Smuzhiyun 112 113 114 115 116 117 118 119 32*4882a593Smuzhiyun 120 121 122 123 124 125 126 127 33*4882a593Smuzhiyun 128 129 130 131 132 133 134 135 34*4882a593Smuzhiyun 136 137 138 139 140 141 142 143 35*4882a593Smuzhiyun 144 145 146 147 148 149 150 151 36*4882a593Smuzhiyun 152 153 154 155 156 157 158 159 37*4882a593Smuzhiyun 160 161 162 163 164 165 166 167 38*4882a593Smuzhiyun 168 169 170 171 172 173 174 175 39*4882a593Smuzhiyun 176 177 178 179 180 181 182 183 40*4882a593Smuzhiyun 184 185 186 187 188 189 190 191 41*4882a593Smuzhiyun 192 193 194 195 196 197 198 199 42*4882a593Smuzhiyun 200 201 202 203 204 205 206 207 43*4882a593Smuzhiyun 208 209 210 211 212 213 214 215 44*4882a593Smuzhiyun 216 217 218 219 220 221 222 223 45*4882a593Smuzhiyun 224 225 226 227 228 229 230 231 46*4882a593Smuzhiyun 232 233 234 235 236 237 238 239 47*4882a593Smuzhiyun 240 241 242 243 244 245 246 247 48*4882a593Smuzhiyun 248 249 250 251 252 253 254 255 49*4882a593Smuzhiyun >; 50*4882a593Smuzhiyun default-brightness-level = <200>; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun test-power { 54*4882a593Smuzhiyun status = "okay"; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun vcc12v_dcin: vcc12v-dcin { 58*4882a593Smuzhiyun compatible = "regulator-fixed"; 59*4882a593Smuzhiyun regulator-name = "vcc12v_dcin"; 60*4882a593Smuzhiyun regulator-always-on; 61*4882a593Smuzhiyun regulator-boot-on; 62*4882a593Smuzhiyun regulator-min-microvolt = <12000000>; 63*4882a593Smuzhiyun regulator-max-microvolt = <12000000>; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun vcc5v0_sys: vcc5v0-sys { 67*4882a593Smuzhiyun compatible = "regulator-fixed"; 68*4882a593Smuzhiyun regulator-name = "vcc5v0_sys"; 69*4882a593Smuzhiyun regulator-always-on; 70*4882a593Smuzhiyun regulator-boot-on; 71*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 72*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 73*4882a593Smuzhiyun vin-supply = <&vcc12v_dcin>; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun vcc5v0_usbdcin: vcc5v0-usbdcin { 77*4882a593Smuzhiyun compatible = "regulator-fixed"; 78*4882a593Smuzhiyun regulator-name = "vcc5v0_usbdcin"; 79*4882a593Smuzhiyun regulator-always-on; 80*4882a593Smuzhiyun regulator-boot-on; 81*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 82*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 83*4882a593Smuzhiyun vin-supply = <&vcc12v_dcin>; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun vcc5v0_usb: vcc5v0-usb { 87*4882a593Smuzhiyun compatible = "regulator-fixed"; 88*4882a593Smuzhiyun regulator-name = "vcc5v0_usb"; 89*4882a593Smuzhiyun regulator-always-on; 90*4882a593Smuzhiyun regulator-boot-on; 91*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 92*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 93*4882a593Smuzhiyun vin-supply = <&vcc5v0_usbdcin>; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun}; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun&av1d_mmu { 98*4882a593Smuzhiyun status = "okay"; 99*4882a593Smuzhiyun}; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun&cpu_l0 { 102*4882a593Smuzhiyun cpu-supply = <&vdd_cpu_lit_s0>; 103*4882a593Smuzhiyun mem-supply = <&vdd_cpu_lit_s0>; 104*4882a593Smuzhiyun}; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun&cpu_b0 { 107*4882a593Smuzhiyun cpu-supply = <&vdd_cpu_big0_s0>; 108*4882a593Smuzhiyun mem-supply = <&vdd_cpu_big0_s0>; 109*4882a593Smuzhiyun}; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun&cpu_b2 { 112*4882a593Smuzhiyun cpu-supply = <&vdd_cpu_big1_s0>; 113*4882a593Smuzhiyun mem-supply = <&vdd_cpu_big1_s0>; 114*4882a593Smuzhiyun}; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun&gpu { 117*4882a593Smuzhiyun mali-supply = <&vdd_gpu_s0>; 118*4882a593Smuzhiyun mem-supply = <&vdd_gpu_s0>; 119*4882a593Smuzhiyun status = "okay"; 120*4882a593Smuzhiyun}; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun&i2s0_8ch { 123*4882a593Smuzhiyun status = "disabled"; 124*4882a593Smuzhiyun}; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun&iep { 127*4882a593Smuzhiyun status = "okay"; 128*4882a593Smuzhiyun}; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun&iep_mmu { 131*4882a593Smuzhiyun status = "okay"; 132*4882a593Smuzhiyun}; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun&jpegd { 135*4882a593Smuzhiyun status = "okay"; 136*4882a593Smuzhiyun}; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun&jpegd_mmu { 139*4882a593Smuzhiyun status = "okay"; 140*4882a593Smuzhiyun}; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun&jpege_ccu { 143*4882a593Smuzhiyun status = "okay"; 144*4882a593Smuzhiyun}; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun&jpege0 { 147*4882a593Smuzhiyun status = "okay"; 148*4882a593Smuzhiyun}; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun&jpege0_mmu { 151*4882a593Smuzhiyun status = "okay"; 152*4882a593Smuzhiyun}; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun&jpege1 { 155*4882a593Smuzhiyun status = "okay"; 156*4882a593Smuzhiyun}; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun&jpege1_mmu { 159*4882a593Smuzhiyun status = "okay"; 160*4882a593Smuzhiyun}; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun&jpege2 { 163*4882a593Smuzhiyun status = "okay"; 164*4882a593Smuzhiyun}; 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun&jpege2_mmu { 167*4882a593Smuzhiyun status = "okay"; 168*4882a593Smuzhiyun}; 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun&jpege3 { 171*4882a593Smuzhiyun status = "okay"; 172*4882a593Smuzhiyun}; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun&jpege3_mmu { 175*4882a593Smuzhiyun status = "okay"; 176*4882a593Smuzhiyun}; 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun&mpp_srv { 179*4882a593Smuzhiyun status = "okay"; 180*4882a593Smuzhiyun}; 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun&rga3_core0 { 183*4882a593Smuzhiyun status = "okay"; 184*4882a593Smuzhiyun}; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun&rga3_0_mmu { 187*4882a593Smuzhiyun status = "okay"; 188*4882a593Smuzhiyun}; 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun&rga3_core1 { 191*4882a593Smuzhiyun status = "okay"; 192*4882a593Smuzhiyun}; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun&rga3_1_mmu { 195*4882a593Smuzhiyun status = "okay"; 196*4882a593Smuzhiyun}; 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun&rga2 { 199*4882a593Smuzhiyun status = "okay"; 200*4882a593Smuzhiyun}; 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun&rknpu { 203*4882a593Smuzhiyun rknpu-supply = <&vdd_npu_s0>; 204*4882a593Smuzhiyun mem-supply = <&vdd_npu_s0>; 205*4882a593Smuzhiyun status = "okay"; 206*4882a593Smuzhiyun}; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun&rknpu_mmu { 209*4882a593Smuzhiyun status = "okay"; 210*4882a593Smuzhiyun}; 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun&rkvdec_ccu { 213*4882a593Smuzhiyun status = "okay"; 214*4882a593Smuzhiyun}; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun&rkvdec0 { 217*4882a593Smuzhiyun status = "okay"; 218*4882a593Smuzhiyun}; 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun&rkvdec0_mmu { 221*4882a593Smuzhiyun status = "okay"; 222*4882a593Smuzhiyun}; 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun&rkvdec1 { 225*4882a593Smuzhiyun status = "okay"; 226*4882a593Smuzhiyun}; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun&rkvdec1_mmu { 229*4882a593Smuzhiyun status = "okay"; 230*4882a593Smuzhiyun}; 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun&rkvenc_ccu { 233*4882a593Smuzhiyun status = "okay"; 234*4882a593Smuzhiyun}; 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun&rkvenc0 { 237*4882a593Smuzhiyun status = "okay"; 238*4882a593Smuzhiyun}; 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun&rkvenc0_mmu { 241*4882a593Smuzhiyun status = "okay"; 242*4882a593Smuzhiyun}; 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun&rkvenc1 { 245*4882a593Smuzhiyun status = "okay"; 246*4882a593Smuzhiyun}; 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun&rkvenc1_mmu { 249*4882a593Smuzhiyun status = "okay"; 250*4882a593Smuzhiyun}; 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun&rockchip_suspend { 253*4882a593Smuzhiyun status = "okay"; 254*4882a593Smuzhiyun rockchip,sleep-debug-en = <1>; 255*4882a593Smuzhiyun}; 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun&saradc { 258*4882a593Smuzhiyun status = "okay"; 259*4882a593Smuzhiyun vref-supply = <&vcc_1v8_s0>; 260*4882a593Smuzhiyun}; 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun&sdhci { 263*4882a593Smuzhiyun bus-width = <8>; 264*4882a593Smuzhiyun no-sdio; 265*4882a593Smuzhiyun no-sd; 266*4882a593Smuzhiyun non-removable; 267*4882a593Smuzhiyun max-frequency = <200000000>; 268*4882a593Smuzhiyun mmc-hs400-1_8v; 269*4882a593Smuzhiyun mmc-hs400-enhanced-strobe; 270*4882a593Smuzhiyun status = "okay"; 271*4882a593Smuzhiyun}; 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun&sdmmc { 274*4882a593Smuzhiyun max-frequency = <150000000>; 275*4882a593Smuzhiyun no-sdio; 276*4882a593Smuzhiyun no-mmc; 277*4882a593Smuzhiyun bus-width = <4>; 278*4882a593Smuzhiyun cap-mmc-highspeed; 279*4882a593Smuzhiyun cap-sd-highspeed; 280*4882a593Smuzhiyun disable-wp; 281*4882a593Smuzhiyun sd-uhs-sdr104; 282*4882a593Smuzhiyun vqmmc-supply = <&vccio_sd_s0>; 283*4882a593Smuzhiyun status = "disabled"; 284*4882a593Smuzhiyun}; 285*4882a593Smuzhiyun 286*4882a593Smuzhiyun&tsadc { 287*4882a593Smuzhiyun status = "okay"; 288*4882a593Smuzhiyun}; 289*4882a593Smuzhiyun 290*4882a593Smuzhiyun&u2phy0 { 291*4882a593Smuzhiyun status = "okay"; 292*4882a593Smuzhiyun}; 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun&u2phy1 { 295*4882a593Smuzhiyun status = "okay"; 296*4882a593Smuzhiyun}; 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun&u2phy2 { 299*4882a593Smuzhiyun status = "okay"; 300*4882a593Smuzhiyun}; 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun&u2phy3 { 303*4882a593Smuzhiyun status = "okay"; 304*4882a593Smuzhiyun}; 305*4882a593Smuzhiyun 306*4882a593Smuzhiyun&u2phy0_otg { 307*4882a593Smuzhiyun status = "okay"; 308*4882a593Smuzhiyun}; 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun&u2phy1_otg { 311*4882a593Smuzhiyun rockchip,sel-pipe-phystatus; 312*4882a593Smuzhiyun status = "okay"; 313*4882a593Smuzhiyun}; 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun&u2phy2_host { 316*4882a593Smuzhiyun status = "okay"; 317*4882a593Smuzhiyun}; 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun&u2phy3_host { 320*4882a593Smuzhiyun status = "okay"; 321*4882a593Smuzhiyun}; 322*4882a593Smuzhiyun 323*4882a593Smuzhiyun&usb_host0_ehci { 324*4882a593Smuzhiyun status = "okay"; 325*4882a593Smuzhiyun}; 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun&usb_host0_ohci { 328*4882a593Smuzhiyun status = "okay"; 329*4882a593Smuzhiyun}; 330*4882a593Smuzhiyun 331*4882a593Smuzhiyun&usb_host1_ehci { 332*4882a593Smuzhiyun status = "okay"; 333*4882a593Smuzhiyun}; 334*4882a593Smuzhiyun 335*4882a593Smuzhiyun&usb_host1_ohci { 336*4882a593Smuzhiyun status = "okay"; 337*4882a593Smuzhiyun}; 338*4882a593Smuzhiyun 339*4882a593Smuzhiyun&usbdp_phy0 { 340*4882a593Smuzhiyun rockchip,dp-lane-mux = <2 3>; 341*4882a593Smuzhiyun status = "okay"; 342*4882a593Smuzhiyun}; 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun&usbdp_phy0_dp { 345*4882a593Smuzhiyun status = "disabled"; 346*4882a593Smuzhiyun}; 347*4882a593Smuzhiyun 348*4882a593Smuzhiyun&usbdp_phy0_u3 { 349*4882a593Smuzhiyun status = "okay"; 350*4882a593Smuzhiyun}; 351*4882a593Smuzhiyun 352*4882a593Smuzhiyun&usbdp_phy1 { 353*4882a593Smuzhiyun status = "okay"; 354*4882a593Smuzhiyun}; 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun&usbdp_phy1_dp { 357*4882a593Smuzhiyun status = "okay"; 358*4882a593Smuzhiyun}; 359*4882a593Smuzhiyun 360*4882a593Smuzhiyun&usbdp_phy1_u3 { 361*4882a593Smuzhiyun status = "okay"; 362*4882a593Smuzhiyun}; 363*4882a593Smuzhiyun 364*4882a593Smuzhiyun&usbdrd3_0 { 365*4882a593Smuzhiyun status = "okay"; 366*4882a593Smuzhiyun}; 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun&usbdrd_dwc3_0 { 369*4882a593Smuzhiyun dr_mode = "otg"; 370*4882a593Smuzhiyun extcon=<&u2phy0>; 371*4882a593Smuzhiyun status = "okay"; 372*4882a593Smuzhiyun}; 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun&usbhost3_0 { 375*4882a593Smuzhiyun status = "okay"; 376*4882a593Smuzhiyun}; 377*4882a593Smuzhiyun 378*4882a593Smuzhiyun&usbhost_dwc3_0 { 379*4882a593Smuzhiyun status = "okay"; 380*4882a593Smuzhiyun}; 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun&usbdrd3_1 { 383*4882a593Smuzhiyun status = "okay"; 384*4882a593Smuzhiyun}; 385*4882a593Smuzhiyun 386*4882a593Smuzhiyun&usbdrd_dwc3_1 { 387*4882a593Smuzhiyun dr_mode = "host"; 388*4882a593Smuzhiyun maximum-speed = "high-speed"; 389*4882a593Smuzhiyun phys = <&u2phy1_otg>; 390*4882a593Smuzhiyun phy-names = "usb2-phy"; 391*4882a593Smuzhiyun snps,dis_u2_susphy_quirk; 392*4882a593Smuzhiyun status = "okay"; 393*4882a593Smuzhiyun}; 394*4882a593Smuzhiyun 395*4882a593Smuzhiyun&vdpu { 396*4882a593Smuzhiyun status = "okay"; 397*4882a593Smuzhiyun}; 398*4882a593Smuzhiyun 399*4882a593Smuzhiyun&vdpu_mmu { 400*4882a593Smuzhiyun status = "okay"; 401*4882a593Smuzhiyun}; 402*4882a593Smuzhiyun 403*4882a593Smuzhiyun&vepu { 404*4882a593Smuzhiyun status = "okay"; 405*4882a593Smuzhiyun}; 406*4882a593Smuzhiyun 407*4882a593Smuzhiyun&vop { 408*4882a593Smuzhiyun status = "okay"; 409*4882a593Smuzhiyun}; 410*4882a593Smuzhiyun 411*4882a593Smuzhiyun&vop_mmu { 412*4882a593Smuzhiyun status = "okay"; 413*4882a593Smuzhiyun}; 414*4882a593Smuzhiyun 415*4882a593Smuzhiyun/* vp0 & vp1 splice for 8K output */ 416*4882a593Smuzhiyun&vp0 { 417*4882a593Smuzhiyun rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; 418*4882a593Smuzhiyun rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART0>; 419*4882a593Smuzhiyun}; 420*4882a593Smuzhiyun 421*4882a593Smuzhiyun&vp1 { 422*4882a593Smuzhiyun rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; 423*4882a593Smuzhiyun rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART1>; 424*4882a593Smuzhiyun}; 425*4882a593Smuzhiyun 426*4882a593Smuzhiyun&vp2 { 427*4882a593Smuzhiyun rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; 428*4882a593Smuzhiyun rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART2>; 429*4882a593Smuzhiyun}; 430*4882a593Smuzhiyun 431*4882a593Smuzhiyun&vp3 { 432*4882a593Smuzhiyun rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; 433*4882a593Smuzhiyun rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART3>; 434*4882a593Smuzhiyun}; 435