1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include <dt-bindings/display/media-bus-format.h> 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/ { 9*4882a593Smuzhiyun aliases { 10*4882a593Smuzhiyun pinctrl0 = &pinctrl; 11*4882a593Smuzhiyun }; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun backlight { 14*4882a593Smuzhiyun compatible = "simple-bus"; 15*4882a593Smuzhiyun #address-cells = <1>; 16*4882a593Smuzhiyun #size-cells = <0>; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun i2c2_max96755f_backlight: backlight@0 { 19*4882a593Smuzhiyun compatible = "pwm-backlight"; 20*4882a593Smuzhiyun reg = <0>; 21*4882a593Smuzhiyun pwms = <&pwm6 0 1000000 0>; 22*4882a593Smuzhiyun brightness-levels = <0 4 8 16 32 64 128 255>; 23*4882a593Smuzhiyun default-brightness-level = <6>; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun i2c3_max96745_backlight: backlight@1 { 27*4882a593Smuzhiyun compatible = "pwm-backlight"; 28*4882a593Smuzhiyun reg = <1>; 29*4882a593Smuzhiyun pwms = <&pwm10 0 1000000 0>; 30*4882a593Smuzhiyun brightness-levels = <0 4 8 16 32 64 128 255>; 31*4882a593Smuzhiyun default-brightness-level = <6>; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun i2c5_max96745_backlight: backlight@2 { 35*4882a593Smuzhiyun compatible = "pwm-backlight"; 36*4882a593Smuzhiyun reg = <2>; 37*4882a593Smuzhiyun pwms = <&pwm12 0 1000000 0>; 38*4882a593Smuzhiyun brightness-levels = <0 4 8 16 32 64 128 255>; 39*4882a593Smuzhiyun default-brightness-level = <6>; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun i2c6_max96755f_backlight: backlight@3 { 43*4882a593Smuzhiyun compatible = "pwm-backlight"; 44*4882a593Smuzhiyun reg = <3>; 45*4882a593Smuzhiyun pwms = <&pwm13 0 1000000 0>; 46*4882a593Smuzhiyun brightness-levels = <0 4 8 16 32 64 128 255>; 47*4882a593Smuzhiyun default-brightness-level = <6>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun i2c7_max96745_backlight: backlight@4 { 51*4882a593Smuzhiyun compatible = "pwm-backlight"; 52*4882a593Smuzhiyun reg = <4>; 53*4882a593Smuzhiyun pwms = <&pwm11 0 1000000 0>; 54*4882a593Smuzhiyun brightness-levels = <0 4 8 16 32 64 128 255>; 55*4882a593Smuzhiyun default-brightness-level = <6>; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun i2c8_max96745_backlight: backlight@5 { 59*4882a593Smuzhiyun compatible = "pwm-backlight"; 60*4882a593Smuzhiyun reg = <5>; 61*4882a593Smuzhiyun pwms = <&pwm14 0 1000000 0>; 62*4882a593Smuzhiyun brightness-levels = <0 4 8 16 32 64 128 255>; 63*4882a593Smuzhiyun default-brightness-level = <6>; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun}; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun&dp0 { 69*4882a593Smuzhiyun split-mode; 70*4882a593Smuzhiyun force-hpd; 71*4882a593Smuzhiyun status = "okay"; 72*4882a593Smuzhiyun}; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun&dp0_in_vp0 { 75*4882a593Smuzhiyun status = "okay"; 76*4882a593Smuzhiyun}; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun&dp0_out { 79*4882a593Smuzhiyun link-frequencies = /bits/ 64 <2700000000>; 80*4882a593Smuzhiyun remote-endpoint = <&i2c3_max96745_in>; 81*4882a593Smuzhiyun}; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun&usbdp_phy0 { 84*4882a593Smuzhiyun rockchip,dp-lane-mux = <0 1 2 3>; 85*4882a593Smuzhiyun status = "okay"; 86*4882a593Smuzhiyun}; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun&usbdp_phy0_dp { 89*4882a593Smuzhiyun status = "okay"; 90*4882a593Smuzhiyun}; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun&route_dp0 { 93*4882a593Smuzhiyun connect = <&vp0_out_dp0>; 94*4882a593Smuzhiyun status = "okay"; 95*4882a593Smuzhiyun}; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun&dp1 { 98*4882a593Smuzhiyun force-hpd; 99*4882a593Smuzhiyun status = "okay"; 100*4882a593Smuzhiyun}; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun&dp1_out { 103*4882a593Smuzhiyun link-frequencies = /bits/ 64 <2700000000>; 104*4882a593Smuzhiyun remote-endpoint = <&i2c8_max96745_in>; 105*4882a593Smuzhiyun}; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun&usbdp_phy1 { 108*4882a593Smuzhiyun rockchip,dp-lane-mux = <0 1 2 3>; 109*4882a593Smuzhiyun status = "okay"; 110*4882a593Smuzhiyun}; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun&usbdp_phy1_dp { 113*4882a593Smuzhiyun status = "okay"; 114*4882a593Smuzhiyun}; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun&dsi0 { 117*4882a593Smuzhiyun status = "okay"; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun ports { 120*4882a593Smuzhiyun #address-cells = <1>; 121*4882a593Smuzhiyun #size-cells = <0>; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun port@1 { 124*4882a593Smuzhiyun reg = <1>; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun dsi0_out: endpoint { 127*4882a593Smuzhiyun remote-endpoint = <&i2c2_max96755f_in>; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun}; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun&mipi_dcphy0 { 134*4882a593Smuzhiyun status = "okay"; 135*4882a593Smuzhiyun}; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun&dsi0_in_vp2 { 138*4882a593Smuzhiyun status = "okay"; 139*4882a593Smuzhiyun}; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun&route_dsi0 { 142*4882a593Smuzhiyun connect = <&vp2_out_dsi0>; 143*4882a593Smuzhiyun status = "okay"; 144*4882a593Smuzhiyun}; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun&dsi1 { 147*4882a593Smuzhiyun status = "okay"; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun ports { 150*4882a593Smuzhiyun #address-cells = <1>; 151*4882a593Smuzhiyun #size-cells = <0>; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun port@1 { 154*4882a593Smuzhiyun reg = <1>; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun dsi1_out: endpoint { 157*4882a593Smuzhiyun remote-endpoint = <&i2c6_max96755f_in>; 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun}; 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun&mipi_dcphy1 { 164*4882a593Smuzhiyun status = "okay"; 165*4882a593Smuzhiyun}; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun&dsi1_in_vp3 { 168*4882a593Smuzhiyun status = "okay"; 169*4882a593Smuzhiyun}; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun&route_dsi1 { 172*4882a593Smuzhiyun connect = <&vp3_out_dsi1>; 173*4882a593Smuzhiyun status = "okay"; 174*4882a593Smuzhiyun}; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun&edp0 { 177*4882a593Smuzhiyun split-mode; 178*4882a593Smuzhiyun force-hpd; 179*4882a593Smuzhiyun status = "okay"; 180*4882a593Smuzhiyun}; 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun&edp0_out { 183*4882a593Smuzhiyun link-frequencies = /bits/ 64 <2700000000>; 184*4882a593Smuzhiyun remote-endpoint = <&i2c5_max96745_in>; 185*4882a593Smuzhiyun}; 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun&hdptxphy0 { 188*4882a593Smuzhiyun status = "okay"; 189*4882a593Smuzhiyun}; 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun&edp0_in_vp1 { 192*4882a593Smuzhiyun status = "okay"; 193*4882a593Smuzhiyun}; 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun&route_edp0 { 196*4882a593Smuzhiyun connect = <&vp1_out_edp0>; 197*4882a593Smuzhiyun status = "okay"; 198*4882a593Smuzhiyun}; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun&edp1 { 201*4882a593Smuzhiyun force-hpd; 202*4882a593Smuzhiyun status = "okay"; 203*4882a593Smuzhiyun}; 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun&edp1_out { 206*4882a593Smuzhiyun link-frequencies = /bits/ 64 <2700000000>; 207*4882a593Smuzhiyun remote-endpoint = <&i2c7_max96745_in>; 208*4882a593Smuzhiyun}; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun&hdptxphy1 { 211*4882a593Smuzhiyun status = "okay"; 212*4882a593Smuzhiyun}; 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun&i2c2 { 215*4882a593Smuzhiyun pinctrl-0 = <&i2c2m4_xfer>; 216*4882a593Smuzhiyun clock-frequency = <400000>; 217*4882a593Smuzhiyun status = "okay"; 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun max96755f@40 { 220*4882a593Smuzhiyun compatible = "maxim,max96755f"; 221*4882a593Smuzhiyun reg = <0x40>; 222*4882a593Smuzhiyun pinctrl-names = "default"; 223*4882a593Smuzhiyun pinctrl-0 = <&i2c2_serdes_pins>; 224*4882a593Smuzhiyun #address-cells = <1>; 225*4882a593Smuzhiyun #size-cells = <0>; 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun pinctrl { 228*4882a593Smuzhiyun compatible = "maxim,max96755f-pinctrl"; 229*4882a593Smuzhiyun pinctrl-names = "default"; 230*4882a593Smuzhiyun pinctrl-0 = <&i2c2_max96755f_pinctrl_hog>; 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun i2c2_max96755f_pinctrl_hog: hog { 233*4882a593Smuzhiyun i2c { 234*4882a593Smuzhiyun groups = "I2C"; 235*4882a593Smuzhiyun function = "I2C"; 236*4882a593Smuzhiyun }; 237*4882a593Smuzhiyun }; 238*4882a593Smuzhiyun 239*4882a593Smuzhiyun i2c2_max96755f_panel_pins: panel-pins { 240*4882a593Smuzhiyun bl-pwm { 241*4882a593Smuzhiyun pins = "MFP18"; 242*4882a593Smuzhiyun function = "GPIO_TX_0"; 243*4882a593Smuzhiyun }; 244*4882a593Smuzhiyun }; 245*4882a593Smuzhiyun }; 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun bridge { 248*4882a593Smuzhiyun compatible = "maxim,max96755f-bridge"; 249*4882a593Smuzhiyun lock-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun ports { 252*4882a593Smuzhiyun #address-cells = <1>; 253*4882a593Smuzhiyun #size-cells = <0>; 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun port@0 { 256*4882a593Smuzhiyun reg = <0>; 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun i2c2_max96755f_in: endpoint { 259*4882a593Smuzhiyun remote-endpoint = <&dsi0_out>; 260*4882a593Smuzhiyun }; 261*4882a593Smuzhiyun }; 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun port@1 { 264*4882a593Smuzhiyun reg = <1>; 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun i2c2_max96755f_out: endpoint { 267*4882a593Smuzhiyun remote-endpoint = <&i2c2_max96755f_panel_in>; 268*4882a593Smuzhiyun }; 269*4882a593Smuzhiyun }; 270*4882a593Smuzhiyun }; 271*4882a593Smuzhiyun }; 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun gmsl@0 { 274*4882a593Smuzhiyun reg = <0>; 275*4882a593Smuzhiyun clock-frequency = <400000>; 276*4882a593Smuzhiyun #address-cells = <1>; 277*4882a593Smuzhiyun #size-cells = <0>; 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun panel@48 { 280*4882a593Smuzhiyun compatible = "boe,av156fht-l83"; 281*4882a593Smuzhiyun reg = <0x48>; 282*4882a593Smuzhiyun backlight = <&i2c2_max96755f_backlight>; 283*4882a593Smuzhiyun pinctrl-names = "default"; 284*4882a593Smuzhiyun pinctrl-0 = <&i2c2_max96755f_panel_pins>; 285*4882a593Smuzhiyun 286*4882a593Smuzhiyun panel-timing { 287*4882a593Smuzhiyun clock-frequency = <148500000>; 288*4882a593Smuzhiyun hactive = <1920>; 289*4882a593Smuzhiyun vactive = <1080>; 290*4882a593Smuzhiyun hfront-porch = <20>; 291*4882a593Smuzhiyun hsync-len = <20>; 292*4882a593Smuzhiyun hback-porch = <20>; 293*4882a593Smuzhiyun vfront-porch = <250>; 294*4882a593Smuzhiyun vsync-len = <2>; 295*4882a593Smuzhiyun vback-porch = <8>; 296*4882a593Smuzhiyun hsync-active = <0>; 297*4882a593Smuzhiyun vsync-active = <0>; 298*4882a593Smuzhiyun de-active = <0>; 299*4882a593Smuzhiyun pixelclk-active = <0>; 300*4882a593Smuzhiyun }; 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun port { 303*4882a593Smuzhiyun i2c2_max96755f_panel_in: endpoint { 304*4882a593Smuzhiyun remote-endpoint = <&i2c2_max96755f_out>; 305*4882a593Smuzhiyun }; 306*4882a593Smuzhiyun }; 307*4882a593Smuzhiyun }; 308*4882a593Smuzhiyun }; 309*4882a593Smuzhiyun }; 310*4882a593Smuzhiyun}; 311*4882a593Smuzhiyun 312*4882a593Smuzhiyun&i2c3 { 313*4882a593Smuzhiyun pinctrl-0 = <&i2c3m2_xfer>; 314*4882a593Smuzhiyun clock-frequency = <400000>; 315*4882a593Smuzhiyun status = "okay"; 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun max96745@42 { 318*4882a593Smuzhiyun compatible = "maxim,max96745"; 319*4882a593Smuzhiyun reg = <0x42>; 320*4882a593Smuzhiyun pinctrl-names = "default"; 321*4882a593Smuzhiyun pinctrl-0 = <&i2c3_serdes_pins>; 322*4882a593Smuzhiyun #address-cells = <1>; 323*4882a593Smuzhiyun #size-cells = <0>; 324*4882a593Smuzhiyun 325*4882a593Smuzhiyun pinctrl { 326*4882a593Smuzhiyun compatible = "maxim,max96745-pinctrl"; 327*4882a593Smuzhiyun pinctrl-names = "default"; 328*4882a593Smuzhiyun pinctrl-0 = <&i2c3_max96745_pinctrl_hog>; 329*4882a593Smuzhiyun 330*4882a593Smuzhiyun i2c3_max96745_pinctrl_hog: hog { 331*4882a593Smuzhiyun i2c { 332*4882a593Smuzhiyun groups = "I2C"; 333*4882a593Smuzhiyun function = "I2C"; 334*4882a593Smuzhiyun }; 335*4882a593Smuzhiyun }; 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun i2c3_max96745_panel_pins: panel-pins { 338*4882a593Smuzhiyun bl-pwm { 339*4882a593Smuzhiyun pins = "MFP0"; 340*4882a593Smuzhiyun function = "GPIO_TX_A_0"; 341*4882a593Smuzhiyun }; 342*4882a593Smuzhiyun }; 343*4882a593Smuzhiyun }; 344*4882a593Smuzhiyun 345*4882a593Smuzhiyun bridge { 346*4882a593Smuzhiyun compatible = "maxim,max96745-bridge"; 347*4882a593Smuzhiyun lock-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; 348*4882a593Smuzhiyun 349*4882a593Smuzhiyun ports { 350*4882a593Smuzhiyun #address-cells = <1>; 351*4882a593Smuzhiyun #size-cells = <0>; 352*4882a593Smuzhiyun 353*4882a593Smuzhiyun port@0 { 354*4882a593Smuzhiyun reg = <0>; 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun i2c3_max96745_in: endpoint { 357*4882a593Smuzhiyun remote-endpoint = <&dp0_out>; 358*4882a593Smuzhiyun }; 359*4882a593Smuzhiyun }; 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun port@1 { 362*4882a593Smuzhiyun reg = <1>; 363*4882a593Smuzhiyun 364*4882a593Smuzhiyun i2c3_max96745_out: endpoint { 365*4882a593Smuzhiyun remote-endpoint = <&i2c3_max96745_panel_in>; 366*4882a593Smuzhiyun }; 367*4882a593Smuzhiyun }; 368*4882a593Smuzhiyun }; 369*4882a593Smuzhiyun }; 370*4882a593Smuzhiyun 371*4882a593Smuzhiyun gmsl@0 { 372*4882a593Smuzhiyun reg = <0>; 373*4882a593Smuzhiyun clock-frequency = <400000>; 374*4882a593Smuzhiyun #address-cells = <1>; 375*4882a593Smuzhiyun #size-cells = <0>; 376*4882a593Smuzhiyun 377*4882a593Smuzhiyun panel@48 { 378*4882a593Smuzhiyun compatible = "boe,av156fht-l83"; 379*4882a593Smuzhiyun reg = <0x48>; 380*4882a593Smuzhiyun backlight = <&i2c3_max96745_backlight>; 381*4882a593Smuzhiyun pinctrl-names = "default"; 382*4882a593Smuzhiyun pinctrl-0 = <&i2c3_max96745_panel_pins>; 383*4882a593Smuzhiyun 384*4882a593Smuzhiyun panel-timing { 385*4882a593Smuzhiyun clock-frequency = <148500000>; 386*4882a593Smuzhiyun hactive = <1920>; 387*4882a593Smuzhiyun vactive = <1080>; 388*4882a593Smuzhiyun hfront-porch = <20>; 389*4882a593Smuzhiyun hsync-len = <20>; 390*4882a593Smuzhiyun hback-porch = <20>; 391*4882a593Smuzhiyun vfront-porch = <250>; 392*4882a593Smuzhiyun vsync-len = <2>; 393*4882a593Smuzhiyun vback-porch = <8>; 394*4882a593Smuzhiyun hsync-active = <0>; 395*4882a593Smuzhiyun vsync-active = <0>; 396*4882a593Smuzhiyun de-active = <0>; 397*4882a593Smuzhiyun pixelclk-active = <0>; 398*4882a593Smuzhiyun }; 399*4882a593Smuzhiyun 400*4882a593Smuzhiyun port { 401*4882a593Smuzhiyun i2c3_max96745_panel_in: endpoint { 402*4882a593Smuzhiyun remote-endpoint = <&i2c3_max96745_out>; 403*4882a593Smuzhiyun }; 404*4882a593Smuzhiyun }; 405*4882a593Smuzhiyun }; 406*4882a593Smuzhiyun }; 407*4882a593Smuzhiyun }; 408*4882a593Smuzhiyun}; 409*4882a593Smuzhiyun 410*4882a593Smuzhiyun&i2c5 { 411*4882a593Smuzhiyun clock-frequency = <400000>; 412*4882a593Smuzhiyun status = "okay"; 413*4882a593Smuzhiyun 414*4882a593Smuzhiyun max96745@42 { 415*4882a593Smuzhiyun compatible = "maxim,max96745"; 416*4882a593Smuzhiyun reg = <0x42>; 417*4882a593Smuzhiyun pinctrl-names = "default"; 418*4882a593Smuzhiyun pinctrl-0 = <&i2c5_serdes_pins>; 419*4882a593Smuzhiyun #address-cells = <1>; 420*4882a593Smuzhiyun #size-cells = <0>; 421*4882a593Smuzhiyun 422*4882a593Smuzhiyun pinctrl { 423*4882a593Smuzhiyun compatible = "maxim,max96745-pinctrl"; 424*4882a593Smuzhiyun pinctrl-names = "default"; 425*4882a593Smuzhiyun pinctrl-0 = <&i2c5_max96745_pinctrl_hog>; 426*4882a593Smuzhiyun 427*4882a593Smuzhiyun i2c5_max96745_pinctrl_hog: hog { 428*4882a593Smuzhiyun i2c { 429*4882a593Smuzhiyun groups = "I2C"; 430*4882a593Smuzhiyun function = "I2C"; 431*4882a593Smuzhiyun }; 432*4882a593Smuzhiyun }; 433*4882a593Smuzhiyun 434*4882a593Smuzhiyun i2c5_max96745_panel_pins: panel-pins { 435*4882a593Smuzhiyun bl-pwm { 436*4882a593Smuzhiyun pins = "MFP0"; 437*4882a593Smuzhiyun function = "GPIO_TX_A_0"; 438*4882a593Smuzhiyun }; 439*4882a593Smuzhiyun }; 440*4882a593Smuzhiyun }; 441*4882a593Smuzhiyun 442*4882a593Smuzhiyun bridge { 443*4882a593Smuzhiyun compatible = "maxim,max96745-bridge"; 444*4882a593Smuzhiyun lock-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; 445*4882a593Smuzhiyun 446*4882a593Smuzhiyun ports { 447*4882a593Smuzhiyun #address-cells = <1>; 448*4882a593Smuzhiyun #size-cells = <0>; 449*4882a593Smuzhiyun 450*4882a593Smuzhiyun port@0 { 451*4882a593Smuzhiyun reg = <0>; 452*4882a593Smuzhiyun 453*4882a593Smuzhiyun i2c5_max96745_in: endpoint { 454*4882a593Smuzhiyun remote-endpoint = <&edp0_out>; 455*4882a593Smuzhiyun }; 456*4882a593Smuzhiyun }; 457*4882a593Smuzhiyun 458*4882a593Smuzhiyun port@1 { 459*4882a593Smuzhiyun reg = <1>; 460*4882a593Smuzhiyun 461*4882a593Smuzhiyun i2c5_max96745_out: endpoint { 462*4882a593Smuzhiyun remote-endpoint = <&i2c5_max96745_panel_in>; 463*4882a593Smuzhiyun }; 464*4882a593Smuzhiyun }; 465*4882a593Smuzhiyun }; 466*4882a593Smuzhiyun }; 467*4882a593Smuzhiyun 468*4882a593Smuzhiyun gmsl@0 { 469*4882a593Smuzhiyun reg = <0>; 470*4882a593Smuzhiyun clock-frequency = <400000>; 471*4882a593Smuzhiyun #address-cells = <1>; 472*4882a593Smuzhiyun #size-cells = <0>; 473*4882a593Smuzhiyun 474*4882a593Smuzhiyun panel@48 { 475*4882a593Smuzhiyun compatible = "boe,av156fht-l83"; 476*4882a593Smuzhiyun reg = <0x48>; 477*4882a593Smuzhiyun backlight = <&i2c5_max96745_backlight>; 478*4882a593Smuzhiyun pinctrl-names = "default"; 479*4882a593Smuzhiyun pinctrl-0 = <&i2c5_max96745_panel_pins>; 480*4882a593Smuzhiyun 481*4882a593Smuzhiyun panel-timing { 482*4882a593Smuzhiyun clock-frequency = <148500000>; 483*4882a593Smuzhiyun hactive = <1920>; 484*4882a593Smuzhiyun vactive = <1080>; 485*4882a593Smuzhiyun hfront-porch = <20>; 486*4882a593Smuzhiyun hsync-len = <20>; 487*4882a593Smuzhiyun hback-porch = <20>; 488*4882a593Smuzhiyun vfront-porch = <250>; 489*4882a593Smuzhiyun vsync-len = <2>; 490*4882a593Smuzhiyun vback-porch = <8>; 491*4882a593Smuzhiyun hsync-active = <0>; 492*4882a593Smuzhiyun vsync-active = <0>; 493*4882a593Smuzhiyun de-active = <0>; 494*4882a593Smuzhiyun pixelclk-active = <0>; 495*4882a593Smuzhiyun }; 496*4882a593Smuzhiyun 497*4882a593Smuzhiyun port { 498*4882a593Smuzhiyun i2c5_max96745_panel_in: endpoint { 499*4882a593Smuzhiyun remote-endpoint = <&i2c5_max96745_out>; 500*4882a593Smuzhiyun }; 501*4882a593Smuzhiyun }; 502*4882a593Smuzhiyun }; 503*4882a593Smuzhiyun }; 504*4882a593Smuzhiyun }; 505*4882a593Smuzhiyun}; 506*4882a593Smuzhiyun 507*4882a593Smuzhiyun&i2c6 { 508*4882a593Smuzhiyun pinctrl-0 = <&i2c6m3_xfer>; 509*4882a593Smuzhiyun clock-frequency = <400000>; 510*4882a593Smuzhiyun status = "okay"; 511*4882a593Smuzhiyun 512*4882a593Smuzhiyun max96755f@40 { 513*4882a593Smuzhiyun compatible = "maxim,max96755f"; 514*4882a593Smuzhiyun reg = <0x40>; 515*4882a593Smuzhiyun pinctrl-names = "default"; 516*4882a593Smuzhiyun pinctrl-0 = <&i2c6_serdes_pins>; 517*4882a593Smuzhiyun #address-cells = <1>; 518*4882a593Smuzhiyun #size-cells = <0>; 519*4882a593Smuzhiyun 520*4882a593Smuzhiyun pinctrl { 521*4882a593Smuzhiyun compatible = "maxim,max96755f-pinctrl"; 522*4882a593Smuzhiyun pinctrl-names = "default"; 523*4882a593Smuzhiyun pinctrl-0 = <&i2c6_max96755f_pinctrl_hog>; 524*4882a593Smuzhiyun 525*4882a593Smuzhiyun i2c6_max96755f_pinctrl_hog: hog { 526*4882a593Smuzhiyun i2c { 527*4882a593Smuzhiyun groups = "I2C"; 528*4882a593Smuzhiyun function = "I2C"; 529*4882a593Smuzhiyun }; 530*4882a593Smuzhiyun }; 531*4882a593Smuzhiyun 532*4882a593Smuzhiyun 533*4882a593Smuzhiyun i2c6_max96755f_panel_pins: panel-pins { 534*4882a593Smuzhiyun bl-pwm { 535*4882a593Smuzhiyun pins = "MFP18"; 536*4882a593Smuzhiyun function = "GPIO_TX_0"; 537*4882a593Smuzhiyun }; 538*4882a593Smuzhiyun }; 539*4882a593Smuzhiyun }; 540*4882a593Smuzhiyun 541*4882a593Smuzhiyun bridge { 542*4882a593Smuzhiyun compatible = "maxim,max96755f-bridge"; 543*4882a593Smuzhiyun lock-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>; 544*4882a593Smuzhiyun 545*4882a593Smuzhiyun ports { 546*4882a593Smuzhiyun #address-cells = <1>; 547*4882a593Smuzhiyun #size-cells = <0>; 548*4882a593Smuzhiyun 549*4882a593Smuzhiyun port@0 { 550*4882a593Smuzhiyun reg = <0>; 551*4882a593Smuzhiyun 552*4882a593Smuzhiyun i2c6_max96755f_in: endpoint { 553*4882a593Smuzhiyun remote-endpoint = <&dsi1_out>; 554*4882a593Smuzhiyun }; 555*4882a593Smuzhiyun }; 556*4882a593Smuzhiyun 557*4882a593Smuzhiyun port@1 { 558*4882a593Smuzhiyun reg = <1>; 559*4882a593Smuzhiyun 560*4882a593Smuzhiyun i2c6_max96755f_out: endpoint { 561*4882a593Smuzhiyun remote-endpoint = <&i2c6_max96755f_panel_in>; 562*4882a593Smuzhiyun }; 563*4882a593Smuzhiyun }; 564*4882a593Smuzhiyun }; 565*4882a593Smuzhiyun }; 566*4882a593Smuzhiyun 567*4882a593Smuzhiyun gmsl@0 { 568*4882a593Smuzhiyun reg = <0>; 569*4882a593Smuzhiyun clock-frequency = <400000>; 570*4882a593Smuzhiyun #address-cells = <1>; 571*4882a593Smuzhiyun #size-cells = <0>; 572*4882a593Smuzhiyun 573*4882a593Smuzhiyun panel@48 { 574*4882a593Smuzhiyun compatible = "boe,av156fht-l83"; 575*4882a593Smuzhiyun reg = <0x48>; 576*4882a593Smuzhiyun backlight = <&i2c6_max96755f_backlight>; 577*4882a593Smuzhiyun pinctrl-names = "default"; 578*4882a593Smuzhiyun pinctrl-0 = <&i2c6_max96755f_panel_pins>; 579*4882a593Smuzhiyun 580*4882a593Smuzhiyun panel-timing { 581*4882a593Smuzhiyun clock-frequency = <148500000>; 582*4882a593Smuzhiyun hactive = <1920>; 583*4882a593Smuzhiyun vactive = <1080>; 584*4882a593Smuzhiyun hfront-porch = <20>; 585*4882a593Smuzhiyun hsync-len = <20>; 586*4882a593Smuzhiyun hback-porch = <20>; 587*4882a593Smuzhiyun vfront-porch = <250>; 588*4882a593Smuzhiyun vsync-len = <2>; 589*4882a593Smuzhiyun vback-porch = <8>; 590*4882a593Smuzhiyun hsync-active = <0>; 591*4882a593Smuzhiyun vsync-active = <0>; 592*4882a593Smuzhiyun de-active = <0>; 593*4882a593Smuzhiyun pixelclk-active = <0>; 594*4882a593Smuzhiyun }; 595*4882a593Smuzhiyun 596*4882a593Smuzhiyun port { 597*4882a593Smuzhiyun i2c6_max96755f_panel_in: endpoint { 598*4882a593Smuzhiyun remote-endpoint = <&i2c6_max96755f_out>; 599*4882a593Smuzhiyun }; 600*4882a593Smuzhiyun }; 601*4882a593Smuzhiyun }; 602*4882a593Smuzhiyun }; 603*4882a593Smuzhiyun }; 604*4882a593Smuzhiyun}; 605*4882a593Smuzhiyun 606*4882a593Smuzhiyun&i2c7 { 607*4882a593Smuzhiyun pinctrl-0 = <&i2c7m3_xfer>; 608*4882a593Smuzhiyun clock-frequency = <400000>; 609*4882a593Smuzhiyun status = "okay"; 610*4882a593Smuzhiyun 611*4882a593Smuzhiyun max96745@42 { 612*4882a593Smuzhiyun compatible = "maxim,max96745"; 613*4882a593Smuzhiyun reg = <0x42>; 614*4882a593Smuzhiyun pinctrl-names = "default"; 615*4882a593Smuzhiyun pinctrl-0 = <&i2c7_serdes_pins>; 616*4882a593Smuzhiyun #address-cells = <1>; 617*4882a593Smuzhiyun #size-cells = <0>; 618*4882a593Smuzhiyun 619*4882a593Smuzhiyun pinctrl { 620*4882a593Smuzhiyun compatible = "maxim,max96745-pinctrl"; 621*4882a593Smuzhiyun pinctrl-names = "default"; 622*4882a593Smuzhiyun pinctrl-0 = <&i2c7_max96745_pinctrl_hog>; 623*4882a593Smuzhiyun 624*4882a593Smuzhiyun i2c7_max96745_pinctrl_hog: hog { 625*4882a593Smuzhiyun i2c { 626*4882a593Smuzhiyun groups = "I2C"; 627*4882a593Smuzhiyun function = "I2C"; 628*4882a593Smuzhiyun }; 629*4882a593Smuzhiyun }; 630*4882a593Smuzhiyun 631*4882a593Smuzhiyun i2c7_max96745_panel_pins: panel-pins { 632*4882a593Smuzhiyun bl-pwm { 633*4882a593Smuzhiyun pins = "MFP0"; 634*4882a593Smuzhiyun function = "GPIO_TX_A_0"; 635*4882a593Smuzhiyun }; 636*4882a593Smuzhiyun }; 637*4882a593Smuzhiyun }; 638*4882a593Smuzhiyun 639*4882a593Smuzhiyun bridge { 640*4882a593Smuzhiyun compatible = "maxim,max96745-bridge"; 641*4882a593Smuzhiyun lock-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; 642*4882a593Smuzhiyun 643*4882a593Smuzhiyun ports { 644*4882a593Smuzhiyun #address-cells = <1>; 645*4882a593Smuzhiyun #size-cells = <0>; 646*4882a593Smuzhiyun 647*4882a593Smuzhiyun port@0 { 648*4882a593Smuzhiyun reg = <0>; 649*4882a593Smuzhiyun 650*4882a593Smuzhiyun i2c7_max96745_in: endpoint { 651*4882a593Smuzhiyun remote-endpoint = <&edp1_out>; 652*4882a593Smuzhiyun }; 653*4882a593Smuzhiyun }; 654*4882a593Smuzhiyun 655*4882a593Smuzhiyun port@1 { 656*4882a593Smuzhiyun reg = <1>; 657*4882a593Smuzhiyun 658*4882a593Smuzhiyun i2c7_max96745_out: endpoint { 659*4882a593Smuzhiyun remote-endpoint = <&i2c7_max96745_panel_in>; 660*4882a593Smuzhiyun }; 661*4882a593Smuzhiyun }; 662*4882a593Smuzhiyun }; 663*4882a593Smuzhiyun }; 664*4882a593Smuzhiyun 665*4882a593Smuzhiyun gmsl@0 { 666*4882a593Smuzhiyun reg = <0>; 667*4882a593Smuzhiyun clock-frequency = <400000>; 668*4882a593Smuzhiyun #address-cells = <1>; 669*4882a593Smuzhiyun #size-cells = <0>; 670*4882a593Smuzhiyun 671*4882a593Smuzhiyun panel@48 { 672*4882a593Smuzhiyun compatible = "boe,av156fht-l83"; 673*4882a593Smuzhiyun reg = <0x48>; 674*4882a593Smuzhiyun backlight = <&i2c7_max96745_backlight>; 675*4882a593Smuzhiyun pinctrl-names = "default"; 676*4882a593Smuzhiyun pinctrl-0 = <&i2c7_max96745_panel_pins>; 677*4882a593Smuzhiyun 678*4882a593Smuzhiyun panel-timing { 679*4882a593Smuzhiyun clock-frequency = <148500000>; 680*4882a593Smuzhiyun hactive = <1920>; 681*4882a593Smuzhiyun vactive = <1080>; 682*4882a593Smuzhiyun hfront-porch = <20>; 683*4882a593Smuzhiyun hsync-len = <20>; 684*4882a593Smuzhiyun hback-porch = <20>; 685*4882a593Smuzhiyun vfront-porch = <250>; 686*4882a593Smuzhiyun vsync-len = <2>; 687*4882a593Smuzhiyun vback-porch = <8>; 688*4882a593Smuzhiyun hsync-active = <0>; 689*4882a593Smuzhiyun vsync-active = <0>; 690*4882a593Smuzhiyun de-active = <0>; 691*4882a593Smuzhiyun pixelclk-active = <0>; 692*4882a593Smuzhiyun }; 693*4882a593Smuzhiyun 694*4882a593Smuzhiyun port { 695*4882a593Smuzhiyun i2c7_max96745_panel_in: endpoint { 696*4882a593Smuzhiyun remote-endpoint = <&i2c7_max96745_out>; 697*4882a593Smuzhiyun }; 698*4882a593Smuzhiyun }; 699*4882a593Smuzhiyun }; 700*4882a593Smuzhiyun }; 701*4882a593Smuzhiyun }; 702*4882a593Smuzhiyun}; 703*4882a593Smuzhiyun 704*4882a593Smuzhiyun&i2c8 { 705*4882a593Smuzhiyun pinctrl-0 = <&i2c8m2_xfer>; 706*4882a593Smuzhiyun clock-frequency = <400000>; 707*4882a593Smuzhiyun status = "okay"; 708*4882a593Smuzhiyun 709*4882a593Smuzhiyun max96745@42 { 710*4882a593Smuzhiyun compatible = "maxim,max96745"; 711*4882a593Smuzhiyun reg = <0x42>; 712*4882a593Smuzhiyun pinctrl-names = "default"; 713*4882a593Smuzhiyun pinctrl-0 = <&i2c8_serdes_pins>; 714*4882a593Smuzhiyun #address-cells = <1>; 715*4882a593Smuzhiyun #size-cells = <0>; 716*4882a593Smuzhiyun 717*4882a593Smuzhiyun pinctrl { 718*4882a593Smuzhiyun compatible = "maxim,max96745-pinctrl"; 719*4882a593Smuzhiyun pinctrl-names = "default"; 720*4882a593Smuzhiyun pinctrl-0 = <&i2c8_max96745_pinctrl_hog>; 721*4882a593Smuzhiyun 722*4882a593Smuzhiyun i2c8_max96745_pinctrl_hog: hog { 723*4882a593Smuzhiyun i2c { 724*4882a593Smuzhiyun groups = "I2C"; 725*4882a593Smuzhiyun function = "I2C"; 726*4882a593Smuzhiyun }; 727*4882a593Smuzhiyun }; 728*4882a593Smuzhiyun 729*4882a593Smuzhiyun i2c8_max96745_panel_pins: panel-pins { 730*4882a593Smuzhiyun bl-pwm { 731*4882a593Smuzhiyun pins = "MFP0"; 732*4882a593Smuzhiyun function = "GPIO_TX_A_0"; 733*4882a593Smuzhiyun }; 734*4882a593Smuzhiyun }; 735*4882a593Smuzhiyun }; 736*4882a593Smuzhiyun 737*4882a593Smuzhiyun bridge { 738*4882a593Smuzhiyun compatible = "maxim,max96745-bridge"; 739*4882a593Smuzhiyun lock-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; 740*4882a593Smuzhiyun 741*4882a593Smuzhiyun ports { 742*4882a593Smuzhiyun #address-cells = <1>; 743*4882a593Smuzhiyun #size-cells = <0>; 744*4882a593Smuzhiyun 745*4882a593Smuzhiyun port@0 { 746*4882a593Smuzhiyun reg = <0>; 747*4882a593Smuzhiyun 748*4882a593Smuzhiyun i2c8_max96745_in: endpoint { 749*4882a593Smuzhiyun remote-endpoint = <&dp1_out>; 750*4882a593Smuzhiyun }; 751*4882a593Smuzhiyun }; 752*4882a593Smuzhiyun 753*4882a593Smuzhiyun port@1 { 754*4882a593Smuzhiyun reg = <1>; 755*4882a593Smuzhiyun 756*4882a593Smuzhiyun i2c8_max96745_out: endpoint { 757*4882a593Smuzhiyun remote-endpoint = <&i2c8_max96745_panel_in>; 758*4882a593Smuzhiyun }; 759*4882a593Smuzhiyun }; 760*4882a593Smuzhiyun }; 761*4882a593Smuzhiyun }; 762*4882a593Smuzhiyun 763*4882a593Smuzhiyun gmsl@0 { 764*4882a593Smuzhiyun reg = <0>; 765*4882a593Smuzhiyun clock-frequency = <400000>; 766*4882a593Smuzhiyun #address-cells = <1>; 767*4882a593Smuzhiyun #size-cells = <0>; 768*4882a593Smuzhiyun 769*4882a593Smuzhiyun panel@48 { 770*4882a593Smuzhiyun compatible = "boe,av156fht-l83"; 771*4882a593Smuzhiyun reg = <0x48>; 772*4882a593Smuzhiyun backlight = <&i2c8_max96745_backlight>; 773*4882a593Smuzhiyun pinctrl-names = "default"; 774*4882a593Smuzhiyun pinctrl-0 = <&i2c8_max96745_panel_pins>; 775*4882a593Smuzhiyun 776*4882a593Smuzhiyun panel-timing { 777*4882a593Smuzhiyun clock-frequency = <148500000>; 778*4882a593Smuzhiyun hactive = <1920>; 779*4882a593Smuzhiyun vactive = <1080>; 780*4882a593Smuzhiyun hfront-porch = <20>; 781*4882a593Smuzhiyun hsync-len = <20>; 782*4882a593Smuzhiyun hback-porch = <20>; 783*4882a593Smuzhiyun vfront-porch = <250>; 784*4882a593Smuzhiyun vsync-len = <2>; 785*4882a593Smuzhiyun vback-porch = <8>; 786*4882a593Smuzhiyun hsync-active = <0>; 787*4882a593Smuzhiyun vsync-active = <0>; 788*4882a593Smuzhiyun de-active = <0>; 789*4882a593Smuzhiyun pixelclk-active = <0>; 790*4882a593Smuzhiyun }; 791*4882a593Smuzhiyun 792*4882a593Smuzhiyun port { 793*4882a593Smuzhiyun i2c8_max96745_panel_in: endpoint { 794*4882a593Smuzhiyun remote-endpoint = <&i2c8_max96745_out>; 795*4882a593Smuzhiyun }; 796*4882a593Smuzhiyun }; 797*4882a593Smuzhiyun }; 798*4882a593Smuzhiyun }; 799*4882a593Smuzhiyun }; 800*4882a593Smuzhiyun}; 801*4882a593Smuzhiyun 802*4882a593Smuzhiyun&pinctrl { 803*4882a593Smuzhiyun serdes { 804*4882a593Smuzhiyun i2c2_serdes_pins: i2c2-serdes-pins { 805*4882a593Smuzhiyun rockchip,pins = 806*4882a593Smuzhiyun <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; 807*4882a593Smuzhiyun }; 808*4882a593Smuzhiyun 809*4882a593Smuzhiyun i2c3_serdes_pins: i2c3-serdes-pins { 810*4882a593Smuzhiyun rockchip,pins = 811*4882a593Smuzhiyun <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; 812*4882a593Smuzhiyun }; 813*4882a593Smuzhiyun 814*4882a593Smuzhiyun i2c5_serdes_pins: i2c5-serdes-pins { 815*4882a593Smuzhiyun rockchip,pins = 816*4882a593Smuzhiyun <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; 817*4882a593Smuzhiyun }; 818*4882a593Smuzhiyun 819*4882a593Smuzhiyun i2c6_serdes_pins: i2c6-serdes-pins { 820*4882a593Smuzhiyun rockchip,pins = 821*4882a593Smuzhiyun <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; 822*4882a593Smuzhiyun }; 823*4882a593Smuzhiyun 824*4882a593Smuzhiyun i2c7_serdes_pins: i2c7-serdes-pins { 825*4882a593Smuzhiyun rockchip,pins = 826*4882a593Smuzhiyun <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; 827*4882a593Smuzhiyun }; 828*4882a593Smuzhiyun 829*4882a593Smuzhiyun i2c8_serdes_pins: i2c8-serdes-pins { 830*4882a593Smuzhiyun rockchip,pins = 831*4882a593Smuzhiyun <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; 832*4882a593Smuzhiyun }; 833*4882a593Smuzhiyun }; 834*4882a593Smuzhiyun}; 835*4882a593Smuzhiyun 836*4882a593Smuzhiyun&pwm6 { 837*4882a593Smuzhiyun pinctrl-0 = <&pwm6m1_pins>; 838*4882a593Smuzhiyun status = "okay"; 839*4882a593Smuzhiyun}; 840*4882a593Smuzhiyun 841*4882a593Smuzhiyun&pwm10 { 842*4882a593Smuzhiyun pinctrl-0 = <&pwm10m2_pins>; 843*4882a593Smuzhiyun status = "okay"; 844*4882a593Smuzhiyun}; 845*4882a593Smuzhiyun 846*4882a593Smuzhiyun&pwm11 { 847*4882a593Smuzhiyun pinctrl-0 = <&pwm11m3_pins>; 848*4882a593Smuzhiyun status = "okay"; 849*4882a593Smuzhiyun}; 850*4882a593Smuzhiyun 851*4882a593Smuzhiyun&pwm12 { 852*4882a593Smuzhiyun pinctrl-0 = <&pwm12m1_pins>; 853*4882a593Smuzhiyun status = "okay"; 854*4882a593Smuzhiyun}; 855*4882a593Smuzhiyun 856*4882a593Smuzhiyun&pwm13 { 857*4882a593Smuzhiyun pinctrl-0 = <&pwm13m1_pins>; 858*4882a593Smuzhiyun status = "okay"; 859*4882a593Smuzhiyun}; 860*4882a593Smuzhiyun 861*4882a593Smuzhiyun&pwm14 { 862*4882a593Smuzhiyun pinctrl-0 = <&pwm14m0_pins>; 863*4882a593Smuzhiyun status = "okay"; 864*4882a593Smuzhiyun}; 865