1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include "rk3588-vehicle-evb-v20.dtsi" 10*4882a593Smuzhiyun#include "rk3588-vehicle-evb-mipi-nvp6188.dtsi" 11*4882a593Smuzhiyun#include "rk3588-vehicle-evb-image-reverse.dtsi" 12*4882a593Smuzhiyun#include "rk3588-vehicle-serdes-display-v20.dtsi" 13*4882a593Smuzhiyun#include "rk3588-android.dtsi" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun/ { 16*4882a593Smuzhiyun model = "Rockchip RK3588 VEHICLE EVB V20 Board"; 17*4882a593Smuzhiyun compatible = "rockchip,rk3588-vehicle-evb-v20", "rockchip,rk3588"; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun bt-sound { 20*4882a593Smuzhiyun compatible = "simple-audio-card"; 21*4882a593Smuzhiyun simple-audio-card,format = "dsp_a"; 22*4882a593Smuzhiyun simple-audio-card,bitclock-inversion = <1>; 23*4882a593Smuzhiyun simple-audio-card,mclk-fs = <256>; 24*4882a593Smuzhiyun simple-audio-card,name = "rockchip,bt"; 25*4882a593Smuzhiyun simple-audio-card,cpu { 26*4882a593Smuzhiyun sound-dai = <&i2s2_2ch>; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun simple-audio-card,codec { 30*4882a593Smuzhiyun sound-dai = <&bt_sco 1>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun bt_sco: bt-sco { 35*4882a593Smuzhiyun compatible = "delta,dfbmcs320"; 36*4882a593Smuzhiyun #sound-dai-cells = <1>; 37*4882a593Smuzhiyun status = "okay"; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun nvp6188_osc: oscillator { 41*4882a593Smuzhiyun compatible = "fixed-clock"; 42*4882a593Smuzhiyun #clock-cells = <1>; 43*4882a593Smuzhiyun clock-frequency = <27000000>; 44*4882a593Smuzhiyun clock-output-names = "nvp6188-osc"; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun}; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun&cif_sensor { 49*4882a593Smuzhiyun nvp6188 { 50*4882a593Smuzhiyun powerdown-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun}; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun&i2c7 { 55*4882a593Smuzhiyun status = "okay"; 56*4882a593Smuzhiyun /delete-node/ nvp6188@33; 57*4882a593Smuzhiyun nvp6188: nvp6188@31 { 58*4882a593Smuzhiyun compatible = "nvp6188"; 59*4882a593Smuzhiyun status = "okay"; 60*4882a593Smuzhiyun reg = <0x31>; 61*4882a593Smuzhiyun clocks = <&nvp6188_osc 0>; 62*4882a593Smuzhiyun clock-names = "xvclk"; 63*4882a593Smuzhiyun power-domains = <&power RK3588_PD_VI>; 64*4882a593Smuzhiyun rockchip,grf = <&sys_grf>; 65*4882a593Smuzhiyun /*power-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;*/ 66*4882a593Smuzhiyun reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; 67*4882a593Smuzhiyun rockchip,camera-module-index = <0>; 68*4882a593Smuzhiyun rockchip,camera-module-facing = "back"; 69*4882a593Smuzhiyun rockchip,camera-module-name = "nvp6188"; 70*4882a593Smuzhiyun rockchip,camera-module-lens-name = "nvp6188"; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun port { 73*4882a593Smuzhiyun nvp6188_out: endpoint { 74*4882a593Smuzhiyun remote-endpoint = <&mipi_dphy0_in_nvp6188>; 75*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun}; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun&i2s2_2ch { 82*4882a593Smuzhiyun pinctrl-0 = <&i2s2m1_lrck 83*4882a593Smuzhiyun &i2s2m1_sclk 84*4882a593Smuzhiyun &i2s2m1_sdi 85*4882a593Smuzhiyun &i2s2m1_sdo>; 86*4882a593Smuzhiyun status = "okay"; 87*4882a593Smuzhiyun}; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun&rockchip_suspend { 90*4882a593Smuzhiyun rockchip,sleep-mode-config = < 91*4882a593Smuzhiyun (0 92*4882a593Smuzhiyun | RKPM_SLP_ARMOFF_DDRPD 93*4882a593Smuzhiyun | RKPM_SLP_PMU_PMUALIVE_32K 94*4882a593Smuzhiyun | RKPM_SLP_PMU_DIS_OSC 95*4882a593Smuzhiyun | RKPM_SLP_32K_EXT 96*4882a593Smuzhiyun ) 97*4882a593Smuzhiyun >; 98*4882a593Smuzhiyun rockchip,wakeup-config = < 99*4882a593Smuzhiyun (0 100*4882a593Smuzhiyun | RKPM_GPIO_WKUP_EN 101*4882a593Smuzhiyun ) 102*4882a593Smuzhiyun >; 103*4882a593Smuzhiyun status = "okay"; 104*4882a593Smuzhiyun}; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun&vdd_log_s0 { 107*4882a593Smuzhiyun regulator-state-mem { 108*4882a593Smuzhiyun regulator-on-in-suspend; 109*4882a593Smuzhiyun regulator-suspend-microvolt = <800000>; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun}; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun&vcc_3v3_s0 { 114*4882a593Smuzhiyun regulator-state-mem { 115*4882a593Smuzhiyun regulator-on-in-suspend; 116*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun}; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun&vcc_1v8_s0 { 121*4882a593Smuzhiyun regulator-state-mem { 122*4882a593Smuzhiyun regulator-on-in-suspend; 123*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun}; 126