1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun&csi2_dphy0_hw { 8*4882a593Smuzhiyun status = "okay"; 9*4882a593Smuzhiyun}; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun&csi2_dphy0 { 12*4882a593Smuzhiyun status = "okay"; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun ports { 15*4882a593Smuzhiyun #address-cells = <1>; 16*4882a593Smuzhiyun #size-cells = <0>; 17*4882a593Smuzhiyun port@0 { 18*4882a593Smuzhiyun reg = <0>; 19*4882a593Smuzhiyun #address-cells = <1>; 20*4882a593Smuzhiyun #size-cells = <0>; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun mipi_dphy0_in_nvp6188: endpoint@1 { 23*4882a593Smuzhiyun reg = <1>; 24*4882a593Smuzhiyun remote-endpoint = <&nvp6188_out>; 25*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun port@1 { 29*4882a593Smuzhiyun reg = <1>; 30*4882a593Smuzhiyun #address-cells = <1>; 31*4882a593Smuzhiyun #size-cells = <0>; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun csidphy0_out: endpoint@0 { 34*4882a593Smuzhiyun reg = <0>; 35*4882a593Smuzhiyun remote-endpoint = <&mipi2_csi2_input>; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun}; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun&i2c7 { 42*4882a593Smuzhiyun status = "okay"; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun nvp6188: nvp6188@31 { 46*4882a593Smuzhiyun compatible = "nvp6188"; 47*4882a593Smuzhiyun status = "okay"; 48*4882a593Smuzhiyun reg = <0x31>; 49*4882a593Smuzhiyun clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; 50*4882a593Smuzhiyun clock-names = "xvclk"; 51*4882a593Smuzhiyun power-domains = <&power RK3588_PD_VI>; 52*4882a593Smuzhiyun pinctrl-names = "default"; 53*4882a593Smuzhiyun pinctrl-0 = <&mipim1_camera1_clk>; 54*4882a593Smuzhiyun rockchip,grf = <&sys_grf>; 55*4882a593Smuzhiyun /*power-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;*/ 56*4882a593Smuzhiyun reset-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; 57*4882a593Smuzhiyun rockchip,camera-module-index = <0>; 58*4882a593Smuzhiyun rockchip,camera-module-facing = "back"; 59*4882a593Smuzhiyun rockchip,camera-module-name = "nvp6188"; 60*4882a593Smuzhiyun rockchip,camera-module-lens-name = "nvp6188"; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun port { 63*4882a593Smuzhiyun nvp6188_out: endpoint { 64*4882a593Smuzhiyun remote-endpoint = <&mipi_dphy0_in_nvp6188>; 65*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun}; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun&mipi2_csi2 { 72*4882a593Smuzhiyun status = "okay"; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun ports { 75*4882a593Smuzhiyun #address-cells = <1>; 76*4882a593Smuzhiyun #size-cells = <0>; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun port@0 { 79*4882a593Smuzhiyun reg = <0>; 80*4882a593Smuzhiyun #address-cells = <1>; 81*4882a593Smuzhiyun #size-cells = <0>; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun mipi2_csi2_input: endpoint@1 { 84*4882a593Smuzhiyun reg = <1>; 85*4882a593Smuzhiyun remote-endpoint = <&csidphy0_out>; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun port@1 { 90*4882a593Smuzhiyun reg = <1>; 91*4882a593Smuzhiyun #address-cells = <1>; 92*4882a593Smuzhiyun #size-cells = <0>; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun mipi2_csi2_output: endpoint@0 { 95*4882a593Smuzhiyun reg = <0>; 96*4882a593Smuzhiyun remote-endpoint = <&cif_mipi2_in>; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun}; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun&rkcif_mipi_lvds2 { 103*4882a593Smuzhiyun status = "okay"; 104*4882a593Smuzhiyun /* parameters for do cif reset detecting: 105*4882a593Smuzhiyun * index0: monitor mode, 106*4882a593Smuzhiyun 0 for idle, 107*4882a593Smuzhiyun 1 for continue, 108*4882a593Smuzhiyun 2 for trigger, 109*4882a593Smuzhiyun 3 for hotplug (for nextchip) 110*4882a593Smuzhiyun * index1: the frame id to start timer, 111*4882a593Smuzhiyun min is 2 112*4882a593Smuzhiyun * index2: frame num of monitoring cycle 113*4882a593Smuzhiyun * index3: err time for keep monitoring 114*4882a593Smuzhiyun after finding out err (ms) 115*4882a593Smuzhiyun * index4: csi2 err reference val for resetting 116*4882a593Smuzhiyun */ 117*4882a593Smuzhiyun rockchip,cif-monitor = <3 2 1 1000 5>; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun port { 120*4882a593Smuzhiyun cif_mipi2_in: endpoint { 121*4882a593Smuzhiyun remote-endpoint = <&mipi2_csi2_output>; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun}; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun&rkcif { 127*4882a593Smuzhiyun status = "okay"; 128*4882a593Smuzhiyun rockchip,android-usb-camerahal-enable; 129*4882a593Smuzhiyun // memory-region = <&cif_reserved>; 130*4882a593Smuzhiyun}; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun&rkcif_mmu { 133*4882a593Smuzhiyun status = "okay"; 134*4882a593Smuzhiyun}; 135*4882a593Smuzhiyun 136