1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun max96712_osc: oscillator { 9*4882a593Smuzhiyun compatible = "fixed-clock"; 10*4882a593Smuzhiyun #clock-cells = <1>; 11*4882a593Smuzhiyun clock-frequency = <25000000>; 12*4882a593Smuzhiyun clock-output-names = "max96712-osc"; 13*4882a593Smuzhiyun }; 14*4882a593Smuzhiyun}; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun&csi2_dphy1_hw { 17*4882a593Smuzhiyun status = "okay"; 18*4882a593Smuzhiyun}; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun&csi2_dphy3 { 21*4882a593Smuzhiyun status = "okay"; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun ports { 24*4882a593Smuzhiyun #address-cells = <1>; 25*4882a593Smuzhiyun #size-cells = <0>; 26*4882a593Smuzhiyun port@0 { 27*4882a593Smuzhiyun reg = <0>; 28*4882a593Smuzhiyun #address-cells = <1>; 29*4882a593Smuzhiyun #size-cells = <0>; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun mipi_dphy1_in_max96712: endpoint@1 { 32*4882a593Smuzhiyun reg = <1>; 33*4882a593Smuzhiyun remote-endpoint = <&max96712_out>; 34*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun port@1 { 38*4882a593Smuzhiyun reg = <1>; 39*4882a593Smuzhiyun #address-cells = <1>; 40*4882a593Smuzhiyun #size-cells = <0>; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun csidphy1_out: endpoint@0 { 43*4882a593Smuzhiyun reg = <0>; 44*4882a593Smuzhiyun remote-endpoint = <&mipi4_csi2_input>; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun}; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun&i2c6 { 51*4882a593Smuzhiyun status = "okay"; 52*4882a593Smuzhiyun pinctrl-names = "default"; 53*4882a593Smuzhiyun pinctrl-0 = <&i2c6m3_xfer>, <&max96712_errb>, <&max96712_int>; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun max96712: max96712@29 { 56*4882a593Smuzhiyun compatible = "max96712"; 57*4882a593Smuzhiyun status = "okay"; 58*4882a593Smuzhiyun reg = <0x29>; 59*4882a593Smuzhiyun clock-names = "xvclk"; 60*4882a593Smuzhiyun clocks = <&max96712_osc 0>; 61*4882a593Smuzhiyun power-domains = <&power RK3588_PD_VI>; 62*4882a593Smuzhiyun rockchip,grf = <&sys_grf>; 63*4882a593Smuzhiyun power-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; 64*4882a593Smuzhiyun pocen-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; 65*4882a593Smuzhiyun //reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; 66*4882a593Smuzhiyun lock-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; 67*4882a593Smuzhiyun auto-init-deskew-mask = <0x03>; 68*4882a593Smuzhiyun frame-sync-period = <0>; 69*4882a593Smuzhiyun rockchip,camera-module-index = <0>; 70*4882a593Smuzhiyun rockchip,camera-module-facing = "back"; 71*4882a593Smuzhiyun rockchip,camera-module-name = "max96712"; 72*4882a593Smuzhiyun rockchip,camera-module-lens-name = "max96712"; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun port { 75*4882a593Smuzhiyun max96712_out: endpoint { 76*4882a593Smuzhiyun remote-endpoint = <&mipi_dphy1_in_max96712>; 77*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun}; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun&mipi4_csi2 { 84*4882a593Smuzhiyun status = "okay"; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun ports { 87*4882a593Smuzhiyun #address-cells = <1>; 88*4882a593Smuzhiyun #size-cells = <0>; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun port@0 { 91*4882a593Smuzhiyun reg = <0>; 92*4882a593Smuzhiyun #address-cells = <1>; 93*4882a593Smuzhiyun #size-cells = <0>; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun mipi4_csi2_input: endpoint@1 { 96*4882a593Smuzhiyun reg = <1>; 97*4882a593Smuzhiyun remote-endpoint = <&csidphy1_out>; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun port@1 { 102*4882a593Smuzhiyun reg = <1>; 103*4882a593Smuzhiyun #address-cells = <1>; 104*4882a593Smuzhiyun #size-cells = <0>; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun mipi4_csi2_output: endpoint@0 { 107*4882a593Smuzhiyun reg = <0>; 108*4882a593Smuzhiyun remote-endpoint = <&cif_mipi2_in>; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun}; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun&rkcif_mipi_lvds4 { 115*4882a593Smuzhiyun status = "okay"; 116*4882a593Smuzhiyun /* parameters for do cif reset detecting: 117*4882a593Smuzhiyun * index0: monitor mode, 118*4882a593Smuzhiyun 0 for idle, 119*4882a593Smuzhiyun 1 for continue, 120*4882a593Smuzhiyun 2 for trigger, 121*4882a593Smuzhiyun 3 for hotplug (for nextchip) 122*4882a593Smuzhiyun * index1: the frame id to start timer, 123*4882a593Smuzhiyun min is 2 124*4882a593Smuzhiyun * index2: frame num of monitoring cycle 125*4882a593Smuzhiyun * index3: err time for keep monitoring 126*4882a593Smuzhiyun after finding out err (ms) 127*4882a593Smuzhiyun * index4: csi2 err reference val for resetting 128*4882a593Smuzhiyun */ 129*4882a593Smuzhiyun rockchip,cif-monitor = <3 2 1 1000 5>; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun port { 132*4882a593Smuzhiyun cif_mipi2_in: endpoint { 133*4882a593Smuzhiyun remote-endpoint = <&mipi4_csi2_output>; 134*4882a593Smuzhiyun }; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun}; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun&rkcif { 139*4882a593Smuzhiyun status = "okay"; 140*4882a593Smuzhiyun rockchip,android-usb-camerahal-enable; 141*4882a593Smuzhiyun}; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun&rkcif_mmu { 144*4882a593Smuzhiyun status = "okay"; 145*4882a593Smuzhiyun}; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun&pinctrl { 148*4882a593Smuzhiyun max96712 { 149*4882a593Smuzhiyun max96712_errb: max96712-errb { 150*4882a593Smuzhiyun rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun max96712_int: max96712-int { 154*4882a593Smuzhiyun rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun }; 157*4882a593Smuzhiyun}; 158