1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun/dts-v1/;
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun#include "rk3588-pcie-ep-demo.dtsi"
10*4882a593Smuzhiyun#include "rk3588-linux.dtsi"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun/ {
13*4882a593Smuzhiyun	model = "Rockchip RK3588 PCIE EP Demo V11 Board";
14*4882a593Smuzhiyun	compatible = "rockchip,rk3588-pcie-ep-demo-v11", "rockchip,rk3588";
15*4882a593Smuzhiyun};
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun&hdmi1_in_vp2 {
18*4882a593Smuzhiyun	status = "okay";
19*4882a593Smuzhiyun};
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun&route_hdmi1 {
22*4882a593Smuzhiyun	status = "okay";
23*4882a593Smuzhiyun	force-output;
24*4882a593Smuzhiyun	connect = <&vp2_out_hdmi1>;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun	force_timing {
27*4882a593Smuzhiyun		clock-frequency = <65000000>;
28*4882a593Smuzhiyun		hactive = <1024>;
29*4882a593Smuzhiyun		vactive = <768>;
30*4882a593Smuzhiyun		hfront-porch = <24>;
31*4882a593Smuzhiyun		hsync-len = <136>;
32*4882a593Smuzhiyun		hback-porch = <160>;
33*4882a593Smuzhiyun		vfront-porch = <3>;
34*4882a593Smuzhiyun		vsync-len = <6>;
35*4882a593Smuzhiyun		vback-porch = <29>;
36*4882a593Smuzhiyun		hsync-active = <0>;
37*4882a593Smuzhiyun		vsync-active = <0>;
38*4882a593Smuzhiyun		de-active = <0>;
39*4882a593Smuzhiyun		pixelclk-active = <0>;
40*4882a593Smuzhiyun	};
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun};
43