1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include <dt-bindings/display/rockchip_vop.h> 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun backlight: backlight { 12*4882a593Smuzhiyun compatible = "pwm-backlight"; 13*4882a593Smuzhiyun brightness-levels = < 14*4882a593Smuzhiyun 0 20 20 21 21 22 22 23 15*4882a593Smuzhiyun 23 24 24 25 25 26 26 27 16*4882a593Smuzhiyun 27 28 28 29 29 30 30 31 17*4882a593Smuzhiyun 31 32 32 33 33 34 34 35 18*4882a593Smuzhiyun 35 36 36 37 37 38 38 39 19*4882a593Smuzhiyun 40 41 42 43 44 45 46 47 20*4882a593Smuzhiyun 48 49 50 51 52 53 54 55 21*4882a593Smuzhiyun 56 57 58 59 60 61 62 63 22*4882a593Smuzhiyun 64 65 66 67 68 69 70 71 23*4882a593Smuzhiyun 72 73 74 75 76 77 78 79 24*4882a593Smuzhiyun 80 81 82 83 84 85 86 87 25*4882a593Smuzhiyun 88 89 90 91 92 93 94 95 26*4882a593Smuzhiyun 96 97 98 99 100 101 102 103 27*4882a593Smuzhiyun 104 105 106 107 108 109 110 111 28*4882a593Smuzhiyun 112 113 114 115 116 117 118 119 29*4882a593Smuzhiyun 120 121 122 123 124 125 126 127 30*4882a593Smuzhiyun 128 129 130 131 132 133 134 135 31*4882a593Smuzhiyun 136 137 138 139 140 141 142 143 32*4882a593Smuzhiyun 144 145 146 147 148 149 150 151 33*4882a593Smuzhiyun 152 153 154 155 156 157 158 159 34*4882a593Smuzhiyun 160 161 162 163 164 165 166 167 35*4882a593Smuzhiyun 168 169 170 171 172 173 174 175 36*4882a593Smuzhiyun 176 177 178 179 180 181 182 183 37*4882a593Smuzhiyun 184 185 186 187 188 189 190 191 38*4882a593Smuzhiyun 192 193 194 195 196 197 198 199 39*4882a593Smuzhiyun 200 201 202 203 204 205 206 207 40*4882a593Smuzhiyun 208 209 210 211 212 213 214 215 41*4882a593Smuzhiyun 216 217 218 219 220 221 222 223 42*4882a593Smuzhiyun 224 225 226 227 228 229 230 231 43*4882a593Smuzhiyun 232 233 234 235 236 237 238 239 44*4882a593Smuzhiyun 240 241 242 243 244 245 246 247 45*4882a593Smuzhiyun 248 249 250 251 252 253 254 255 46*4882a593Smuzhiyun >; 47*4882a593Smuzhiyun default-brightness-level = <200>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun vcc12v_dcin: vcc12v-dcin { 51*4882a593Smuzhiyun compatible = "regulator-fixed"; 52*4882a593Smuzhiyun regulator-name = "vcc12v_dcin"; 53*4882a593Smuzhiyun regulator-always-on; 54*4882a593Smuzhiyun regulator-boot-on; 55*4882a593Smuzhiyun regulator-min-microvolt = <12000000>; 56*4882a593Smuzhiyun regulator-max-microvolt = <12000000>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun vcc5v0_sys: vcc5v0-sys { 60*4882a593Smuzhiyun compatible = "regulator-fixed"; 61*4882a593Smuzhiyun regulator-name = "vcc5v0_sys"; 62*4882a593Smuzhiyun regulator-always-on; 63*4882a593Smuzhiyun regulator-boot-on; 64*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 65*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 66*4882a593Smuzhiyun vin-supply = <&vcc12v_dcin>; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun vcc5v0_usbdcin: vcc5v0-usbdcin { 70*4882a593Smuzhiyun compatible = "regulator-fixed"; 71*4882a593Smuzhiyun regulator-name = "vcc5v0_usbdcin"; 72*4882a593Smuzhiyun regulator-always-on; 73*4882a593Smuzhiyun regulator-boot-on; 74*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 75*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 76*4882a593Smuzhiyun vin-supply = <&vcc12v_dcin>; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun}; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun&cpu_b0 { 81*4882a593Smuzhiyun cpu-supply = <&vdd_cpu_big0_s0>; 82*4882a593Smuzhiyun mem-supply = <&vdd_cpu_big0_mem_s0>; 83*4882a593Smuzhiyun}; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun&cpu_b2 { 86*4882a593Smuzhiyun cpu-supply = <&vdd_cpu_big1_s0>; 87*4882a593Smuzhiyun mem-supply = <&vdd_cpu_big1_mem_s0>; 88*4882a593Smuzhiyun}; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun&cpu_l0 { 91*4882a593Smuzhiyun cpu-supply = <&vdd_cpu_lit_s0>; 92*4882a593Smuzhiyun mem-supply = <&vdd_cpu_lit_mem_s0>; 93*4882a593Smuzhiyun}; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun&dfi { 96*4882a593Smuzhiyun status = "okay"; 97*4882a593Smuzhiyun}; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun&dmc { 100*4882a593Smuzhiyun center-supply = <&vdd_ddr_s0>; 101*4882a593Smuzhiyun mem-supply = <&vdd_log_s0>; 102*4882a593Smuzhiyun status = "okay"; 103*4882a593Smuzhiyun}; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun&gpu { 106*4882a593Smuzhiyun mali-supply = <&vdd_gpu_s0>; 107*4882a593Smuzhiyun mem-supply = <&vdd_gpu_mem_s0>; 108*4882a593Smuzhiyun status = "okay"; 109*4882a593Smuzhiyun}; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun&gpu_opp_table { 112*4882a593Smuzhiyun /delete-node/ opp-198000000; 113*4882a593Smuzhiyun /delete-node/ opp-297000000; 114*4882a593Smuzhiyun /delete-node/ opp-396000000; 115*4882a593Smuzhiyun /delete-node/ opp-594000000; 116*4882a593Smuzhiyun}; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun&iep { 119*4882a593Smuzhiyun status = "okay"; 120*4882a593Smuzhiyun}; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun&iep_mmu { 123*4882a593Smuzhiyun status = "okay"; 124*4882a593Smuzhiyun}; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun&jpegd { 127*4882a593Smuzhiyun status = "okay"; 128*4882a593Smuzhiyun}; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun&jpegd_mmu { 131*4882a593Smuzhiyun status = "okay"; 132*4882a593Smuzhiyun}; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun&jpege_ccu { 135*4882a593Smuzhiyun status = "okay"; 136*4882a593Smuzhiyun}; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun&jpege0 { 139*4882a593Smuzhiyun status = "okay"; 140*4882a593Smuzhiyun}; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun&jpege0_mmu { 143*4882a593Smuzhiyun status = "okay"; 144*4882a593Smuzhiyun}; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun&jpege1 { 147*4882a593Smuzhiyun status = "okay"; 148*4882a593Smuzhiyun}; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun&jpege1_mmu { 151*4882a593Smuzhiyun status = "okay"; 152*4882a593Smuzhiyun}; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun&jpege2 { 155*4882a593Smuzhiyun status = "okay"; 156*4882a593Smuzhiyun}; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun&jpege2_mmu { 159*4882a593Smuzhiyun status = "okay"; 160*4882a593Smuzhiyun}; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun&jpege3 { 163*4882a593Smuzhiyun status = "okay"; 164*4882a593Smuzhiyun}; 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun&jpege3_mmu { 167*4882a593Smuzhiyun status = "okay"; 168*4882a593Smuzhiyun}; 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun&mpp_srv { 171*4882a593Smuzhiyun status = "okay"; 172*4882a593Smuzhiyun}; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun&rga2 { 175*4882a593Smuzhiyun status = "okay"; 176*4882a593Smuzhiyun}; 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun&rga3_core0 { 179*4882a593Smuzhiyun status = "okay"; 180*4882a593Smuzhiyun}; 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun&rga3_0_mmu { 183*4882a593Smuzhiyun status = "okay"; 184*4882a593Smuzhiyun}; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun&rga3_core1 { 187*4882a593Smuzhiyun status = "okay"; 188*4882a593Smuzhiyun}; 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun&rga3_1_mmu { 191*4882a593Smuzhiyun status = "okay"; 192*4882a593Smuzhiyun}; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun&rknpu { 195*4882a593Smuzhiyun rknpu-supply = <&vdd_npu_s0>; 196*4882a593Smuzhiyun mem-supply = <&vdd_npu_mem_s0>; 197*4882a593Smuzhiyun status = "okay"; 198*4882a593Smuzhiyun}; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun&rknpu_mmu { 201*4882a593Smuzhiyun status = "okay"; 202*4882a593Smuzhiyun}; 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun&rkvdec_ccu { 205*4882a593Smuzhiyun status = "okay"; 206*4882a593Smuzhiyun}; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun&rkvdec0 { 209*4882a593Smuzhiyun status = "okay"; 210*4882a593Smuzhiyun}; 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun&rkvdec0_mmu { 213*4882a593Smuzhiyun status = "okay"; 214*4882a593Smuzhiyun}; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun&rkvdec1 { 217*4882a593Smuzhiyun status = "okay"; 218*4882a593Smuzhiyun}; 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun&rkvdec1_mmu { 221*4882a593Smuzhiyun status = "okay"; 222*4882a593Smuzhiyun}; 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun&rkvenc_ccu { 225*4882a593Smuzhiyun status = "okay"; 226*4882a593Smuzhiyun}; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun&rkvenc0 { 229*4882a593Smuzhiyun venc-supply = <&vdd_vdenc_s0>; 230*4882a593Smuzhiyun mem-supply = <&vdd_vdenc_mem_s0>; 231*4882a593Smuzhiyun status = "okay"; 232*4882a593Smuzhiyun}; 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun&rkvenc0_mmu { 235*4882a593Smuzhiyun status = "okay"; 236*4882a593Smuzhiyun}; 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun&rkvenc1 { 239*4882a593Smuzhiyun venc-supply = <&vdd_vdenc_s0>; 240*4882a593Smuzhiyun mem-supply = <&vdd_vdenc_mem_s0>; 241*4882a593Smuzhiyun status = "okay"; 242*4882a593Smuzhiyun}; 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun&rkvenc1_mmu { 245*4882a593Smuzhiyun status = "okay"; 246*4882a593Smuzhiyun}; 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun&saradc { 249*4882a593Smuzhiyun status = "okay"; 250*4882a593Smuzhiyun vref-supply = <&vcc_1v8_s0>; 251*4882a593Smuzhiyun}; 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun&tsadc { 254*4882a593Smuzhiyun status = "okay"; 255*4882a593Smuzhiyun}; 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun&u2phy0 { 258*4882a593Smuzhiyun status = "okay"; 259*4882a593Smuzhiyun}; 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun&u2phy1 { 262*4882a593Smuzhiyun status = "okay"; 263*4882a593Smuzhiyun}; 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun&u2phy2 { 266*4882a593Smuzhiyun status = "okay"; 267*4882a593Smuzhiyun}; 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun&u2phy3 { 270*4882a593Smuzhiyun status = "okay"; 271*4882a593Smuzhiyun}; 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun&usb_host0_ehci { 275*4882a593Smuzhiyun status = "okay"; 276*4882a593Smuzhiyun}; 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun&usb_host0_ohci { 279*4882a593Smuzhiyun status = "okay"; 280*4882a593Smuzhiyun}; 281*4882a593Smuzhiyun 282*4882a593Smuzhiyun&usb_host1_ehci { 283*4882a593Smuzhiyun status = "okay"; 284*4882a593Smuzhiyun}; 285*4882a593Smuzhiyun 286*4882a593Smuzhiyun&usb_host1_ohci { 287*4882a593Smuzhiyun status = "okay"; 288*4882a593Smuzhiyun}; 289*4882a593Smuzhiyun 290*4882a593Smuzhiyun&usbdp_phy0 { 291*4882a593Smuzhiyun status = "okay"; 292*4882a593Smuzhiyun}; 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun&usbdp_phy0_dp { 295*4882a593Smuzhiyun status = "okay"; 296*4882a593Smuzhiyun}; 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun&usbdp_phy0_u3 { 299*4882a593Smuzhiyun status = "okay"; 300*4882a593Smuzhiyun}; 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun&usbdp_phy1_dp { 303*4882a593Smuzhiyun status = "okay"; 304*4882a593Smuzhiyun}; 305*4882a593Smuzhiyun 306*4882a593Smuzhiyun&usbdp_phy1_u3 { 307*4882a593Smuzhiyun status = "okay"; 308*4882a593Smuzhiyun}; 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun&usbdrd3_0 { 311*4882a593Smuzhiyun status = "okay"; 312*4882a593Smuzhiyun}; 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun&usbdrd_dwc3_0 { 315*4882a593Smuzhiyun dr_mode = "otg"; 316*4882a593Smuzhiyun status = "okay"; 317*4882a593Smuzhiyun}; 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun&usbhost3_0 { 320*4882a593Smuzhiyun status = "okay"; 321*4882a593Smuzhiyun}; 322*4882a593Smuzhiyun 323*4882a593Smuzhiyun&usbhost_dwc3_0 { 324*4882a593Smuzhiyun status = "okay"; 325*4882a593Smuzhiyun}; 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun&vdpu { 328*4882a593Smuzhiyun status = "okay"; 329*4882a593Smuzhiyun}; 330*4882a593Smuzhiyun 331*4882a593Smuzhiyun&vdpu_mmu { 332*4882a593Smuzhiyun status = "okay"; 333*4882a593Smuzhiyun}; 334*4882a593Smuzhiyun 335*4882a593Smuzhiyun&vepu { 336*4882a593Smuzhiyun status = "okay"; 337*4882a593Smuzhiyun}; 338*4882a593Smuzhiyun 339*4882a593Smuzhiyun&vop { 340*4882a593Smuzhiyun disable-win-move; 341*4882a593Smuzhiyun assigned-clocks = <&cru DCLK_VOP0_SRC>, 342*4882a593Smuzhiyun <&cru DCLK_VOP1_SRC>, 343*4882a593Smuzhiyun <&cru DCLK_VOP2_SRC>, 344*4882a593Smuzhiyun <&cru DCLK_VOP3>; 345*4882a593Smuzhiyun assigned-clock-parents = <0>, <0>, <&cru PLL_V0PLL>, <0>; 346*4882a593Smuzhiyun status = "okay"; 347*4882a593Smuzhiyun}; 348*4882a593Smuzhiyun 349*4882a593Smuzhiyun&vop_mmu { 350*4882a593Smuzhiyun status = "okay"; 351*4882a593Smuzhiyun}; 352