1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include "rk3588-nvr-demo.dtsi" 10*4882a593Smuzhiyun#include "rk3588-android.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun model = "Rockchip RK3588 NVR DEMO LP4 V10 Android Board"; 14*4882a593Smuzhiyun compatible = "rockchip,rk3588-nvr-demo-v10-android", "rockchip,rk3588"; 15*4882a593Smuzhiyun}; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun&avsd { 18*4882a593Smuzhiyun status = "okay"; 19*4882a593Smuzhiyun}; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun&dp0 { 22*4882a593Smuzhiyun status = "disabled"; 23*4882a593Smuzhiyun}; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun&dp1_in_vp0 { 26*4882a593Smuzhiyun status = "disabled"; 27*4882a593Smuzhiyun}; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun&dp1_in_vp1 { 30*4882a593Smuzhiyun status = "disabled"; 31*4882a593Smuzhiyun}; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun&hdmi0_in_vp1 { 34*4882a593Smuzhiyun status = "disabled"; 35*4882a593Smuzhiyun}; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun&hdmi0_in_vp2 { 38*4882a593Smuzhiyun status = "disabled"; 39*4882a593Smuzhiyun}; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun&hdmi1 { 42*4882a593Smuzhiyun status = "disabled"; 43*4882a593Smuzhiyun}; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun&hdmi1_in_vp0 { 46*4882a593Smuzhiyun status = "disabled"; 47*4882a593Smuzhiyun}; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun&hdmi1_in_vp2 { 50*4882a593Smuzhiyun status = "disabled"; 51*4882a593Smuzhiyun}; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun&hdmi1_sound { 54*4882a593Smuzhiyun status = "disabled"; 55*4882a593Smuzhiyun}; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun&hdptxphy_hdmi1 { 58*4882a593Smuzhiyun status = "disabled"; 59*4882a593Smuzhiyun}; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun&i2s6_8ch { 62*4882a593Smuzhiyun status = "disabled"; 63*4882a593Smuzhiyun}; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun&pcie30phy { 66*4882a593Smuzhiyun status = "disabled"; 67*4882a593Smuzhiyun}; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun&pcie3x4 { 70*4882a593Smuzhiyun status = "disabled"; 71*4882a593Smuzhiyun}; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun&route_dp0 { 74*4882a593Smuzhiyun status = "okay"; 75*4882a593Smuzhiyun connect = <&vp2_out_dp0>; 76*4882a593Smuzhiyun /delete-property/ force-output; 77*4882a593Smuzhiyun /delete-node/ force_timing; 78*4882a593Smuzhiyun}; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun&route_dp1 { 81*4882a593Smuzhiyun status = "disabled"; 82*4882a593Smuzhiyun}; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun&route_hdmi0 { 85*4882a593Smuzhiyun status = "okay"; 86*4882a593Smuzhiyun connect = <&vp0_out_hdmi0>; 87*4882a593Smuzhiyun /delete-property/ force-output; 88*4882a593Smuzhiyun /delete-node/ force_timing; 89*4882a593Smuzhiyun}; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun&route_hdmi1 { 92*4882a593Smuzhiyun status = "disabled"; 93*4882a593Smuzhiyun}; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun&sata0 { 96*4882a593Smuzhiyun status = "disabled"; 97*4882a593Smuzhiyun}; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun&sata1 { 100*4882a593Smuzhiyun status = "disabled"; 101*4882a593Smuzhiyun}; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun&usbdrd_dwc3_0 { 104*4882a593Smuzhiyun dr_mode = "otg"; 105*4882a593Smuzhiyun extcon = <&u2phy0>; 106*4882a593Smuzhiyun status = "okay"; 107*4882a593Smuzhiyun}; 108