xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm64/rockchip/rk3588-evb2-lp4.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun#include "rk3588.dtsi"
8*4882a593Smuzhiyun#include "rk3588-evb.dtsi"
9*4882a593Smuzhiyun#include "rk3588-rk806-dual.dtsi"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun/ {
12*4882a593Smuzhiyun	es7202_sound_micarray: es7202-sound-micarray {
13*4882a593Smuzhiyun		status = "okay";
14*4882a593Smuzhiyun		compatible = "simple-audio-card";
15*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
16*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,sound-micarray";
17*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <256>;
18*4882a593Smuzhiyun		simple-audio-card,dai-link@0 {
19*4882a593Smuzhiyun			format = "pdm";
20*4882a593Smuzhiyun			cpu {
21*4882a593Smuzhiyun				sound-dai = <&pdm0>;
22*4882a593Smuzhiyun			};
23*4882a593Smuzhiyun			codec {
24*4882a593Smuzhiyun				sound-dai = <&es7202>;
25*4882a593Smuzhiyun			};
26*4882a593Smuzhiyun		};
27*4882a593Smuzhiyun	};
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun	es8388_sound: es8388-sound {
30*4882a593Smuzhiyun		status = "okay";
31*4882a593Smuzhiyun		compatible = "rockchip,multicodecs-card";
32*4882a593Smuzhiyun		rockchip,card-name = "rockchip-es8388";
33*4882a593Smuzhiyun		hp-det-gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>;
34*4882a593Smuzhiyun		io-channels = <&saradc 3>;
35*4882a593Smuzhiyun		io-channel-names = "adc-detect";
36*4882a593Smuzhiyun		keyup-threshold-microvolt = <1800000>;
37*4882a593Smuzhiyun		poll-interval = <100>;
38*4882a593Smuzhiyun		spk-con-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>;
39*4882a593Smuzhiyun		hp-con-gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
40*4882a593Smuzhiyun		rockchip,format = "i2s";
41*4882a593Smuzhiyun		rockchip,mclk-fs = <256>;
42*4882a593Smuzhiyun		rockchip,cpu = <&i2s0_8ch>;
43*4882a593Smuzhiyun		rockchip,codec = <&es8388>;
44*4882a593Smuzhiyun		rockchip,audio-routing =
45*4882a593Smuzhiyun			"Headphone", "LOUT1",
46*4882a593Smuzhiyun			"Headphone", "ROUT1",
47*4882a593Smuzhiyun			"Speaker", "LOUT2",
48*4882a593Smuzhiyun			"Speaker", "ROUT2",
49*4882a593Smuzhiyun			"Headphone", "Headphone Power",
50*4882a593Smuzhiyun			"Headphone", "Headphone Power",
51*4882a593Smuzhiyun			"Speaker", "Speaker Power",
52*4882a593Smuzhiyun			"Speaker", "Speaker Power",
53*4882a593Smuzhiyun			"LINPUT1", "Main Mic",
54*4882a593Smuzhiyun			"LINPUT2", "Main Mic",
55*4882a593Smuzhiyun			"RINPUT1", "Headset Mic",
56*4882a593Smuzhiyun			"RINPUT2", "Headset Mic";
57*4882a593Smuzhiyun		pinctrl-names = "default";
58*4882a593Smuzhiyun		pinctrl-0 = <&hp_det>;
59*4882a593Smuzhiyun		play-pause-key {
60*4882a593Smuzhiyun			label = "playpause";
61*4882a593Smuzhiyun			linux,code = <KEY_PLAYPAUSE>;
62*4882a593Smuzhiyun			press-threshold-microvolt = <2000>;
63*4882a593Smuzhiyun		};
64*4882a593Smuzhiyun	};
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun	fan: pwm-fan {
67*4882a593Smuzhiyun		compatible = "pwm-fan";
68*4882a593Smuzhiyun		#cooling-cells = <2>;
69*4882a593Smuzhiyun		pwms = <&pwm9 0 50000 0>;
70*4882a593Smuzhiyun		cooling-levels = <0 50 100 150 200 255>;
71*4882a593Smuzhiyun		rockchip,temp-trips = <
72*4882a593Smuzhiyun			50000	1
73*4882a593Smuzhiyun			55000	2
74*4882a593Smuzhiyun			60000	3
75*4882a593Smuzhiyun			65000	4
76*4882a593Smuzhiyun			70000	5
77*4882a593Smuzhiyun		>;
78*4882a593Smuzhiyun	};
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun	pcie20_avdd0v85: pcie20-avdd0v85 {
81*4882a593Smuzhiyun		compatible = "regulator-fixed";
82*4882a593Smuzhiyun		regulator-name = "pcie20_avdd0v85";
83*4882a593Smuzhiyun		regulator-boot-on;
84*4882a593Smuzhiyun		regulator-always-on;
85*4882a593Smuzhiyun		regulator-min-microvolt = <850000>;
86*4882a593Smuzhiyun		regulator-max-microvolt = <850000>;
87*4882a593Smuzhiyun		vin-supply = <&avdd_0v85_s0>;
88*4882a593Smuzhiyun	};
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun	pcie20_avdd1v8: pcie20-avdd1v8 {
91*4882a593Smuzhiyun		compatible = "regulator-fixed";
92*4882a593Smuzhiyun		regulator-name = "pcie20_avdd1v8";
93*4882a593Smuzhiyun		regulator-boot-on;
94*4882a593Smuzhiyun		regulator-always-on;
95*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
96*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
97*4882a593Smuzhiyun		vin-supply = <&avcc_1v8_s0>;
98*4882a593Smuzhiyun	};
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun	pcie30_avdd0v75: pcie30-avdd0v75 {
101*4882a593Smuzhiyun		compatible = "regulator-fixed";
102*4882a593Smuzhiyun		regulator-name = "pcie30_avdd0v75";
103*4882a593Smuzhiyun		regulator-boot-on;
104*4882a593Smuzhiyun		regulator-always-on;
105*4882a593Smuzhiyun		regulator-min-microvolt = <750000>;
106*4882a593Smuzhiyun		regulator-max-microvolt = <750000>;
107*4882a593Smuzhiyun		vin-supply = <&avdd_0v75_s0>;
108*4882a593Smuzhiyun	};
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun	pcie30_avdd1v8: pcie30-avdd1v8 {
111*4882a593Smuzhiyun		compatible = "regulator-fixed";
112*4882a593Smuzhiyun		regulator-name = "pcie30_avdd1v8";
113*4882a593Smuzhiyun		regulator-boot-on;
114*4882a593Smuzhiyun		regulator-always-on;
115*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
116*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
117*4882a593Smuzhiyun		vin-supply = <&avcc_1v8_s0>;
118*4882a593Smuzhiyun	};
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun	sdio_pwrseq: sdio-pwrseq {
121*4882a593Smuzhiyun		compatible = "mmc-pwrseq-simple";
122*4882a593Smuzhiyun		clocks = <&hym8563>;
123*4882a593Smuzhiyun		clock-names = "ext_clock";
124*4882a593Smuzhiyun		pinctrl-names = "default";
125*4882a593Smuzhiyun		pinctrl-0 = <&wifi_enable_h>;
126*4882a593Smuzhiyun		/*
127*4882a593Smuzhiyun		 * On the module itself this is one of these (depending
128*4882a593Smuzhiyun		 * on the actual card populated):
129*4882a593Smuzhiyun		 * - SDIO_RESET_L_WL_REG_ON
130*4882a593Smuzhiyun		 * - PDN (power down when low)
131*4882a593Smuzhiyun		 */
132*4882a593Smuzhiyun		post-power-on-delay-ms = <200>;
133*4882a593Smuzhiyun		reset-gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_LOW>;
134*4882a593Smuzhiyun	};
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun	vcc3v3_lcd_n: vcc3v3-lcd0-n {
137*4882a593Smuzhiyun		compatible = "regulator-fixed";
138*4882a593Smuzhiyun		regulator-name = "vcc3v3_lcd0_n";
139*4882a593Smuzhiyun		regulator-boot-on;
140*4882a593Smuzhiyun		enable-active-high;
141*4882a593Smuzhiyun		gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
142*4882a593Smuzhiyun		vin-supply = <&vcc_1v8_s0>;
143*4882a593Smuzhiyun	};
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun	vcc3v3_pcie30: vcc3v3-pcie30 {
146*4882a593Smuzhiyun		compatible = "regulator-fixed";
147*4882a593Smuzhiyun		regulator-name = "vcc3v3_pcie30";
148*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
149*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
150*4882a593Smuzhiyun		enable-active-high;
151*4882a593Smuzhiyun		gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
152*4882a593Smuzhiyun		startup-delay-us = <5000>;
153*4882a593Smuzhiyun		vin-supply = <&vcc12v_dcin>;
154*4882a593Smuzhiyun	};
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun	vcc5v0_host: vcc5v0-host {
157*4882a593Smuzhiyun		compatible = "regulator-fixed";
158*4882a593Smuzhiyun		regulator-name = "vcc5v0_host";
159*4882a593Smuzhiyun		regulator-boot-on;
160*4882a593Smuzhiyun		regulator-always-on;
161*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
162*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
163*4882a593Smuzhiyun		enable-active-high;
164*4882a593Smuzhiyun		gpio = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>;
165*4882a593Smuzhiyun		vin-supply = <&vcc5v0_usb>;
166*4882a593Smuzhiyun		pinctrl-names = "default";
167*4882a593Smuzhiyun		pinctrl-0 = <&vcc5v0_host_en>;
168*4882a593Smuzhiyun	};
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun	wireless_bluetooth: wireless-bluetooth {
171*4882a593Smuzhiyun		compatible = "bluetooth-platdata";
172*4882a593Smuzhiyun		clocks = <&hym8563>;
173*4882a593Smuzhiyun		clock-names = "ext_clock";
174*4882a593Smuzhiyun		uart_rts_gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>;
175*4882a593Smuzhiyun		pinctrl-names = "default", "rts_gpio";
176*4882a593Smuzhiyun		pinctrl-0 = <&uart9m0_rtsn>, <&bt_gpio>;
177*4882a593Smuzhiyun		pinctrl-1 = <&uart9_gpios>;
178*4882a593Smuzhiyun		BT,reset_gpio    = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
179*4882a593Smuzhiyun		BT,wake_gpio     = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
180*4882a593Smuzhiyun		BT,wake_host_irq = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
181*4882a593Smuzhiyun		status = "okay";
182*4882a593Smuzhiyun	};
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun	wireless_wlan: wireless-wlan {
185*4882a593Smuzhiyun		compatible = "wlan-platdata";
186*4882a593Smuzhiyun		wifi_chip_type = "ap6398s";
187*4882a593Smuzhiyun		pinctrl-names = "default";
188*4882a593Smuzhiyun		pinctrl-0 = <&wifi_host_wake_irq>;
189*4882a593Smuzhiyun		WIFI,host_wake_irq = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
190*4882a593Smuzhiyun		WIFI,poweren_gpio = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>;
191*4882a593Smuzhiyun		status = "okay";
192*4882a593Smuzhiyun	};
193*4882a593Smuzhiyun};
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun&backlight {
196*4882a593Smuzhiyun	pwms = <&pwm3 0 25000 0>;
197*4882a593Smuzhiyun	status = "okay";
198*4882a593Smuzhiyun};
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun&combphy0_ps {
201*4882a593Smuzhiyun	status = "okay";
202*4882a593Smuzhiyun};
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun&combphy1_ps {
205*4882a593Smuzhiyun	status = "okay";
206*4882a593Smuzhiyun};
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun&combphy2_psu {
209*4882a593Smuzhiyun	status = "okay";
210*4882a593Smuzhiyun};
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun&dp0 {
213*4882a593Smuzhiyun	pinctrl-0 = <&dp0m2_pins>;
214*4882a593Smuzhiyun	pinctrl-names = "default";
215*4882a593Smuzhiyun	status = "okay";
216*4882a593Smuzhiyun};
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun&dp0_in_vp2 {
219*4882a593Smuzhiyun	status = "okay";
220*4882a593Smuzhiyun};
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun&dp0_sound {
223*4882a593Smuzhiyun	status = "okay";
224*4882a593Smuzhiyun};
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun&dp1 {
227*4882a593Smuzhiyun	pinctrl-0 = <&dp1m2_pins>;
228*4882a593Smuzhiyun	pinctrl-names = "default";
229*4882a593Smuzhiyun	status = "okay";
230*4882a593Smuzhiyun};
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun&dp1_in_vp2 {
233*4882a593Smuzhiyun	status = "okay";
234*4882a593Smuzhiyun};
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun/*
237*4882a593Smuzhiyun * mipi_dcphy1 needs to be enabled
238*4882a593Smuzhiyun * when dsi1 is enabled
239*4882a593Smuzhiyun */
240*4882a593Smuzhiyun&dsi1 {
241*4882a593Smuzhiyun	status = "okay";
242*4882a593Smuzhiyun};
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun&dsi1_in_vp2 {
245*4882a593Smuzhiyun	status = "disabled";
246*4882a593Smuzhiyun};
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun&dsi1_in_vp3 {
249*4882a593Smuzhiyun	status = "okay";
250*4882a593Smuzhiyun};
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun&dsi1_panel {
253*4882a593Smuzhiyun	power-supply = <&vcc3v3_lcd_n>;
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun	reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>;
256*4882a593Smuzhiyun	pinctrl-names = "default";
257*4882a593Smuzhiyun	pinctrl-0 = <&lcd_rst_gpio>;
258*4882a593Smuzhiyun};
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun&gmac1 {
261*4882a593Smuzhiyun	/* Use rgmii-rxid mode to disable rx delay inside Soc */
262*4882a593Smuzhiyun	phy-mode = "rgmii-rxid";
263*4882a593Smuzhiyun	clock_in_out = "output";
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun	snps,reset-gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>;
266*4882a593Smuzhiyun	snps,reset-active-low;
267*4882a593Smuzhiyun	/* Reset time is 20ms, 100ms for rtl8211f */
268*4882a593Smuzhiyun	snps,reset-delays-us = <0 20000 100000>;
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun	pinctrl-names = "default";
271*4882a593Smuzhiyun	pinctrl-0 = <&gmac1_miim
272*4882a593Smuzhiyun		     &gmac1_tx_bus2
273*4882a593Smuzhiyun		     &gmac1_rx_bus2
274*4882a593Smuzhiyun		     &gmac1_rgmii_clk
275*4882a593Smuzhiyun		     &gmac1_rgmii_bus>;
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun	tx_delay = <0x45>;
278*4882a593Smuzhiyun	/* rx_delay = <0x3f>; */
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun	phy-handle = <&rgmii_phy>;
281*4882a593Smuzhiyun	status = "okay";
282*4882a593Smuzhiyun};
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun&hdmi0 {
285*4882a593Smuzhiyun	enable-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
286*4882a593Smuzhiyun	status = "okay";
287*4882a593Smuzhiyun};
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun&hdmi0_in_vp0 {
290*4882a593Smuzhiyun	status = "okay";
291*4882a593Smuzhiyun};
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun&hdmi0_sound {
294*4882a593Smuzhiyun	status = "okay";
295*4882a593Smuzhiyun};
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun&hdptxphy_hdmi0 {
298*4882a593Smuzhiyun	status = "okay";
299*4882a593Smuzhiyun};
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun&i2c2 {
302*4882a593Smuzhiyun	status = "okay";
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun	hym8563: hym8563@51 {
305*4882a593Smuzhiyun		compatible = "haoyu,hym8563";
306*4882a593Smuzhiyun		reg = <0x51>;
307*4882a593Smuzhiyun		#clock-cells = <0>;
308*4882a593Smuzhiyun		clock-frequency = <32768>;
309*4882a593Smuzhiyun		clock-output-names = "hym8563";
310*4882a593Smuzhiyun		pinctrl-names = "default";
311*4882a593Smuzhiyun		pinctrl-0 = <&hym8563_int>;
312*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
313*4882a593Smuzhiyun		interrupts = <RK_PC4 IRQ_TYPE_LEVEL_LOW>;
314*4882a593Smuzhiyun		wakeup-source;
315*4882a593Smuzhiyun	};
316*4882a593Smuzhiyun};
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun&i2c6 {
319*4882a593Smuzhiyun	status = "okay";
320*4882a593Smuzhiyun	gt1x: gt1x@14 {
321*4882a593Smuzhiyun		compatible = "goodix,gt1x";
322*4882a593Smuzhiyun		reg = <0x14>;
323*4882a593Smuzhiyun		pinctrl-names = "default";
324*4882a593Smuzhiyun		pinctrl-0 = <&touch_gpio>;
325*4882a593Smuzhiyun		goodix,rst-gpio = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>;
326*4882a593Smuzhiyun		goodix,irq-gpio = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_LOW>;
327*4882a593Smuzhiyun		power-supply = <&vcc3v3_lcd_n>;
328*4882a593Smuzhiyun	};
329*4882a593Smuzhiyun};
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun&i2c7 {
332*4882a593Smuzhiyun	status = "okay";
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun	es8388: es8388@11 {
335*4882a593Smuzhiyun		status = "okay";
336*4882a593Smuzhiyun		#sound-dai-cells = <0>;
337*4882a593Smuzhiyun		compatible = "everest,es8388", "everest,es8323";
338*4882a593Smuzhiyun		reg = <0x11>;
339*4882a593Smuzhiyun		clocks = <&mclkout_i2s0>;
340*4882a593Smuzhiyun		clock-names = "mclk";
341*4882a593Smuzhiyun		assigned-clocks = <&mclkout_i2s0>;
342*4882a593Smuzhiyun		assigned-clock-rates = <12288000>;
343*4882a593Smuzhiyun		pinctrl-names = "default";
344*4882a593Smuzhiyun		pinctrl-0 = <&i2s0_mclk>;
345*4882a593Smuzhiyun	};
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun	es7202: es7202@32 {
348*4882a593Smuzhiyun		status = "okay";
349*4882a593Smuzhiyun		#sound-dai-cells = <0>;
350*4882a593Smuzhiyun		compatible = "ES7202_PDM_ADC_1";
351*4882a593Smuzhiyun		power-supply = <&vcc_1v8_s0>;	/* only 1v8 or 3v3, default is 3v3 */
352*4882a593Smuzhiyun		reg = <0x32>;
353*4882a593Smuzhiyun	};
354*4882a593Smuzhiyun};
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun&i2s2_2ch {
357*4882a593Smuzhiyun	pinctrl-0 = <&i2s2m0_sclk &i2s2m0_lrck &i2s2m0_sdi &i2s2m0_sdo>;
358*4882a593Smuzhiyun	status = "disabled";
359*4882a593Smuzhiyun};
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun&i2s5_8ch {
362*4882a593Smuzhiyun	status = "okay";
363*4882a593Smuzhiyun};
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun&mdio1 {
366*4882a593Smuzhiyun	rgmii_phy: phy@1 {
367*4882a593Smuzhiyun		compatible = "ethernet-phy-ieee802.3-c22";
368*4882a593Smuzhiyun		reg = <0x1>;
369*4882a593Smuzhiyun	};
370*4882a593Smuzhiyun};
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun&mipi_dcphy1 {
373*4882a593Smuzhiyun	status = "okay";
374*4882a593Smuzhiyun};
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun&pcie2x1l0 {
377*4882a593Smuzhiyun	reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
378*4882a593Smuzhiyun	status = "okay";
379*4882a593Smuzhiyun};
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun&pcie30phy {
382*4882a593Smuzhiyun	status = "okay";
383*4882a593Smuzhiyun};
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun&pcie3x4 {
386*4882a593Smuzhiyun	reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
387*4882a593Smuzhiyun	vpcie3v3-supply = <&vcc3v3_pcie30>;
388*4882a593Smuzhiyun	pinctrl-names = "default";
389*4882a593Smuzhiyun	pinctrl-0 = <&pcie30x4_clkreqn_m1>;
390*4882a593Smuzhiyun	status = "okay";
391*4882a593Smuzhiyun};
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun&pdm0 {
394*4882a593Smuzhiyun	status = "okay";
395*4882a593Smuzhiyun	pinctrl-names = "default";
396*4882a593Smuzhiyun	pinctrl-0 = <&pdm0m0_clk
397*4882a593Smuzhiyun		     &pdm0m0_sdi0>;
398*4882a593Smuzhiyun};
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun&pinctrl {
401*4882a593Smuzhiyun	headphone {
402*4882a593Smuzhiyun		hp_det: hp-det {
403*4882a593Smuzhiyun			rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
404*4882a593Smuzhiyun		};
405*4882a593Smuzhiyun	};
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun	hym8563 {
408*4882a593Smuzhiyun		hym8563_int: hym8563-int {
409*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
410*4882a593Smuzhiyun		};
411*4882a593Smuzhiyun	};
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun	lcd {
414*4882a593Smuzhiyun		lcd_rst_gpio: lcd-rst-gpio {
415*4882a593Smuzhiyun			rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
416*4882a593Smuzhiyun		};
417*4882a593Smuzhiyun	};
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun	pcie30x4 {
420*4882a593Smuzhiyun		pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 {
421*4882a593Smuzhiyun			rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
422*4882a593Smuzhiyun		};
423*4882a593Smuzhiyun	};
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun	sdio-pwrseq {
426*4882a593Smuzhiyun		wifi_enable_h: wifi-enable-h {
427*4882a593Smuzhiyun		       rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
428*4882a593Smuzhiyun	       };
429*4882a593Smuzhiyun	};
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun	touch {
432*4882a593Smuzhiyun		touch_gpio: touch-gpio {
433*4882a593Smuzhiyun			rockchip,pins =
434*4882a593Smuzhiyun				<0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>,
435*4882a593Smuzhiyun				<0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
436*4882a593Smuzhiyun		};
437*4882a593Smuzhiyun	};
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun	usb {
440*4882a593Smuzhiyun		vcc5v0_host_en: vcc5v0-host-en {
441*4882a593Smuzhiyun			rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
442*4882a593Smuzhiyun		};
443*4882a593Smuzhiyun	};
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun	wireless-bluetooth {
446*4882a593Smuzhiyun		uart9_gpios: uart9-gpios {
447*4882a593Smuzhiyun			rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
448*4882a593Smuzhiyun		};
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun		bt_gpio: bt-gpio {
451*4882a593Smuzhiyun			rockchip,pins =
452*4882a593Smuzhiyun				<2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>,
453*4882a593Smuzhiyun				<4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>,
454*4882a593Smuzhiyun				<4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
455*4882a593Smuzhiyun		};
456*4882a593Smuzhiyun	};
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun	wireless-wlan {
459*4882a593Smuzhiyun		wifi_host_wake_irq: wifi-host-wake-irq {
460*4882a593Smuzhiyun			rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
461*4882a593Smuzhiyun		};
462*4882a593Smuzhiyun	};
463*4882a593Smuzhiyun};
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun&pwm3 {
466*4882a593Smuzhiyun	status = "okay";
467*4882a593Smuzhiyun	pinctrl-0 = <&pwm3m1_pins>;
468*4882a593Smuzhiyun};
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun&pwm9 {
471*4882a593Smuzhiyun	pinctrl-0 = <&pwm9m2_pins>;
472*4882a593Smuzhiyun	status = "okay";
473*4882a593Smuzhiyun};
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun&route_dsi1 {
476*4882a593Smuzhiyun	status = "okay";
477*4882a593Smuzhiyun	connect = <&vp3_out_dsi1>;
478*4882a593Smuzhiyun};
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun&sata0 {
481*4882a593Smuzhiyun	status = "okay";
482*4882a593Smuzhiyun};
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun&sdio {
485*4882a593Smuzhiyun	max-frequency = <150000000>;
486*4882a593Smuzhiyun	no-sd;
487*4882a593Smuzhiyun	no-mmc;
488*4882a593Smuzhiyun	bus-width = <4>;
489*4882a593Smuzhiyun	disable-wp;
490*4882a593Smuzhiyun	cap-sd-highspeed;
491*4882a593Smuzhiyun	cap-sdio-irq;
492*4882a593Smuzhiyun	keep-power-in-suspend;
493*4882a593Smuzhiyun	mmc-pwrseq = <&sdio_pwrseq>;
494*4882a593Smuzhiyun	non-removable;
495*4882a593Smuzhiyun	pinctrl-names = "default";
496*4882a593Smuzhiyun	pinctrl-0 = <&sdiom0_pins>;
497*4882a593Smuzhiyun	sd-uhs-sdr104;
498*4882a593Smuzhiyun	status = "okay";
499*4882a593Smuzhiyun};
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun&sdmmc {
502*4882a593Smuzhiyun	status = "okay";
503*4882a593Smuzhiyun	vmmc-supply = <&vcc_3v3_sd_s0>;
504*4882a593Smuzhiyun};
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun&spdif_tx2 {
507*4882a593Smuzhiyun	status = "okay";
508*4882a593Smuzhiyun};
509*4882a593Smuzhiyun
510*4882a593Smuzhiyun&u2phy0_otg {
511*4882a593Smuzhiyun	phy-supply = <&vcc5v0_host>;
512*4882a593Smuzhiyun};
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun&u2phy1_otg {
515*4882a593Smuzhiyun	phy-supply = <&vcc5v0_host>;
516*4882a593Smuzhiyun};
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun&u2phy2_host {
519*4882a593Smuzhiyun	phy-supply = <&vcc5v0_host>;
520*4882a593Smuzhiyun};
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun&u2phy3_host {
523*4882a593Smuzhiyun	phy-supply = <&vcc5v0_host>;
524*4882a593Smuzhiyun};
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun&usbdp_phy0 {
527*4882a593Smuzhiyun	rockchip,dp-lane-mux = <2 3>;
528*4882a593Smuzhiyun};
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun&usbdp_phy1 {
531*4882a593Smuzhiyun	rockchip,dp-lane-mux = <2 3>;
532*4882a593Smuzhiyun};
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun&usbdrd_dwc3_0 {
535*4882a593Smuzhiyun	dr_mode = "otg";
536*4882a593Smuzhiyun	extcon = <&u2phy0>;
537*4882a593Smuzhiyun	status = "okay";
538*4882a593Smuzhiyun};
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun&uart9 {
541*4882a593Smuzhiyun	status = "okay";
542*4882a593Smuzhiyun	pinctrl-names = "default";
543*4882a593Smuzhiyun	pinctrl-0 = <&uart9m0_xfer &uart9m0_ctsn>;
544*4882a593Smuzhiyun};
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun&vcc3v3_lcd_n {
547*4882a593Smuzhiyun	gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
548*4882a593Smuzhiyun	enable-active-high;
549*4882a593Smuzhiyun};
550