1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun// Copyright (c) 2021 Rockchip Electronics Co., Ltd. 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun/dts-v1/; 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include "rk3588-evb2-lp4.dtsi" 7*4882a593Smuzhiyun#include "rk3588-android.dtsi" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun model = "Rockchip RK3588 EVB2 LP4 V10 eDP Board"; 11*4882a593Smuzhiyun compatible = "rockchip,rk3588-evb2-lp4-v10-edp", "rockchip,rk3588"; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun panel-edp1 { 14*4882a593Smuzhiyun compatible = "simple-panel"; 15*4882a593Smuzhiyun backlight = <&backlight>; 16*4882a593Smuzhiyun power-supply = <&vcc3v3_lcd>; 17*4882a593Smuzhiyun prepare-delay-ms = <120>; 18*4882a593Smuzhiyun enable-delay-ms = <120>; 19*4882a593Smuzhiyun unprepare-delay-ms = <120>; 20*4882a593Smuzhiyun disable-delay-ms = <120>; 21*4882a593Smuzhiyun width-mm = <129>; 22*4882a593Smuzhiyun height-mm = <171>; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun panel-timing { 25*4882a593Smuzhiyun clock-frequency = <200000000>; 26*4882a593Smuzhiyun hactive = <1536>; 27*4882a593Smuzhiyun vactive = <2048>; 28*4882a593Smuzhiyun hfront-porch = <12>; 29*4882a593Smuzhiyun hsync-len = <16>; 30*4882a593Smuzhiyun hback-porch = <48>; 31*4882a593Smuzhiyun vfront-porch = <8>; 32*4882a593Smuzhiyun vsync-len = <4>; 33*4882a593Smuzhiyun vback-porch = <8>; 34*4882a593Smuzhiyun hsync-active = <0>; 35*4882a593Smuzhiyun vsync-active = <0>; 36*4882a593Smuzhiyun de-active = <0>; 37*4882a593Smuzhiyun pixelclk-active = <0>; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun port { 41*4882a593Smuzhiyun panel_in_edp1: endpoint { 42*4882a593Smuzhiyun remote-endpoint = <&edp1_out_panel>; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun vcc3v3_lcd: vcc3v3-lcd { 48*4882a593Smuzhiyun compatible = "regulator-fixed"; 49*4882a593Smuzhiyun regulator-name = "vcc3v3_lcd"; 50*4882a593Smuzhiyun vin-supply = <&vcc_3v3_s0>; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun}; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun&backlight { 55*4882a593Smuzhiyun enable-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; 56*4882a593Smuzhiyun}; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun&dp0_in_vp0 { 59*4882a593Smuzhiyun status = "disabled"; 60*4882a593Smuzhiyun}; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun&dp0_in_vp1 { 63*4882a593Smuzhiyun status = "okay"; 64*4882a593Smuzhiyun}; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun&dp0_in_vp2 { 67*4882a593Smuzhiyun status = "disabled"; 68*4882a593Smuzhiyun}; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun&dp1_in_vp0 { 71*4882a593Smuzhiyun status = "disabled"; 72*4882a593Smuzhiyun}; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun&dp1_in_vp1 { 75*4882a593Smuzhiyun status = "okay"; 76*4882a593Smuzhiyun}; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun&dp1_in_vp2 { 79*4882a593Smuzhiyun status = "disabled"; 80*4882a593Smuzhiyun}; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun&dsi1 { 83*4882a593Smuzhiyun status = "disabled"; 84*4882a593Smuzhiyun}; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun&edp1 { 87*4882a593Smuzhiyun force-hpd; 88*4882a593Smuzhiyun status = "okay"; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun ports { 91*4882a593Smuzhiyun port@1 { 92*4882a593Smuzhiyun reg = <1>; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun edp1_out_panel: endpoint { 95*4882a593Smuzhiyun remote-endpoint = <&panel_in_edp1>; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun}; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun&edp1_in_vp0 { 102*4882a593Smuzhiyun status = "disabled"; 103*4882a593Smuzhiyun}; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun&edp1_in_vp1 { 106*4882a593Smuzhiyun status = "disabled"; 107*4882a593Smuzhiyun}; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun&edp1_in_vp2 { 110*4882a593Smuzhiyun status = "okay"; 111*4882a593Smuzhiyun}; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun>1x { 114*4882a593Smuzhiyun status = "disabled"; 115*4882a593Smuzhiyun}; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun&hdptxphy1 { 118*4882a593Smuzhiyun status = "okay"; 119*4882a593Smuzhiyun}; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun&i2c6 { 122*4882a593Smuzhiyun clock-frequency = <400000>; 123*4882a593Smuzhiyun status = "okay"; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun gsl3673@40 { 126*4882a593Smuzhiyun compatible = "GSL,GSL3673"; 127*4882a593Smuzhiyun reg = <0x40>; 128*4882a593Smuzhiyun screen_max_x = <1536>; 129*4882a593Smuzhiyun screen_max_y = <2048>; 130*4882a593Smuzhiyun irq_gpio_number = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_LOW>; 131*4882a593Smuzhiyun rst_gpio_number = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun}; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun&vcc3v3_lcd_n { 136*4882a593Smuzhiyun /delete-property/ gpio; 137*4882a593Smuzhiyun}; 138