xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm64/rockchip/rk3588-evb1-lp4.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun#include "dt-bindings/usb/pd.h"
8*4882a593Smuzhiyun#include "rk3588.dtsi"
9*4882a593Smuzhiyun#include "rk3588-evb.dtsi"
10*4882a593Smuzhiyun#include "rk3588-rk806-dual.dtsi"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun/ {
13*4882a593Smuzhiyun	/* If hdmirx node is disabled, delete the reserved-memory node here. */
14*4882a593Smuzhiyun	reserved-memory {
15*4882a593Smuzhiyun		#address-cells = <2>;
16*4882a593Smuzhiyun		#size-cells = <2>;
17*4882a593Smuzhiyun		ranges;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun		/* Reserve 128MB memory for hdmirx-controller@fdee0000 */
20*4882a593Smuzhiyun		cma {
21*4882a593Smuzhiyun			compatible = "shared-dma-pool";
22*4882a593Smuzhiyun			reusable;
23*4882a593Smuzhiyun			reg = <0x0 (256 * 0x100000) 0x0 (128 * 0x100000)>;
24*4882a593Smuzhiyun			linux,cma-default;
25*4882a593Smuzhiyun		};
26*4882a593Smuzhiyun	};
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun	es8388_sound: es8388-sound {
29*4882a593Smuzhiyun		status = "okay";
30*4882a593Smuzhiyun		compatible = "rockchip,multicodecs-card";
31*4882a593Smuzhiyun		rockchip,card-name = "rockchip-es8388";
32*4882a593Smuzhiyun		hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
33*4882a593Smuzhiyun		io-channels = <&saradc 3>;
34*4882a593Smuzhiyun		io-channel-names = "adc-detect";
35*4882a593Smuzhiyun		keyup-threshold-microvolt = <1800000>;
36*4882a593Smuzhiyun		poll-interval = <100>;
37*4882a593Smuzhiyun		spk-con-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>;
38*4882a593Smuzhiyun		hp-con-gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
39*4882a593Smuzhiyun		rockchip,format = "i2s";
40*4882a593Smuzhiyun		rockchip,mclk-fs = <256>;
41*4882a593Smuzhiyun		rockchip,cpu = <&i2s0_8ch>;
42*4882a593Smuzhiyun		rockchip,codec = <&es8388>;
43*4882a593Smuzhiyun		rockchip,audio-routing =
44*4882a593Smuzhiyun			"Headphone", "LOUT1",
45*4882a593Smuzhiyun			"Headphone", "ROUT1",
46*4882a593Smuzhiyun			"Speaker", "LOUT2",
47*4882a593Smuzhiyun			"Speaker", "ROUT2",
48*4882a593Smuzhiyun			"Headphone", "Headphone Power",
49*4882a593Smuzhiyun			"Headphone", "Headphone Power",
50*4882a593Smuzhiyun			"Speaker", "Speaker Power",
51*4882a593Smuzhiyun			"Speaker", "Speaker Power",
52*4882a593Smuzhiyun			"LINPUT1", "Main Mic",
53*4882a593Smuzhiyun			"LINPUT2", "Main Mic",
54*4882a593Smuzhiyun			"RINPUT1", "Headset Mic",
55*4882a593Smuzhiyun			"RINPUT2", "Headset Mic";
56*4882a593Smuzhiyun		pinctrl-names = "default";
57*4882a593Smuzhiyun		pinctrl-0 = <&hp_det>;
58*4882a593Smuzhiyun		play-pause-key {
59*4882a593Smuzhiyun			label = "playpause";
60*4882a593Smuzhiyun			linux,code = <KEY_PLAYPAUSE>;
61*4882a593Smuzhiyun			press-threshold-microvolt = <2000>;
62*4882a593Smuzhiyun		};
63*4882a593Smuzhiyun	};
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun	fan: pwm-fan {
66*4882a593Smuzhiyun		compatible = "pwm-fan";
67*4882a593Smuzhiyun		#cooling-cells = <2>;
68*4882a593Smuzhiyun		pwms = <&pwm9 0 50000 0>;
69*4882a593Smuzhiyun		cooling-levels = <0 50 100 150 200 255>;
70*4882a593Smuzhiyun		rockchip,temp-trips = <
71*4882a593Smuzhiyun			50000	1
72*4882a593Smuzhiyun			55000	2
73*4882a593Smuzhiyun			60000	3
74*4882a593Smuzhiyun			65000	4
75*4882a593Smuzhiyun			70000	5
76*4882a593Smuzhiyun		>;
77*4882a593Smuzhiyun	};
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun	hdmiin-sound {
80*4882a593Smuzhiyun		compatible = "rockchip,hdmi";
81*4882a593Smuzhiyun		rockchip,mclk-fs = <128>;
82*4882a593Smuzhiyun		rockchip,format = "i2s";
83*4882a593Smuzhiyun		rockchip,bitclock-master = <&hdmirx_ctrler>;
84*4882a593Smuzhiyun		rockchip,frame-master = <&hdmirx_ctrler>;
85*4882a593Smuzhiyun		rockchip,card-name = "rockchip,hdmiin";
86*4882a593Smuzhiyun		rockchip,cpu = <&i2s7_8ch>;
87*4882a593Smuzhiyun		rockchip,codec = <&hdmirx_ctrler 0>;
88*4882a593Smuzhiyun		rockchip,jack-det;
89*4882a593Smuzhiyun	};
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun	pcie20_avdd0v85: pcie20-avdd0v85 {
92*4882a593Smuzhiyun		compatible = "regulator-fixed";
93*4882a593Smuzhiyun		regulator-name = "pcie20_avdd0v85";
94*4882a593Smuzhiyun		regulator-boot-on;
95*4882a593Smuzhiyun		regulator-always-on;
96*4882a593Smuzhiyun		regulator-min-microvolt = <850000>;
97*4882a593Smuzhiyun		regulator-max-microvolt = <850000>;
98*4882a593Smuzhiyun		vin-supply = <&avdd_0v85_s0>;
99*4882a593Smuzhiyun	};
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun	pcie20_avdd1v8: pcie20-avdd1v8 {
102*4882a593Smuzhiyun		compatible = "regulator-fixed";
103*4882a593Smuzhiyun		regulator-name = "pcie20_avdd1v8";
104*4882a593Smuzhiyun		regulator-boot-on;
105*4882a593Smuzhiyun		regulator-always-on;
106*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
107*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
108*4882a593Smuzhiyun		vin-supply = <&avcc_1v8_s0>;
109*4882a593Smuzhiyun	};
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun	pcie30_avdd0v75: pcie30-avdd0v75 {
112*4882a593Smuzhiyun		compatible = "regulator-fixed";
113*4882a593Smuzhiyun		regulator-name = "pcie30_avdd0v75";
114*4882a593Smuzhiyun		regulator-boot-on;
115*4882a593Smuzhiyun		regulator-always-on;
116*4882a593Smuzhiyun		regulator-min-microvolt = <750000>;
117*4882a593Smuzhiyun		regulator-max-microvolt = <750000>;
118*4882a593Smuzhiyun		vin-supply = <&avdd_0v75_s0>;
119*4882a593Smuzhiyun	};
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun	pcie30_avdd1v8: pcie30-avdd1v8 {
122*4882a593Smuzhiyun		compatible = "regulator-fixed";
123*4882a593Smuzhiyun		regulator-name = "pcie30_avdd1v8";
124*4882a593Smuzhiyun		regulator-boot-on;
125*4882a593Smuzhiyun		regulator-always-on;
126*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
127*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
128*4882a593Smuzhiyun		vin-supply = <&avcc_1v8_s0>;
129*4882a593Smuzhiyun	};
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun	rk_headset: rk-headset {
132*4882a593Smuzhiyun		status = "disabled";
133*4882a593Smuzhiyun		compatible = "rockchip_headset";
134*4882a593Smuzhiyun		headset_gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>;
135*4882a593Smuzhiyun		pinctrl-names = "default";
136*4882a593Smuzhiyun		pinctrl-0 = <&hp_det>;
137*4882a593Smuzhiyun		io-channels = <&saradc 3>;
138*4882a593Smuzhiyun	};
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun	vbus5v0_typec: vbus5v0-typec {
141*4882a593Smuzhiyun		compatible = "regulator-fixed";
142*4882a593Smuzhiyun		regulator-name = "vbus5v0_typec";
143*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
144*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
145*4882a593Smuzhiyun		enable-active-high;
146*4882a593Smuzhiyun		gpio = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>;
147*4882a593Smuzhiyun		vin-supply = <&vcc5v0_usb>;
148*4882a593Smuzhiyun		pinctrl-names = "default";
149*4882a593Smuzhiyun		pinctrl-0 = <&typec5v_pwren>;
150*4882a593Smuzhiyun	};
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun	vcc3v3_lcd_n: vcc3v3-lcd0-n {
153*4882a593Smuzhiyun		compatible = "regulator-fixed";
154*4882a593Smuzhiyun		regulator-name = "vcc3v3_lcd0_n";
155*4882a593Smuzhiyun		regulator-boot-on;
156*4882a593Smuzhiyun		enable-active-high;
157*4882a593Smuzhiyun		gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
158*4882a593Smuzhiyun		vin-supply = <&vcc_1v8_s0>;
159*4882a593Smuzhiyun	};
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun	vcc3v3_pcie30: vcc3v3-pcie30 {
162*4882a593Smuzhiyun		compatible = "regulator-fixed";
163*4882a593Smuzhiyun		regulator-name = "vcc3v3_pcie30";
164*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
165*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
166*4882a593Smuzhiyun		enable-active-high;
167*4882a593Smuzhiyun		gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
168*4882a593Smuzhiyun		startup-delay-us = <5000>;
169*4882a593Smuzhiyun		vin-supply = <&vcc12v_dcin>;
170*4882a593Smuzhiyun	};
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun	vcc5v0_host: vcc5v0-host {
173*4882a593Smuzhiyun		compatible = "regulator-fixed";
174*4882a593Smuzhiyun		regulator-name = "vcc5v0_host";
175*4882a593Smuzhiyun		regulator-boot-on;
176*4882a593Smuzhiyun		regulator-always-on;
177*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
178*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
179*4882a593Smuzhiyun		enable-active-high;
180*4882a593Smuzhiyun		gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
181*4882a593Smuzhiyun		vin-supply = <&vcc5v0_usb>;
182*4882a593Smuzhiyun		pinctrl-names = "default";
183*4882a593Smuzhiyun		pinctrl-0 = <&vcc5v0_host_en>;
184*4882a593Smuzhiyun	};
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun	vcc_mipicsi0: vcc-mipicsi0-regulator {
187*4882a593Smuzhiyun		compatible = "regulator-fixed";
188*4882a593Smuzhiyun		gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
189*4882a593Smuzhiyun		pinctrl-names = "default";
190*4882a593Smuzhiyun		pinctrl-0 = <&mipicsi0_pwr>;
191*4882a593Smuzhiyun		regulator-name = "vcc_mipicsi0";
192*4882a593Smuzhiyun		enable-active-high;
193*4882a593Smuzhiyun	};
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun	vcc_mipicsi1: vcc-mipicsi1-regulator {
196*4882a593Smuzhiyun		compatible = "regulator-fixed";
197*4882a593Smuzhiyun		gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
198*4882a593Smuzhiyun		pinctrl-names = "default";
199*4882a593Smuzhiyun		pinctrl-0 = <&mipicsi1_pwr>;
200*4882a593Smuzhiyun		regulator-name = "vcc_mipicsi1";
201*4882a593Smuzhiyun		enable-active-high;
202*4882a593Smuzhiyun	};
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun	vcc_mipidcphy0: vcc-mipidcphy0-regulator {
205*4882a593Smuzhiyun		compatible = "regulator-fixed";
206*4882a593Smuzhiyun		gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>;
207*4882a593Smuzhiyun		pinctrl-names = "default";
208*4882a593Smuzhiyun		pinctrl-0 = <&mipidcphy0_pwr>;
209*4882a593Smuzhiyun		regulator-name = "vcc_mipidcphy0";
210*4882a593Smuzhiyun		enable-active-high;
211*4882a593Smuzhiyun	};
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun	wireless_bluetooth: wireless-bluetooth {
214*4882a593Smuzhiyun		compatible = "bluetooth-platdata";
215*4882a593Smuzhiyun		clocks = <&hym8563>;
216*4882a593Smuzhiyun		clock-names = "ext_clock";
217*4882a593Smuzhiyun		uart_rts_gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>;
218*4882a593Smuzhiyun		pinctrl-names = "default", "rts_gpio";
219*4882a593Smuzhiyun		pinctrl-0 = <&uart8m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>;
220*4882a593Smuzhiyun		pinctrl-1 = <&uart8_gpios>;
221*4882a593Smuzhiyun		BT,reset_gpio    = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
222*4882a593Smuzhiyun		BT,wake_gpio     = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
223*4882a593Smuzhiyun		BT,wake_host_irq = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>;
224*4882a593Smuzhiyun		status = "okay";
225*4882a593Smuzhiyun	};
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun	wireless_wlan: wireless-wlan {
228*4882a593Smuzhiyun		compatible = "wlan-platdata";
229*4882a593Smuzhiyun		wifi_chip_type = "ap6255";
230*4882a593Smuzhiyun		pinctrl-names = "default";
231*4882a593Smuzhiyun		pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>;
232*4882a593Smuzhiyun		WIFI,host_wake_irq = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
233*4882a593Smuzhiyun		WIFI,poweren_gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>;
234*4882a593Smuzhiyun		status = "okay";
235*4882a593Smuzhiyun	};
236*4882a593Smuzhiyun};
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun&backlight {
239*4882a593Smuzhiyun	pwms = <&pwm2 0 25000 0>;
240*4882a593Smuzhiyun	status = "okay";
241*4882a593Smuzhiyun};
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun&combphy0_ps {
244*4882a593Smuzhiyun	status = "okay";
245*4882a593Smuzhiyun};
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun&combphy1_ps {
248*4882a593Smuzhiyun	status = "okay";
249*4882a593Smuzhiyun};
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun&combphy2_psu {
252*4882a593Smuzhiyun	status = "okay";
253*4882a593Smuzhiyun};
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun&dp0 {
256*4882a593Smuzhiyun	status = "okay";
257*4882a593Smuzhiyun};
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun&dp0_in_vp2 {
260*4882a593Smuzhiyun	status = "okay";
261*4882a593Smuzhiyun};
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun&dp0_sound{
264*4882a593Smuzhiyun	status = "okay";
265*4882a593Smuzhiyun};
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun&dp1 {
268*4882a593Smuzhiyun	pinctrl-names = "default";
269*4882a593Smuzhiyun	pinctrl-0 = <&dp1_hpd>;
270*4882a593Smuzhiyun	hpd-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
271*4882a593Smuzhiyun	status = "okay";
272*4882a593Smuzhiyun};
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun&dp1_in_vp2 {
275*4882a593Smuzhiyun	status = "okay";
276*4882a593Smuzhiyun};
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun/*
279*4882a593Smuzhiyun * mipi_dcphy0 needs to be enabled
280*4882a593Smuzhiyun * when dsi0 is enabled
281*4882a593Smuzhiyun */
282*4882a593Smuzhiyun&dsi0 {
283*4882a593Smuzhiyun	status = "okay";
284*4882a593Smuzhiyun};
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun&dsi0_in_vp2 {
287*4882a593Smuzhiyun	status = "disabled";
288*4882a593Smuzhiyun};
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun&dsi0_in_vp3 {
291*4882a593Smuzhiyun	status = "okay";
292*4882a593Smuzhiyun};
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun&dsi0_panel {
295*4882a593Smuzhiyun	power-supply = <&vcc3v3_lcd_n>;
296*4882a593Smuzhiyun	reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>;
297*4882a593Smuzhiyun	pinctrl-names = "default";
298*4882a593Smuzhiyun	pinctrl-0 = <&lcd_rst_gpio>;
299*4882a593Smuzhiyun};
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun/*
302*4882a593Smuzhiyun * mipi_dcphy1 needs to be enabled
303*4882a593Smuzhiyun * when dsi1 is enabled
304*4882a593Smuzhiyun */
305*4882a593Smuzhiyun&dsi1 {
306*4882a593Smuzhiyun	status = "disabled";
307*4882a593Smuzhiyun};
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun&dsi1_in_vp2 {
310*4882a593Smuzhiyun	status = "disabled";
311*4882a593Smuzhiyun};
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun&dsi1_in_vp3 {
314*4882a593Smuzhiyun	status = "disabled";
315*4882a593Smuzhiyun};
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun&dsi1_panel {
318*4882a593Smuzhiyun	power-supply = <&vcc3v3_lcd_n>;
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun	/*
321*4882a593Smuzhiyun	 * because in hardware, the two screens share the reset pin,
322*4882a593Smuzhiyun	 * so reset-gpios need only in dsi1 enable and dsi0 disabled
323*4882a593Smuzhiyun	 * case.
324*4882a593Smuzhiyun	 */
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun	//reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>;
327*4882a593Smuzhiyun	//pinctrl-names = "default";
328*4882a593Smuzhiyun	//pinctrl-0 = <&lcd_rst_gpio>;
329*4882a593Smuzhiyun};
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun&gmac0 {
332*4882a593Smuzhiyun	/* Use rgmii-rxid mode to disable rx delay inside Soc */
333*4882a593Smuzhiyun	phy-mode = "rgmii-rxid";
334*4882a593Smuzhiyun	clock_in_out = "output";
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun	snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
337*4882a593Smuzhiyun	snps,reset-active-low;
338*4882a593Smuzhiyun	/* Reset time is 20ms, 100ms for rtl8211f */
339*4882a593Smuzhiyun	snps,reset-delays-us = <0 20000 100000>;
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun	pinctrl-names = "default";
342*4882a593Smuzhiyun	pinctrl-0 = <&gmac0_miim
343*4882a593Smuzhiyun		     &gmac0_tx_bus2
344*4882a593Smuzhiyun		     &gmac0_rx_bus2
345*4882a593Smuzhiyun		     &gmac0_rgmii_clk
346*4882a593Smuzhiyun		     &gmac0_rgmii_bus>;
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun	tx_delay = <0x43>;
349*4882a593Smuzhiyun	/* rx_delay = <0x3f>; */
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun	phy-handle = <&rgmii_phy>;
352*4882a593Smuzhiyun	status = "okay";
353*4882a593Smuzhiyun};
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun&hdmi0 {
356*4882a593Smuzhiyun	enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>;
357*4882a593Smuzhiyun	status = "okay";
358*4882a593Smuzhiyun};
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun&hdmi0_in_vp0 {
361*4882a593Smuzhiyun	status = "okay";
362*4882a593Smuzhiyun};
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun&hdmi0_sound {
365*4882a593Smuzhiyun	status = "okay";
366*4882a593Smuzhiyun};
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun&hdmi1 {
369*4882a593Smuzhiyun	enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
370*4882a593Smuzhiyun	status = "okay";
371*4882a593Smuzhiyun};
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun&hdmi1_in_vp1 {
374*4882a593Smuzhiyun	status = "okay";
375*4882a593Smuzhiyun};
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun&hdmi1_sound {
378*4882a593Smuzhiyun	status = "okay";
379*4882a593Smuzhiyun};
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun/* Should work with at least 128MB cma reserved above. */
382*4882a593Smuzhiyun&hdmirx_ctrler {
383*4882a593Smuzhiyun	status = "okay";
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun	#sound-dai-cells = <1>;
386*4882a593Smuzhiyun	/* Effective level used to trigger HPD: 0-low, 1-high */
387*4882a593Smuzhiyun	hpd-trigger-level = <1>;
388*4882a593Smuzhiyun	hdmirx-det-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
389*4882a593Smuzhiyun	pinctrl-names = "default";
390*4882a593Smuzhiyun	pinctrl-0 = <&hdmim1_rx &hdmirx_det>;
391*4882a593Smuzhiyun};
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun&hdptxphy_hdmi0 {
394*4882a593Smuzhiyun	status = "okay";
395*4882a593Smuzhiyun};
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun&hdptxphy_hdmi1 {
398*4882a593Smuzhiyun	status = "okay";
399*4882a593Smuzhiyun};
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun&i2c2 {
402*4882a593Smuzhiyun	status = "okay";
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun	usbc0: fusb302@22 {
405*4882a593Smuzhiyun		compatible = "fcs,fusb302";
406*4882a593Smuzhiyun		reg = <0x22>;
407*4882a593Smuzhiyun		interrupt-parent = <&gpio3>;
408*4882a593Smuzhiyun		interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>;
409*4882a593Smuzhiyun		pinctrl-names = "default";
410*4882a593Smuzhiyun		pinctrl-0 = <&usbc0_int>;
411*4882a593Smuzhiyun		vbus-supply = <&vbus5v0_typec>;
412*4882a593Smuzhiyun		status = "okay";
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun		ports {
415*4882a593Smuzhiyun			#address-cells = <1>;
416*4882a593Smuzhiyun			#size-cells = <0>;
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun			port@0 {
419*4882a593Smuzhiyun				reg = <0>;
420*4882a593Smuzhiyun				usbc0_role_sw: endpoint@0 {
421*4882a593Smuzhiyun					remote-endpoint = <&dwc3_0_role_switch>;
422*4882a593Smuzhiyun				};
423*4882a593Smuzhiyun			};
424*4882a593Smuzhiyun		};
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun		usb_con: connector {
427*4882a593Smuzhiyun			compatible = "usb-c-connector";
428*4882a593Smuzhiyun			label = "USB-C";
429*4882a593Smuzhiyun			data-role = "dual";
430*4882a593Smuzhiyun			power-role = "dual";
431*4882a593Smuzhiyun			try-power-role = "sink";
432*4882a593Smuzhiyun			op-sink-microwatt = <1000000>;
433*4882a593Smuzhiyun			sink-pdos =
434*4882a593Smuzhiyun				<PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
435*4882a593Smuzhiyun			source-pdos =
436*4882a593Smuzhiyun				<PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun			altmodes {
439*4882a593Smuzhiyun				#address-cells = <1>;
440*4882a593Smuzhiyun				#size-cells = <0>;
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun				altmode@0 {
443*4882a593Smuzhiyun					reg = <0>;
444*4882a593Smuzhiyun					svid = <0xff01>;
445*4882a593Smuzhiyun					vdo = <0xffffffff>;
446*4882a593Smuzhiyun				};
447*4882a593Smuzhiyun			};
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun			ports {
450*4882a593Smuzhiyun				#address-cells = <1>;
451*4882a593Smuzhiyun				#size-cells = <0>;
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun				port@0 {
454*4882a593Smuzhiyun					reg = <0>;
455*4882a593Smuzhiyun					usbc0_orien_sw: endpoint {
456*4882a593Smuzhiyun						remote-endpoint = <&usbdp_phy0_orientation_switch>;
457*4882a593Smuzhiyun					};
458*4882a593Smuzhiyun				};
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun				port@1 {
461*4882a593Smuzhiyun					reg = <1>;
462*4882a593Smuzhiyun					dp_altmode_mux: endpoint {
463*4882a593Smuzhiyun						remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
464*4882a593Smuzhiyun					};
465*4882a593Smuzhiyun				};
466*4882a593Smuzhiyun			};
467*4882a593Smuzhiyun		};
468*4882a593Smuzhiyun	};
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun	hym8563: hym8563@51 {
471*4882a593Smuzhiyun		compatible = "haoyu,hym8563";
472*4882a593Smuzhiyun		reg = <0x51>;
473*4882a593Smuzhiyun		#clock-cells = <0>;
474*4882a593Smuzhiyun		clock-frequency = <32768>;
475*4882a593Smuzhiyun		clock-output-names = "hym8563";
476*4882a593Smuzhiyun		pinctrl-names = "default";
477*4882a593Smuzhiyun		pinctrl-0 = <&hym8563_int>;
478*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
479*4882a593Smuzhiyun		interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>;
480*4882a593Smuzhiyun		wakeup-source;
481*4882a593Smuzhiyun	};
482*4882a593Smuzhiyun};
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun&i2c6 {
485*4882a593Smuzhiyun	status = "okay";
486*4882a593Smuzhiyun	gt1x: gt1x@14 {
487*4882a593Smuzhiyun		compatible = "goodix,gt1x";
488*4882a593Smuzhiyun		reg = <0x14>;
489*4882a593Smuzhiyun		pinctrl-names = "default";
490*4882a593Smuzhiyun		pinctrl-0 = <&touch_gpio>;
491*4882a593Smuzhiyun		goodix,rst-gpio = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>;
492*4882a593Smuzhiyun		goodix,irq-gpio = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_LOW>;
493*4882a593Smuzhiyun		power-supply = <&vcc3v3_lcd_n>;
494*4882a593Smuzhiyun	};
495*4882a593Smuzhiyun};
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun&i2c7 {
498*4882a593Smuzhiyun	status = "okay";
499*4882a593Smuzhiyun	es8388: es8388@11 {
500*4882a593Smuzhiyun		status = "okay";
501*4882a593Smuzhiyun		#sound-dai-cells = <0>;
502*4882a593Smuzhiyun		compatible = "everest,es8388", "everest,es8323";
503*4882a593Smuzhiyun		reg = <0x11>;
504*4882a593Smuzhiyun		clocks = <&mclkout_i2s0>;
505*4882a593Smuzhiyun		clock-names = "mclk";
506*4882a593Smuzhiyun		assigned-clocks = <&mclkout_i2s0>;
507*4882a593Smuzhiyun		assigned-clock-rates = <12288000>;
508*4882a593Smuzhiyun		pinctrl-names = "default";
509*4882a593Smuzhiyun		pinctrl-0 = <&i2s0_mclk>;
510*4882a593Smuzhiyun	};
511*4882a593Smuzhiyun};
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun&i2s5_8ch {
514*4882a593Smuzhiyun	status = "okay";
515*4882a593Smuzhiyun};
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun&i2s6_8ch {
518*4882a593Smuzhiyun	status = "okay";
519*4882a593Smuzhiyun};
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun&i2s7_8ch {
522*4882a593Smuzhiyun	status = "okay";
523*4882a593Smuzhiyun};
524*4882a593Smuzhiyun
525*4882a593Smuzhiyun&mdio0 {
526*4882a593Smuzhiyun	rgmii_phy: phy@1 {
527*4882a593Smuzhiyun		compatible = "ethernet-phy-ieee802.3-c22";
528*4882a593Smuzhiyun		reg = <0x1>;
529*4882a593Smuzhiyun	};
530*4882a593Smuzhiyun};
531*4882a593Smuzhiyun
532*4882a593Smuzhiyun&mipi_dcphy0 {
533*4882a593Smuzhiyun	status = "okay";
534*4882a593Smuzhiyun};
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun&mipi_dcphy1 {
537*4882a593Smuzhiyun	status = "disabled";
538*4882a593Smuzhiyun};
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun&pcie2x1l0 {
541*4882a593Smuzhiyun	reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
542*4882a593Smuzhiyun	rockchip,skip-scan-in-resume;
543*4882a593Smuzhiyun	status = "okay";
544*4882a593Smuzhiyun};
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun&pcie2x1l1 {
547*4882a593Smuzhiyun	reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
548*4882a593Smuzhiyun	pinctrl-names = "default";
549*4882a593Smuzhiyun	pinctrl-0 = <&rtl8111_isolate>;
550*4882a593Smuzhiyun	status = "okay";
551*4882a593Smuzhiyun};
552*4882a593Smuzhiyun
553*4882a593Smuzhiyun&pcie30phy {
554*4882a593Smuzhiyun	rockchip,pcie30-phymode = <PHY_MODE_PCIE_AGGREGATION>;
555*4882a593Smuzhiyun	status = "okay";
556*4882a593Smuzhiyun};
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun&pcie3x4 {
559*4882a593Smuzhiyun	reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
560*4882a593Smuzhiyun	vpcie3v3-supply = <&vcc3v3_pcie30>;
561*4882a593Smuzhiyun	pinctrl-names = "default";
562*4882a593Smuzhiyun	pinctrl-0 = <&pcie30x4_clkreqn_m1>;
563*4882a593Smuzhiyun	status = "okay";
564*4882a593Smuzhiyun};
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun&pinctrl {
567*4882a593Smuzhiyun	cam {
568*4882a593Smuzhiyun		mipicsi0_pwr: mipicsi0-pwr {
569*4882a593Smuzhiyun			rockchip,pins =
570*4882a593Smuzhiyun				/* camera power en */
571*4882a593Smuzhiyun				<1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
572*4882a593Smuzhiyun		};
573*4882a593Smuzhiyun		mipicsi1_pwr: mipicsi1-pwr {
574*4882a593Smuzhiyun			rockchip,pins =
575*4882a593Smuzhiyun				/* camera power en */
576*4882a593Smuzhiyun				<1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
577*4882a593Smuzhiyun		};
578*4882a593Smuzhiyun		mipidcphy0_pwr: mipidcphy0-pwr {
579*4882a593Smuzhiyun			rockchip,pins =
580*4882a593Smuzhiyun				/* camera power en */
581*4882a593Smuzhiyun				<2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
582*4882a593Smuzhiyun		};
583*4882a593Smuzhiyun	};
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun	dp {
586*4882a593Smuzhiyun		dp1_hpd: dp1-hpd {
587*4882a593Smuzhiyun			rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
588*4882a593Smuzhiyun		};
589*4882a593Smuzhiyun	};
590*4882a593Smuzhiyun
591*4882a593Smuzhiyun	hdmi {
592*4882a593Smuzhiyun		hdmirx_det: hdmirx-det {
593*4882a593Smuzhiyun			rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
594*4882a593Smuzhiyun		};
595*4882a593Smuzhiyun	};
596*4882a593Smuzhiyun
597*4882a593Smuzhiyun	headphone {
598*4882a593Smuzhiyun		hp_det: hp-det {
599*4882a593Smuzhiyun			rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
600*4882a593Smuzhiyun		};
601*4882a593Smuzhiyun	};
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun	hym8563 {
604*4882a593Smuzhiyun		hym8563_int: hym8563-int {
605*4882a593Smuzhiyun			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
606*4882a593Smuzhiyun		};
607*4882a593Smuzhiyun	};
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun	lcd {
610*4882a593Smuzhiyun		lcd_rst_gpio: lcd-rst-gpio {
611*4882a593Smuzhiyun			rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
612*4882a593Smuzhiyun		};
613*4882a593Smuzhiyun	};
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun	pcie30x4 {
616*4882a593Smuzhiyun		pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 {
617*4882a593Smuzhiyun			rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
618*4882a593Smuzhiyun		};
619*4882a593Smuzhiyun	};
620*4882a593Smuzhiyun
621*4882a593Smuzhiyun	rtl8111 {
622*4882a593Smuzhiyun		rtl8111_isolate: rtl8111-isolate {
623*4882a593Smuzhiyun			rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
624*4882a593Smuzhiyun		};
625*4882a593Smuzhiyun	};
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun	touch {
628*4882a593Smuzhiyun		touch_gpio: touch-gpio {
629*4882a593Smuzhiyun			rockchip,pins =
630*4882a593Smuzhiyun				<0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>,
631*4882a593Smuzhiyun				<0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
632*4882a593Smuzhiyun		};
633*4882a593Smuzhiyun	};
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun	usb {
636*4882a593Smuzhiyun		vcc5v0_host_en: vcc5v0-host-en {
637*4882a593Smuzhiyun			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
638*4882a593Smuzhiyun		};
639*4882a593Smuzhiyun	};
640*4882a593Smuzhiyun
641*4882a593Smuzhiyun	usb-typec {
642*4882a593Smuzhiyun		usbc0_int: usbc0-int {
643*4882a593Smuzhiyun			rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
644*4882a593Smuzhiyun		};
645*4882a593Smuzhiyun
646*4882a593Smuzhiyun		typec5v_pwren: typec5v-pwren {
647*4882a593Smuzhiyun			rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
648*4882a593Smuzhiyun		};
649*4882a593Smuzhiyun	};
650*4882a593Smuzhiyun
651*4882a593Smuzhiyun	wireless-bluetooth {
652*4882a593Smuzhiyun		uart8_gpios: uart8-gpios {
653*4882a593Smuzhiyun			rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
654*4882a593Smuzhiyun		};
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun		bt_reset_gpio: bt-reset-gpio {
657*4882a593Smuzhiyun			rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
658*4882a593Smuzhiyun		};
659*4882a593Smuzhiyun
660*4882a593Smuzhiyun		bt_wake_gpio: bt-wake-gpio {
661*4882a593Smuzhiyun			rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
662*4882a593Smuzhiyun		};
663*4882a593Smuzhiyun
664*4882a593Smuzhiyun		bt_irq_gpio: bt-irq-gpio {
665*4882a593Smuzhiyun			rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
666*4882a593Smuzhiyun		};
667*4882a593Smuzhiyun	};
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun	wireless-wlan {
670*4882a593Smuzhiyun		wifi_host_wake_irq: wifi-host-wake-irq {
671*4882a593Smuzhiyun			rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>;
672*4882a593Smuzhiyun		};
673*4882a593Smuzhiyun
674*4882a593Smuzhiyun		wifi_poweren_gpio: wifi-poweren-gpio {
675*4882a593Smuzhiyun			rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
676*4882a593Smuzhiyun		};
677*4882a593Smuzhiyun	};
678*4882a593Smuzhiyun};
679*4882a593Smuzhiyun
680*4882a593Smuzhiyun&pwm2 {
681*4882a593Smuzhiyun	status = "okay";
682*4882a593Smuzhiyun};
683*4882a593Smuzhiyun
684*4882a593Smuzhiyun&pwm9 {
685*4882a593Smuzhiyun	pinctrl-0 = <&pwm9m1_pins>;
686*4882a593Smuzhiyun	status = "okay";
687*4882a593Smuzhiyun};
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun&route_dsi0 {
690*4882a593Smuzhiyun	status = "okay";
691*4882a593Smuzhiyun	connect = <&vp3_out_dsi0>;
692*4882a593Smuzhiyun};
693*4882a593Smuzhiyun
694*4882a593Smuzhiyun&route_dsi1 {
695*4882a593Smuzhiyun	status = "disabled";
696*4882a593Smuzhiyun	connect = <&vp3_out_dsi1>;
697*4882a593Smuzhiyun};
698*4882a593Smuzhiyun
699*4882a593Smuzhiyun&route_hdmi0 {
700*4882a593Smuzhiyun	status = "okay";
701*4882a593Smuzhiyun	connect = <&vp0_out_hdmi0>;
702*4882a593Smuzhiyun};
703*4882a593Smuzhiyun
704*4882a593Smuzhiyun&route_hdmi1 {
705*4882a593Smuzhiyun	status = "okay";
706*4882a593Smuzhiyun	connect = <&vp1_out_hdmi1>;
707*4882a593Smuzhiyun};
708*4882a593Smuzhiyun
709*4882a593Smuzhiyun&sata0 {
710*4882a593Smuzhiyun	status = "okay";
711*4882a593Smuzhiyun};
712*4882a593Smuzhiyun
713*4882a593Smuzhiyun&spdif_tx2 {
714*4882a593Smuzhiyun	status = "okay";
715*4882a593Smuzhiyun};
716*4882a593Smuzhiyun
717*4882a593Smuzhiyun&u2phy0_otg {
718*4882a593Smuzhiyun	rockchip,typec-vbus-det;
719*4882a593Smuzhiyun};
720*4882a593Smuzhiyun
721*4882a593Smuzhiyun&u2phy1_otg {
722*4882a593Smuzhiyun	phy-supply = <&vcc5v0_host>;
723*4882a593Smuzhiyun};
724*4882a593Smuzhiyun
725*4882a593Smuzhiyun&u2phy2_host {
726*4882a593Smuzhiyun	phy-supply = <&vcc5v0_host>;
727*4882a593Smuzhiyun};
728*4882a593Smuzhiyun
729*4882a593Smuzhiyun&u2phy3_host {
730*4882a593Smuzhiyun	phy-supply = <&vcc5v0_host>;
731*4882a593Smuzhiyun};
732*4882a593Smuzhiyun
733*4882a593Smuzhiyun&uart8 {
734*4882a593Smuzhiyun	status = "okay";
735*4882a593Smuzhiyun	pinctrl-names = "default";
736*4882a593Smuzhiyun	pinctrl-0 = <&uart8m1_xfer &uart8m1_ctsn>;
737*4882a593Smuzhiyun};
738*4882a593Smuzhiyun
739*4882a593Smuzhiyun&usbdp_phy0 {
740*4882a593Smuzhiyun	orientation-switch;
741*4882a593Smuzhiyun	svid = <0xff01>;
742*4882a593Smuzhiyun	sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
743*4882a593Smuzhiyun	sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
744*4882a593Smuzhiyun
745*4882a593Smuzhiyun	port {
746*4882a593Smuzhiyun		#address-cells = <1>;
747*4882a593Smuzhiyun		#size-cells = <0>;
748*4882a593Smuzhiyun		usbdp_phy0_orientation_switch: endpoint@0 {
749*4882a593Smuzhiyun			reg = <0>;
750*4882a593Smuzhiyun			remote-endpoint = <&usbc0_orien_sw>;
751*4882a593Smuzhiyun		};
752*4882a593Smuzhiyun
753*4882a593Smuzhiyun		usbdp_phy0_dp_altmode_mux: endpoint@1 {
754*4882a593Smuzhiyun			reg = <1>;
755*4882a593Smuzhiyun			remote-endpoint = <&dp_altmode_mux>;
756*4882a593Smuzhiyun		};
757*4882a593Smuzhiyun	};
758*4882a593Smuzhiyun};
759*4882a593Smuzhiyun
760*4882a593Smuzhiyun&usbdp_phy1 {
761*4882a593Smuzhiyun	rockchip,dp-lane-mux = <2 3>;
762*4882a593Smuzhiyun};
763*4882a593Smuzhiyun
764*4882a593Smuzhiyun&usbdrd_dwc3_0 {
765*4882a593Smuzhiyun	dr_mode = "otg";
766*4882a593Smuzhiyun	usb-role-switch;
767*4882a593Smuzhiyun	port {
768*4882a593Smuzhiyun		#address-cells = <1>;
769*4882a593Smuzhiyun		#size-cells = <0>;
770*4882a593Smuzhiyun		dwc3_0_role_switch: endpoint@0 {
771*4882a593Smuzhiyun			reg = <0>;
772*4882a593Smuzhiyun			remote-endpoint = <&usbc0_role_sw>;
773*4882a593Smuzhiyun		};
774*4882a593Smuzhiyun	};
775*4882a593Smuzhiyun};
776*4882a593Smuzhiyun
777*4882a593Smuzhiyun&usbhost3_0 {
778*4882a593Smuzhiyun	status = "disabled";
779*4882a593Smuzhiyun};
780*4882a593Smuzhiyun
781*4882a593Smuzhiyun&usbhost_dwc3_0 {
782*4882a593Smuzhiyun	status = "disabled";
783*4882a593Smuzhiyun};
784