xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm64/rockchip/rk3568-toybrick.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
8*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h>
9*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h>
10*4882a593Smuzhiyun#include <dt-bindings/input/rk-input.h>
11*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h>
12*4882a593Smuzhiyun#include <dt-bindings/sensor-dev.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun/ {
15*4882a593Smuzhiyun	adc_keys: adc-keys {
16*4882a593Smuzhiyun		compatible = "adc-keys";
17*4882a593Smuzhiyun		io-channels = <&saradc 0>;
18*4882a593Smuzhiyun		io-channel-names = "buttons";
19*4882a593Smuzhiyun		keyup-threshold-microvolt = <1800000>;
20*4882a593Smuzhiyun		poll-interval = <100>;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun		vol-up-key {
23*4882a593Smuzhiyun			label = "volume up";
24*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
25*4882a593Smuzhiyun			press-threshold-microvolt = <1750>;
26*4882a593Smuzhiyun		};
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun		vol-down-key {
29*4882a593Smuzhiyun			label = "volume down";
30*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEDOWN>;
31*4882a593Smuzhiyun			press-threshold-microvolt = <297500>;
32*4882a593Smuzhiyun		};
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun		menu-key {
35*4882a593Smuzhiyun			label = "menu";
36*4882a593Smuzhiyun			linux,code = <KEY_MENU>;
37*4882a593Smuzhiyun			press-threshold-microvolt = <980000>;
38*4882a593Smuzhiyun		};
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun		back-key {
41*4882a593Smuzhiyun			label = "back";
42*4882a593Smuzhiyun			linux,code = <KEY_BACK>;
43*4882a593Smuzhiyun			press-threshold-microvolt = <1305500>;
44*4882a593Smuzhiyun		};
45*4882a593Smuzhiyun	};
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun	audiopwmout_diff: audiopwmout-diff {
48*4882a593Smuzhiyun		status = "disabled";
49*4882a593Smuzhiyun		compatible = "simple-audio-card";
50*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
51*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,audiopwmout-diff";
52*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <256>;
53*4882a593Smuzhiyun		simple-audio-card,bitclock-master = <&master>;
54*4882a593Smuzhiyun		simple-audio-card,frame-master = <&master>;
55*4882a593Smuzhiyun		simple-audio-card,cpu {
56*4882a593Smuzhiyun			sound-dai = <&i2s3_2ch>;
57*4882a593Smuzhiyun		};
58*4882a593Smuzhiyun		master: simple-audio-card,codec {
59*4882a593Smuzhiyun			sound-dai = <&dig_acodec>;
60*4882a593Smuzhiyun		};
61*4882a593Smuzhiyun	};
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun	/*
64*4882a593Smuzhiyun	 * extliux conf: extlinux.conf.${FLAG}.${BOARD_ID}
65*4882a593Smuzhiyun	 * dtb file:     toybrick.dtb.${FLAG}.${BOARD_ID}
66*4882a593Smuzhiyun	 */
67*4882a593Smuzhiyun	board_id: board-id {
68*4882a593Smuzhiyun		compatible = "board-id";
69*4882a593Smuzhiyun		io-channels = <&saradc 4>;
70*4882a593Smuzhiyun		/*
71*4882a593Smuzhiyun		 * ID:    adc-value/adc-io
72*4882a593Smuzhiyun		 * -------------------------
73*4882a593Smuzhiyun		 * 0:     adc-io is low level
74*4882a593Smuzhiyun		 * 1:     0   ~ 100
75*4882a593Smuzhiyun		 * 2:     100 ~ 199
76*4882a593Smuzhiyun		 * 3:     200 ~ 299
77*4882a593Smuzhiyun		 * 4:     300 ~ 399
78*4882a593Smuzhiyun		 * 5:     400 ~ 499
79*4882a593Smuzhiyun		 * 6:     500 ~ 599
80*4882a593Smuzhiyun		 * 7:     600 ~ 699
81*4882a593Smuzhiyun		 * 8:     700 ~ 799
82*4882a593Smuzhiyun		 * 9:     800 ~ 899
83*4882a593Smuzhiyun		 * 10:    900 ~ 1024
84*4882a593Smuzhiyun		 */
85*4882a593Smuzhiyun		adc-io = <29>;// GPIO0_D5
86*4882a593Smuzhiyun		thresholds = <100 200 300 400 500 600 700 800 900>;
87*4882a593Smuzhiyun	};
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun	backlight: backlight {
90*4882a593Smuzhiyun		compatible = "pwm-backlight";
91*4882a593Smuzhiyun		pwms = <&pwm4 0 25000 0>;
92*4882a593Smuzhiyun		brightness-levels = <
93*4882a593Smuzhiyun			  0  20  20  21  21  22  22  23
94*4882a593Smuzhiyun			 23  24  24  25  25  26  26  27
95*4882a593Smuzhiyun			 27  28  28  29  29  30  30  31
96*4882a593Smuzhiyun			 31  32  32  33  33  34  34  35
97*4882a593Smuzhiyun			 35  36  36  37  37  38  38  39
98*4882a593Smuzhiyun			 40  41  42  43  44  45  46  47
99*4882a593Smuzhiyun			 48  49  50  51  52  53  54  55
100*4882a593Smuzhiyun			 56  57  58  59  60  61  62  63
101*4882a593Smuzhiyun			 64  65  66  67  68  69  70  71
102*4882a593Smuzhiyun			 72  73  74  75  76  77  78  79
103*4882a593Smuzhiyun			 80  81  82  83  84  85  86  87
104*4882a593Smuzhiyun			 88  89  90  91  92  93  94  95
105*4882a593Smuzhiyun			 96  97  98  99 100 101 102 103
106*4882a593Smuzhiyun			104 105 106 107 108 109 110 111
107*4882a593Smuzhiyun			112 113 114 115 116 117 118 119
108*4882a593Smuzhiyun			120 121 122 123 124 125 126 127
109*4882a593Smuzhiyun			128 129 130 131 132 133 134 135
110*4882a593Smuzhiyun			136 137 138 139 140 141 142 143
111*4882a593Smuzhiyun			144 145 146 147 148 149 150 151
112*4882a593Smuzhiyun			152 153 154 155 156 157 158 159
113*4882a593Smuzhiyun			160 161 162 163 164 165 166 167
114*4882a593Smuzhiyun			168 169 170 171 172 173 174 175
115*4882a593Smuzhiyun			176 177 178 179 180 181 182 183
116*4882a593Smuzhiyun			184 185 186 187 188 189 190 191
117*4882a593Smuzhiyun			192 193 194 195 196 197 198 199
118*4882a593Smuzhiyun			200 201 202 203 204 205 206 207
119*4882a593Smuzhiyun			208 209 210 211 212 213 214 215
120*4882a593Smuzhiyun			216 217 218 219 220 221 222 223
121*4882a593Smuzhiyun			224 225 226 227 228 229 230 231
122*4882a593Smuzhiyun			232 233 234 235 236 237 238 239
123*4882a593Smuzhiyun			240 241 242 243 244 245 246 247
124*4882a593Smuzhiyun			248 249 250 251 252 253 254 255
125*4882a593Smuzhiyun		>;
126*4882a593Smuzhiyun		default-brightness-level = <200>;
127*4882a593Smuzhiyun	};
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun	backlight1: backlight1 {
130*4882a593Smuzhiyun		compatible = "pwm-backlight";
131*4882a593Smuzhiyun		pwms = <&pwm5 0 25000 0>;
132*4882a593Smuzhiyun		brightness-levels = <
133*4882a593Smuzhiyun			  0  20  20  21  21  22  22  23
134*4882a593Smuzhiyun			 23  24  24  25  25  26  26  27
135*4882a593Smuzhiyun			 27  28  28  29  29  30  30  31
136*4882a593Smuzhiyun			 31  32  32  33  33  34  34  35
137*4882a593Smuzhiyun			 35  36  36  37  37  38  38  39
138*4882a593Smuzhiyun			 40  41  42  43  44  45  46  47
139*4882a593Smuzhiyun			 48  49  50  51  52  53  54  55
140*4882a593Smuzhiyun			 56  57  58  59  60  61  62  63
141*4882a593Smuzhiyun			 64  65  66  67  68  69  70  71
142*4882a593Smuzhiyun			 72  73  74  75  76  77  78  79
143*4882a593Smuzhiyun			 80  81  82  83  84  85  86  87
144*4882a593Smuzhiyun			 88  89  90  91  92  93  94  95
145*4882a593Smuzhiyun			 96  97  98  99 100 101 102 103
146*4882a593Smuzhiyun			104 105 106 107 108 109 110 111
147*4882a593Smuzhiyun			112 113 114 115 116 117 118 119
148*4882a593Smuzhiyun			120 121 122 123 124 125 126 127
149*4882a593Smuzhiyun			128 129 130 131 132 133 134 135
150*4882a593Smuzhiyun			136 137 138 139 140 141 142 143
151*4882a593Smuzhiyun			144 145 146 147 148 149 150 151
152*4882a593Smuzhiyun			152 153 154 155 156 157 158 159
153*4882a593Smuzhiyun			160 161 162 163 164 165 166 167
154*4882a593Smuzhiyun			168 169 170 171 172 173 174 175
155*4882a593Smuzhiyun			176 177 178 179 180 181 182 183
156*4882a593Smuzhiyun			184 185 186 187 188 189 190 191
157*4882a593Smuzhiyun			192 193 194 195 196 197 198 199
158*4882a593Smuzhiyun			200 201 202 203 204 205 206 207
159*4882a593Smuzhiyun			208 209 210 211 212 213 214 215
160*4882a593Smuzhiyun			216 217 218 219 220 221 222 223
161*4882a593Smuzhiyun			224 225 226 227 228 229 230 231
162*4882a593Smuzhiyun			232 233 234 235 236 237 238 239
163*4882a593Smuzhiyun			240 241 242 243 244 245 246 247
164*4882a593Smuzhiyun			248 249 250 251 252 253 254 255
165*4882a593Smuzhiyun		>;
166*4882a593Smuzhiyun		default-brightness-level = <200>;
167*4882a593Smuzhiyun	};
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun	bt-sound {
170*4882a593Smuzhiyun		compatible = "simple-audio-card";
171*4882a593Smuzhiyun		simple-audio-card,format = "dsp_b";
172*4882a593Smuzhiyun		simple-audio-card,bitclock-inversion = <1>;
173*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <256>;
174*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,bt";
175*4882a593Smuzhiyun		#simple-audio-card,bitclock-master = <&sound2_master>;
176*4882a593Smuzhiyun		#simple-audio-card,frame-master = <&sound2_master>;
177*4882a593Smuzhiyun		simple-audio-card,cpu {
178*4882a593Smuzhiyun			sound-dai = <&i2s3_2ch>;
179*4882a593Smuzhiyun		};
180*4882a593Smuzhiyun		sound2_master:simple-audio-card,codec {
181*4882a593Smuzhiyun			#sound-dai-cells = <0>;
182*4882a593Smuzhiyun			sound-dai = <&bt_sco>;
183*4882a593Smuzhiyun		};
184*4882a593Smuzhiyun	};
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun	bt_sco: bt-sco {
187*4882a593Smuzhiyun		compatible = "delta,dfbmcs320";
188*4882a593Smuzhiyun		#sound-dai-cells = <0>;
189*4882a593Smuzhiyun		status = "okay";
190*4882a593Smuzhiyun	};
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun	dc_12v: dc-12v {
193*4882a593Smuzhiyun		compatible = "regulator-fixed";
194*4882a593Smuzhiyun		regulator-name = "dc_12v";
195*4882a593Smuzhiyun		regulator-always-on;
196*4882a593Smuzhiyun		regulator-boot-on;
197*4882a593Smuzhiyun		regulator-min-microvolt = <12000000>;
198*4882a593Smuzhiyun		regulator-max-microvolt = <12000000>;
199*4882a593Smuzhiyun	};
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun	hdmi_sound: hdmi-sound {
202*4882a593Smuzhiyun		compatible = "simple-audio-card";
203*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
204*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <128>;
205*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,hdmi";
206*4882a593Smuzhiyun		status = "disabled";
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun		simple-audio-card,cpu {
209*4882a593Smuzhiyun				sound-dai = <&i2s0_8ch>;
210*4882a593Smuzhiyun		};
211*4882a593Smuzhiyun		simple-audio-card,codec {
212*4882a593Smuzhiyun				sound-dai = <&hdmi>;
213*4882a593Smuzhiyun		};
214*4882a593Smuzhiyun	};
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun	leds: leds {
217*4882a593Smuzhiyun		compatible = "gpio-leds";
218*4882a593Smuzhiyun		work_led: work {
219*4882a593Smuzhiyun			gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
220*4882a593Smuzhiyun			linux,default-trigger = "heartbeat";
221*4882a593Smuzhiyun		};
222*4882a593Smuzhiyun	};
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun	pdmics: dummy-codec {
225*4882a593Smuzhiyun		status = "disabled";
226*4882a593Smuzhiyun		compatible = "rockchip,dummy-codec";
227*4882a593Smuzhiyun		#sound-dai-cells = <0>;
228*4882a593Smuzhiyun	};
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun	pdm_mic_array: pdm-mic-array {
231*4882a593Smuzhiyun		status = "disabled";
232*4882a593Smuzhiyun		compatible = "simple-audio-card";
233*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,pdm-mic-array";
234*4882a593Smuzhiyun		simple-audio-card,cpu {
235*4882a593Smuzhiyun			sound-dai = <&pdm>;
236*4882a593Smuzhiyun		};
237*4882a593Smuzhiyun		simple-audio-card,codec {
238*4882a593Smuzhiyun			sound-dai = <&pdmics>;
239*4882a593Smuzhiyun		};
240*4882a593Smuzhiyun	};
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun	rk809_sound: rk809-sound {
243*4882a593Smuzhiyun		status = "okay";
244*4882a593Smuzhiyun		compatible = "simple-audio-card";
245*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
246*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,rk809-codec";
247*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <256>;
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun		simple-audio-card,cpu {
250*4882a593Smuzhiyun			sound-dai = <&i2s1_8ch>;
251*4882a593Smuzhiyun		};
252*4882a593Smuzhiyun		simple-audio-card,codec {
253*4882a593Smuzhiyun			sound-dai = <&rk809_codec>;
254*4882a593Smuzhiyun		};
255*4882a593Smuzhiyun	};
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun	sdio_pwrseq: sdio-pwrseq {
258*4882a593Smuzhiyun		compatible = "mmc-pwrseq-simple";
259*4882a593Smuzhiyun		clocks = <&rk809 1>;
260*4882a593Smuzhiyun		clock-names = "ext_clock";
261*4882a593Smuzhiyun		pinctrl-names = "default";
262*4882a593Smuzhiyun		pinctrl-0 = <&wifi_enable_h>;
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun		/*
265*4882a593Smuzhiyun		 * On the module itself this is one of these (depending
266*4882a593Smuzhiyun		 * on the actual card populated):
267*4882a593Smuzhiyun		 * - SDIO_RESET_L_WL_REG_ON
268*4882a593Smuzhiyun		 * - PDN (power down when low)
269*4882a593Smuzhiyun		 */
270*4882a593Smuzhiyun		post-power-on-delay-ms = <200>;
271*4882a593Smuzhiyun		reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
272*4882a593Smuzhiyun	};
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun	spdif-sound {
275*4882a593Smuzhiyun		status = "okay";
276*4882a593Smuzhiyun		compatible = "simple-audio-card";
277*4882a593Smuzhiyun		simple-audio-card,name = "ROCKCHIP,SPDIF";
278*4882a593Smuzhiyun		simple-audio-card,cpu {
279*4882a593Smuzhiyun				sound-dai = <&spdif_8ch>;
280*4882a593Smuzhiyun		};
281*4882a593Smuzhiyun		simple-audio-card,codec {
282*4882a593Smuzhiyun				sound-dai = <&spdif_out>;
283*4882a593Smuzhiyun		};
284*4882a593Smuzhiyun	};
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun	spdif_out: spdif-out {
287*4882a593Smuzhiyun			status = "okay";
288*4882a593Smuzhiyun			compatible = "linux,spdif-dit";
289*4882a593Smuzhiyun			#sound-dai-cells = <0>;
290*4882a593Smuzhiyun	};
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun	test-power {
293*4882a593Smuzhiyun		status = "okay";
294*4882a593Smuzhiyun	};
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun	vad_sound: vad-sound {
297*4882a593Smuzhiyun		status = "disabled";
298*4882a593Smuzhiyun		compatible = "rockchip,multicodecs-card";
299*4882a593Smuzhiyun		rockchip,card-name = "rockchip,rk3568-vad";
300*4882a593Smuzhiyun		rockchip,cpu = <&i2s1_8ch>;
301*4882a593Smuzhiyun		rockchip,codec = <&rk809_codec>, <&vad>;
302*4882a593Smuzhiyun	};
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun	vcc3v3_sys: vcc3v3-sys {
305*4882a593Smuzhiyun		compatible = "regulator-fixed";
306*4882a593Smuzhiyun		regulator-name = "vcc3v3_sys";
307*4882a593Smuzhiyun		regulator-always-on;
308*4882a593Smuzhiyun		regulator-boot-on;
309*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
310*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
311*4882a593Smuzhiyun		vin-supply = <&dc_12v>;
312*4882a593Smuzhiyun	};
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun	vcc5v0_sys: vcc5v0-sys {
315*4882a593Smuzhiyun		compatible = "regulator-fixed";
316*4882a593Smuzhiyun		regulator-name = "vcc5v0_sys";
317*4882a593Smuzhiyun		regulator-always-on;
318*4882a593Smuzhiyun		regulator-boot-on;
319*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
320*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
321*4882a593Smuzhiyun		vin-supply = <&dc_12v>;
322*4882a593Smuzhiyun	};
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun	vcc5v0_host: vcc5v0-host-regulator {
325*4882a593Smuzhiyun		compatible = "regulator-fixed";
326*4882a593Smuzhiyun		enable-active-high;
327*4882a593Smuzhiyun		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
328*4882a593Smuzhiyun		pinctrl-names = "default";
329*4882a593Smuzhiyun		pinctrl-0 = <&vcc5v0_host_en>;
330*4882a593Smuzhiyun		regulator-name = "vcc5v0_host";
331*4882a593Smuzhiyun		regulator-always-on;
332*4882a593Smuzhiyun	};
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun	vcc5v0_otg: vcc5v0-otg-regulator {
335*4882a593Smuzhiyun		compatible = "regulator-fixed";
336*4882a593Smuzhiyun		enable-active-high;
337*4882a593Smuzhiyun		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
338*4882a593Smuzhiyun		pinctrl-names = "default";
339*4882a593Smuzhiyun		pinctrl-0 = <&vcc5v0_otg_en>;
340*4882a593Smuzhiyun		regulator-name = "vcc5v0_otg";
341*4882a593Smuzhiyun	};
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun	vcc3v3_lcd0_n: vcc3v3-lcd0-n {
344*4882a593Smuzhiyun		compatible = "regulator-fixed";
345*4882a593Smuzhiyun		regulator-name = "vcc3v3_lcd0_n";
346*4882a593Smuzhiyun		regulator-boot-on;
347*4882a593Smuzhiyun		regulator-state-mem {
348*4882a593Smuzhiyun			regulator-off-in-suspend;
349*4882a593Smuzhiyun		};
350*4882a593Smuzhiyun	};
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun	vcc3v3_lcd1_n: vcc3v3-lcd1-n {
353*4882a593Smuzhiyun		compatible = "regulator-fixed";
354*4882a593Smuzhiyun		regulator-name = "vcc3v3_lcd1_n";
355*4882a593Smuzhiyun		regulator-boot-on;
356*4882a593Smuzhiyun		regulator-state-mem {
357*4882a593Smuzhiyun			regulator-off-in-suspend;
358*4882a593Smuzhiyun		};
359*4882a593Smuzhiyun	};
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun	wireless_wlan: wireless-wlan {
362*4882a593Smuzhiyun		compatible = "wlan-platdata";
363*4882a593Smuzhiyun		rockchip,grf = <&grf>;
364*4882a593Smuzhiyun		wifi_chip_type = "ap6398s";
365*4882a593Smuzhiyun		status = "okay";
366*4882a593Smuzhiyun	};
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun	wireless_bluetooth: wireless-bluetooth {
369*4882a593Smuzhiyun		compatible = "bluetooth-platdata";
370*4882a593Smuzhiyun		clocks = <&rk809 1>;
371*4882a593Smuzhiyun		clock-names = "ext_clock";
372*4882a593Smuzhiyun		//wifi-bt-power-toggle;
373*4882a593Smuzhiyun		uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
374*4882a593Smuzhiyun		pinctrl-names = "default", "rts_gpio";
375*4882a593Smuzhiyun		pinctrl-0 = <&uart8m0_rtsn>;
376*4882a593Smuzhiyun		pinctrl-1 = <&uart8_pin>;
377*4882a593Smuzhiyun		BT,reset_gpio    = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>;
378*4882a593Smuzhiyun		BT,wake_gpio     = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
379*4882a593Smuzhiyun		BT,wake_host_irq = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
380*4882a593Smuzhiyun		status = "okay";
381*4882a593Smuzhiyun	};
382*4882a593Smuzhiyun};
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun&bus_npu {
385*4882a593Smuzhiyun	bus-supply = <&vdd_logic>;
386*4882a593Smuzhiyun	pvtm-supply = <&vdd_cpu>;
387*4882a593Smuzhiyun	status = "okay";
388*4882a593Smuzhiyun};
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun&can0 {
391*4882a593Smuzhiyun	assigned-clocks = <&cru CLK_CAN0>;
392*4882a593Smuzhiyun	assigned-clock-rates = <150000000>;
393*4882a593Smuzhiyun	pinctrl-names = "default";
394*4882a593Smuzhiyun	pinctrl-0 = <&can0m1_pins>;
395*4882a593Smuzhiyun	status = "disabled";
396*4882a593Smuzhiyun};
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun&can1 {
399*4882a593Smuzhiyun	assigned-clocks = <&cru CLK_CAN1>;
400*4882a593Smuzhiyun	assigned-clock-rates = <150000000>;
401*4882a593Smuzhiyun	pinctrl-names = "default";
402*4882a593Smuzhiyun	pinctrl-0 = <&can1m1_pins>;
403*4882a593Smuzhiyun	status = "disabled";
404*4882a593Smuzhiyun};
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun&can2 {
407*4882a593Smuzhiyun	assigned-clocks = <&cru CLK_CAN2>;
408*4882a593Smuzhiyun	assigned-clock-rates = <150000000>;
409*4882a593Smuzhiyun	pinctrl-names = "default";
410*4882a593Smuzhiyun	pinctrl-0 = <&can2m1_pins>;
411*4882a593Smuzhiyun	status = "disabled";
412*4882a593Smuzhiyun};
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun&cpu0 {
415*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu>;
416*4882a593Smuzhiyun};
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun&dfi {
419*4882a593Smuzhiyun	status = "okay";
420*4882a593Smuzhiyun};
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun&dmc {
423*4882a593Smuzhiyun	center-supply = <&vdd_logic>;
424*4882a593Smuzhiyun	status = "okay";
425*4882a593Smuzhiyun};
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun&dsi0 {
428*4882a593Smuzhiyun	status = "disabled";
429*4882a593Smuzhiyun	//rockchip,lane-rate = <1000>;
430*4882a593Smuzhiyun	dsi0_panel: panel@0 {
431*4882a593Smuzhiyun		status = "okay";
432*4882a593Smuzhiyun		compatible = "simple-panel-dsi";
433*4882a593Smuzhiyun		reg = <0>;
434*4882a593Smuzhiyun		backlight = <&backlight>;
435*4882a593Smuzhiyun		reset-delay-ms = <60>;
436*4882a593Smuzhiyun		enable-delay-ms = <60>;
437*4882a593Smuzhiyun		prepare-delay-ms = <60>;
438*4882a593Smuzhiyun		unprepare-delay-ms = <60>;
439*4882a593Smuzhiyun		disable-delay-ms = <60>;
440*4882a593Smuzhiyun		dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
441*4882a593Smuzhiyun			MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
442*4882a593Smuzhiyun		dsi,format = <MIPI_DSI_FMT_RGB888>;
443*4882a593Smuzhiyun		dsi,lanes  = <4>;
444*4882a593Smuzhiyun		panel-init-sequence = [
445*4882a593Smuzhiyun			23 00 02 FE 21
446*4882a593Smuzhiyun			23 00 02 04 00
447*4882a593Smuzhiyun			23 00 02 00 64
448*4882a593Smuzhiyun			23 00 02 2A 00
449*4882a593Smuzhiyun			23 00 02 26 64
450*4882a593Smuzhiyun			23 00 02 54 00
451*4882a593Smuzhiyun			23 00 02 50 64
452*4882a593Smuzhiyun			23 00 02 7B 00
453*4882a593Smuzhiyun			23 00 02 77 64
454*4882a593Smuzhiyun			23 00 02 A2 00
455*4882a593Smuzhiyun			23 00 02 9D 64
456*4882a593Smuzhiyun			23 00 02 C9 00
457*4882a593Smuzhiyun			23 00 02 C5 64
458*4882a593Smuzhiyun			23 00 02 01 71
459*4882a593Smuzhiyun			23 00 02 27 71
460*4882a593Smuzhiyun			23 00 02 51 71
461*4882a593Smuzhiyun			23 00 02 78 71
462*4882a593Smuzhiyun			23 00 02 9E 71
463*4882a593Smuzhiyun			23 00 02 C6 71
464*4882a593Smuzhiyun			23 00 02 02 89
465*4882a593Smuzhiyun			23 00 02 28 89
466*4882a593Smuzhiyun			23 00 02 52 89
467*4882a593Smuzhiyun			23 00 02 79 89
468*4882a593Smuzhiyun			23 00 02 9F 89
469*4882a593Smuzhiyun			23 00 02 C7 89
470*4882a593Smuzhiyun			23 00 02 03 9E
471*4882a593Smuzhiyun			23 00 02 29 9E
472*4882a593Smuzhiyun			23 00 02 53 9E
473*4882a593Smuzhiyun			23 00 02 7A 9E
474*4882a593Smuzhiyun			23 00 02 A0 9E
475*4882a593Smuzhiyun			23 00 02 C8 9E
476*4882a593Smuzhiyun			23 00 02 09 00
477*4882a593Smuzhiyun			23 00 02 05 B0
478*4882a593Smuzhiyun			23 00 02 31 00
479*4882a593Smuzhiyun			23 00 02 2B B0
480*4882a593Smuzhiyun			23 00 02 5A 00
481*4882a593Smuzhiyun			23 00 02 55 B0
482*4882a593Smuzhiyun			23 00 02 80 00
483*4882a593Smuzhiyun			23 00 02 7C B0
484*4882a593Smuzhiyun			23 00 02 A7 00
485*4882a593Smuzhiyun			23 00 02 A3 B0
486*4882a593Smuzhiyun			23 00 02 CE 00
487*4882a593Smuzhiyun			23 00 02 CA B0
488*4882a593Smuzhiyun			23 00 02 06 C0
489*4882a593Smuzhiyun			23 00 02 2D C0
490*4882a593Smuzhiyun			23 00 02 56 C0
491*4882a593Smuzhiyun			23 00 02 7D C0
492*4882a593Smuzhiyun			23 00 02 A4 C0
493*4882a593Smuzhiyun			23 00 02 CB C0
494*4882a593Smuzhiyun			23 00 02 07 CF
495*4882a593Smuzhiyun			23 00 02 2F CF
496*4882a593Smuzhiyun			23 00 02 58 CF
497*4882a593Smuzhiyun			23 00 02 7E CF
498*4882a593Smuzhiyun			23 00 02 A5 CF
499*4882a593Smuzhiyun			23 00 02 CC CF
500*4882a593Smuzhiyun			23 00 02 08 DD
501*4882a593Smuzhiyun			23 00 02 30 DD
502*4882a593Smuzhiyun			23 00 02 59 DD
503*4882a593Smuzhiyun			23 00 02 7F DD
504*4882a593Smuzhiyun			23 00 02 A6 DD
505*4882a593Smuzhiyun			23 00 02 CD DD
506*4882a593Smuzhiyun			23 00 02 0E 15
507*4882a593Smuzhiyun			23 00 02 0A E9
508*4882a593Smuzhiyun			23 00 02 36 15
509*4882a593Smuzhiyun			23 00 02 32 E9
510*4882a593Smuzhiyun			23 00 02 5F 15
511*4882a593Smuzhiyun			23 00 02 5B E9
512*4882a593Smuzhiyun			23 00 02 85 15
513*4882a593Smuzhiyun			23 00 02 81 E9
514*4882a593Smuzhiyun			23 00 02 AD 15
515*4882a593Smuzhiyun			23 00 02 A9 E9
516*4882a593Smuzhiyun			23 00 02 D3 15
517*4882a593Smuzhiyun			23 00 02 CF E9
518*4882a593Smuzhiyun			23 00 02 0B 14
519*4882a593Smuzhiyun			23 00 02 33 14
520*4882a593Smuzhiyun			23 00 02 5C 14
521*4882a593Smuzhiyun			23 00 02 82 14
522*4882a593Smuzhiyun			23 00 02 AA 14
523*4882a593Smuzhiyun			23 00 02 D0 14
524*4882a593Smuzhiyun			23 00 02 0C 36
525*4882a593Smuzhiyun			23 00 02 34 36
526*4882a593Smuzhiyun			23 00 02 5D 36
527*4882a593Smuzhiyun			23 00 02 83 36
528*4882a593Smuzhiyun			23 00 02 AB 36
529*4882a593Smuzhiyun			23 00 02 D1 36
530*4882a593Smuzhiyun			23 00 02 0D 6B
531*4882a593Smuzhiyun			23 00 02 35 6B
532*4882a593Smuzhiyun			23 00 02 5E 6B
533*4882a593Smuzhiyun			23 00 02 84 6B
534*4882a593Smuzhiyun			23 00 02 AC 6B
535*4882a593Smuzhiyun			23 00 02 D2 6B
536*4882a593Smuzhiyun			23 00 02 13 5A
537*4882a593Smuzhiyun			23 00 02 0F 94
538*4882a593Smuzhiyun			23 00 02 3B 5A
539*4882a593Smuzhiyun			23 00 02 37 94
540*4882a593Smuzhiyun			23 00 02 64 5A
541*4882a593Smuzhiyun			23 00 02 60 94
542*4882a593Smuzhiyun			23 00 02 8A 5A
543*4882a593Smuzhiyun			23 00 02 86 94
544*4882a593Smuzhiyun			23 00 02 B2 5A
545*4882a593Smuzhiyun			23 00 02 AE 94
546*4882a593Smuzhiyun			23 00 02 D8 5A
547*4882a593Smuzhiyun			23 00 02 D4 94
548*4882a593Smuzhiyun			23 00 02 10 D1
549*4882a593Smuzhiyun			23 00 02 38 D1
550*4882a593Smuzhiyun			23 00 02 61 D1
551*4882a593Smuzhiyun			23 00 02 87 D1
552*4882a593Smuzhiyun			23 00 02 AF D1
553*4882a593Smuzhiyun			23 00 02 D5 D1
554*4882a593Smuzhiyun			23 00 02 11 04
555*4882a593Smuzhiyun			23 00 02 39 04
556*4882a593Smuzhiyun			23 00 02 62 04
557*4882a593Smuzhiyun			23 00 02 88 04
558*4882a593Smuzhiyun			23 00 02 B0 04
559*4882a593Smuzhiyun			23 00 02 D6 04
560*4882a593Smuzhiyun			23 00 02 12 05
561*4882a593Smuzhiyun			23 00 02 3A 05
562*4882a593Smuzhiyun			23 00 02 63 05
563*4882a593Smuzhiyun			23 00 02 89 05
564*4882a593Smuzhiyun			23 00 02 B1 05
565*4882a593Smuzhiyun			23 00 02 D7 05
566*4882a593Smuzhiyun			23 00 02 18 AA
567*4882a593Smuzhiyun			23 00 02 14 36
568*4882a593Smuzhiyun			23 00 02 42 AA
569*4882a593Smuzhiyun			23 00 02 3D 36
570*4882a593Smuzhiyun			23 00 02 69 AA
571*4882a593Smuzhiyun			23 00 02 65 36
572*4882a593Smuzhiyun			23 00 02 8F AA
573*4882a593Smuzhiyun			23 00 02 8B 36
574*4882a593Smuzhiyun			23 00 02 B7 AA
575*4882a593Smuzhiyun			23 00 02 B3 36
576*4882a593Smuzhiyun			23 00 02 DD AA
577*4882a593Smuzhiyun			23 00 02 D9 36
578*4882a593Smuzhiyun			23 00 02 15 74
579*4882a593Smuzhiyun			23 00 02 3F 74
580*4882a593Smuzhiyun			23 00 02 66 74
581*4882a593Smuzhiyun			23 00 02 8C 74
582*4882a593Smuzhiyun			23 00 02 B4 74
583*4882a593Smuzhiyun			23 00 02 DA 74
584*4882a593Smuzhiyun			23 00 02 16 9F
585*4882a593Smuzhiyun			23 00 02 40 9F
586*4882a593Smuzhiyun			23 00 02 67 9F
587*4882a593Smuzhiyun			23 00 02 8D 9F
588*4882a593Smuzhiyun			23 00 02 B5 9F
589*4882a593Smuzhiyun			23 00 02 DB 9F
590*4882a593Smuzhiyun			23 00 02 17 DC
591*4882a593Smuzhiyun			23 00 02 41 DC
592*4882a593Smuzhiyun			23 00 02 68 DC
593*4882a593Smuzhiyun			23 00 02 8E DC
594*4882a593Smuzhiyun			23 00 02 B6 DC
595*4882a593Smuzhiyun			23 00 02 DC DC
596*4882a593Smuzhiyun			23 00 02 1D FF
597*4882a593Smuzhiyun			23 00 02 19 03
598*4882a593Smuzhiyun			23 00 02 47 FF
599*4882a593Smuzhiyun			23 00 02 43 03
600*4882a593Smuzhiyun			23 00 02 6E FF
601*4882a593Smuzhiyun			23 00 02 6A 03
602*4882a593Smuzhiyun			23 00 02 94 FF
603*4882a593Smuzhiyun			23 00 02 90 03
604*4882a593Smuzhiyun			23 00 02 BC FF
605*4882a593Smuzhiyun			23 00 02 B8 03
606*4882a593Smuzhiyun			23 00 02 E2 FF
607*4882a593Smuzhiyun			23 00 02 DE 03
608*4882a593Smuzhiyun			23 00 02 1A 35
609*4882a593Smuzhiyun			23 00 02 44 35
610*4882a593Smuzhiyun			23 00 02 6B 35
611*4882a593Smuzhiyun			23 00 02 91 35
612*4882a593Smuzhiyun			23 00 02 B9 35
613*4882a593Smuzhiyun			23 00 02 DF 35
614*4882a593Smuzhiyun			23 00 02 1B 45
615*4882a593Smuzhiyun			23 00 02 45 45
616*4882a593Smuzhiyun			23 00 02 6C 45
617*4882a593Smuzhiyun			23 00 02 92 45
618*4882a593Smuzhiyun			23 00 02 BA 45
619*4882a593Smuzhiyun			23 00 02 E0 45
620*4882a593Smuzhiyun			23 00 02 1C 55
621*4882a593Smuzhiyun			23 00 02 46 55
622*4882a593Smuzhiyun			23 00 02 6D 55
623*4882a593Smuzhiyun			23 00 02 93 55
624*4882a593Smuzhiyun			23 00 02 BB 55
625*4882a593Smuzhiyun			23 00 02 E1 55
626*4882a593Smuzhiyun			23 00 02 22 FF
627*4882a593Smuzhiyun			23 00 02 1E 68
628*4882a593Smuzhiyun			23 00 02 4C FF
629*4882a593Smuzhiyun			23 00 02 48 68
630*4882a593Smuzhiyun			23 00 02 73 FF
631*4882a593Smuzhiyun			23 00 02 6F 68
632*4882a593Smuzhiyun			23 00 02 99 FF
633*4882a593Smuzhiyun			23 00 02 95 68
634*4882a593Smuzhiyun			23 00 02 C1 FF
635*4882a593Smuzhiyun			23 00 02 BD 68
636*4882a593Smuzhiyun			23 00 02 E7 FF
637*4882a593Smuzhiyun			23 00 02 E3 68
638*4882a593Smuzhiyun			23 00 02 1F 7E
639*4882a593Smuzhiyun			23 00 02 49 7E
640*4882a593Smuzhiyun			23 00 02 70 7E
641*4882a593Smuzhiyun			23 00 02 96 7E
642*4882a593Smuzhiyun			23 00 02 BE 7E
643*4882a593Smuzhiyun			23 00 02 E4 7E
644*4882a593Smuzhiyun			23 00 02 20 97
645*4882a593Smuzhiyun			23 00 02 4A 97
646*4882a593Smuzhiyun			23 00 02 71 97
647*4882a593Smuzhiyun			23 00 02 97 97
648*4882a593Smuzhiyun			23 00 02 BF 97
649*4882a593Smuzhiyun			23 00 02 E5 97
650*4882a593Smuzhiyun			23 00 02 21 B5
651*4882a593Smuzhiyun			23 00 02 4B B5
652*4882a593Smuzhiyun			23 00 02 72 B5
653*4882a593Smuzhiyun			23 00 02 98 B5
654*4882a593Smuzhiyun			23 00 02 C0 B5
655*4882a593Smuzhiyun			23 00 02 E6 B5
656*4882a593Smuzhiyun			23 00 02 25 F0
657*4882a593Smuzhiyun			23 00 02 23 E8
658*4882a593Smuzhiyun			23 00 02 4F F0
659*4882a593Smuzhiyun			23 00 02 4D E8
660*4882a593Smuzhiyun			23 00 02 76 F0
661*4882a593Smuzhiyun			23 00 02 74 E8
662*4882a593Smuzhiyun			23 00 02 9C F0
663*4882a593Smuzhiyun			23 00 02 9A E8
664*4882a593Smuzhiyun			23 00 02 C4 F0
665*4882a593Smuzhiyun			23 00 02 C2 E8
666*4882a593Smuzhiyun			23 00 02 EA F0
667*4882a593Smuzhiyun			23 00 02 E8 E8
668*4882a593Smuzhiyun			23 00 02 24 FF
669*4882a593Smuzhiyun			23 00 02 4E FF
670*4882a593Smuzhiyun			23 00 02 75 FF
671*4882a593Smuzhiyun			23 00 02 9B FF
672*4882a593Smuzhiyun			23 00 02 C3 FF
673*4882a593Smuzhiyun			23 00 02 E9 FF
674*4882a593Smuzhiyun			23 00 02 FE 3D
675*4882a593Smuzhiyun			23 00 02 00 04
676*4882a593Smuzhiyun			23 00 02 FE 23
677*4882a593Smuzhiyun			23 00 02 08 82
678*4882a593Smuzhiyun			23 00 02 0A 00
679*4882a593Smuzhiyun			23 00 02 0B 00
680*4882a593Smuzhiyun			23 00 02 0C 01
681*4882a593Smuzhiyun			23 00 02 16 00
682*4882a593Smuzhiyun			23 00 02 18 02
683*4882a593Smuzhiyun			23 00 02 1B 04
684*4882a593Smuzhiyun			23 00 02 19 04
685*4882a593Smuzhiyun			23 00 02 1C 81
686*4882a593Smuzhiyun			23 00 02 1F 00
687*4882a593Smuzhiyun			23 00 02 20 03
688*4882a593Smuzhiyun			23 00 02 23 04
689*4882a593Smuzhiyun			23 00 02 21 01
690*4882a593Smuzhiyun			23 00 02 54 63
691*4882a593Smuzhiyun			23 00 02 55 54
692*4882a593Smuzhiyun			23 00 02 6E 45
693*4882a593Smuzhiyun			23 00 02 6D 36
694*4882a593Smuzhiyun			23 00 02 FE 3D
695*4882a593Smuzhiyun			23 00 02 55 78
696*4882a593Smuzhiyun			23 00 02 FE 20
697*4882a593Smuzhiyun			23 00 02 26 30
698*4882a593Smuzhiyun			23 00 02 FE 3D
699*4882a593Smuzhiyun			23 00 02 20 71
700*4882a593Smuzhiyun			23 00 02 50 8F
701*4882a593Smuzhiyun			23 00 02 51 8F
702*4882a593Smuzhiyun			23 00 02 FE 00
703*4882a593Smuzhiyun			23 00 02 35 00
704*4882a593Smuzhiyun			05 78 01 11
705*4882a593Smuzhiyun			05 1E 01 29
706*4882a593Smuzhiyun		];
707*4882a593Smuzhiyun
708*4882a593Smuzhiyun		panel-exit-sequence = [
709*4882a593Smuzhiyun			05 00 01 28
710*4882a593Smuzhiyun			05 00 01 10
711*4882a593Smuzhiyun		];
712*4882a593Smuzhiyun
713*4882a593Smuzhiyun		disp_timings0: display-timings {
714*4882a593Smuzhiyun			native-mode = <&dsi0_timing0>;
715*4882a593Smuzhiyun			dsi0_timing0: timing0 {
716*4882a593Smuzhiyun				clock-frequency = <132000000>;
717*4882a593Smuzhiyun				hactive = <1080>;
718*4882a593Smuzhiyun				vactive = <1920>;
719*4882a593Smuzhiyun				hfront-porch = <15>;
720*4882a593Smuzhiyun				hsync-len = <2>;
721*4882a593Smuzhiyun				hback-porch = <30>;
722*4882a593Smuzhiyun				vfront-porch = <15>;
723*4882a593Smuzhiyun				vsync-len = <2>;
724*4882a593Smuzhiyun				vback-porch = <15>;
725*4882a593Smuzhiyun				hsync-active = <0>;
726*4882a593Smuzhiyun				vsync-active = <0>;
727*4882a593Smuzhiyun				de-active = <0>;
728*4882a593Smuzhiyun				pixelclk-active = <1>;
729*4882a593Smuzhiyun			};
730*4882a593Smuzhiyun		};
731*4882a593Smuzhiyun
732*4882a593Smuzhiyun		ports {
733*4882a593Smuzhiyun			#address-cells = <1>;
734*4882a593Smuzhiyun			#size-cells = <0>;
735*4882a593Smuzhiyun
736*4882a593Smuzhiyun			port@0 {
737*4882a593Smuzhiyun				reg = <0>;
738*4882a593Smuzhiyun				panel_in_dsi: endpoint {
739*4882a593Smuzhiyun					remote-endpoint = <&dsi_out_panel>;
740*4882a593Smuzhiyun				};
741*4882a593Smuzhiyun			};
742*4882a593Smuzhiyun		};
743*4882a593Smuzhiyun	};
744*4882a593Smuzhiyun
745*4882a593Smuzhiyun	ports {
746*4882a593Smuzhiyun		#address-cells = <1>;
747*4882a593Smuzhiyun		#size-cells = <0>;
748*4882a593Smuzhiyun
749*4882a593Smuzhiyun		port@1 {
750*4882a593Smuzhiyun			reg = <1>;
751*4882a593Smuzhiyun			dsi_out_panel: endpoint {
752*4882a593Smuzhiyun				remote-endpoint = <&panel_in_dsi>;
753*4882a593Smuzhiyun			};
754*4882a593Smuzhiyun		};
755*4882a593Smuzhiyun	};
756*4882a593Smuzhiyun};
757*4882a593Smuzhiyun
758*4882a593Smuzhiyun&dsi1 {
759*4882a593Smuzhiyun	status = "disabled";
760*4882a593Smuzhiyun	//rockchip,lane-rate = <1000>;
761*4882a593Smuzhiyun	dsi1_panel: panel@0 {
762*4882a593Smuzhiyun		status = "okay";
763*4882a593Smuzhiyun		compatible = "simple-panel-dsi";
764*4882a593Smuzhiyun		reg = <0>;
765*4882a593Smuzhiyun		backlight = <&backlight1>;
766*4882a593Smuzhiyun		reset-delay-ms = <60>;
767*4882a593Smuzhiyun		enable-delay-ms = <60>;
768*4882a593Smuzhiyun		prepare-delay-ms = <60>;
769*4882a593Smuzhiyun		unprepare-delay-ms = <60>;
770*4882a593Smuzhiyun		disable-delay-ms = <60>;
771*4882a593Smuzhiyun		dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
772*4882a593Smuzhiyun			MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
773*4882a593Smuzhiyun		dsi,format = <MIPI_DSI_FMT_RGB888>;
774*4882a593Smuzhiyun		dsi,lanes  = <4>;
775*4882a593Smuzhiyun		panel-init-sequence = [
776*4882a593Smuzhiyun			23 00 02 FE 21
777*4882a593Smuzhiyun			23 00 02 04 00
778*4882a593Smuzhiyun			23 00 02 00 64
779*4882a593Smuzhiyun			23 00 02 2A 00
780*4882a593Smuzhiyun			23 00 02 26 64
781*4882a593Smuzhiyun			23 00 02 54 00
782*4882a593Smuzhiyun			23 00 02 50 64
783*4882a593Smuzhiyun			23 00 02 7B 00
784*4882a593Smuzhiyun			23 00 02 77 64
785*4882a593Smuzhiyun			23 00 02 A2 00
786*4882a593Smuzhiyun			23 00 02 9D 64
787*4882a593Smuzhiyun			23 00 02 C9 00
788*4882a593Smuzhiyun			23 00 02 C5 64
789*4882a593Smuzhiyun			23 00 02 01 71
790*4882a593Smuzhiyun			23 00 02 27 71
791*4882a593Smuzhiyun			23 00 02 51 71
792*4882a593Smuzhiyun			23 00 02 78 71
793*4882a593Smuzhiyun			23 00 02 9E 71
794*4882a593Smuzhiyun			23 00 02 C6 71
795*4882a593Smuzhiyun			23 00 02 02 89
796*4882a593Smuzhiyun			23 00 02 28 89
797*4882a593Smuzhiyun			23 00 02 52 89
798*4882a593Smuzhiyun			23 00 02 79 89
799*4882a593Smuzhiyun			23 00 02 9F 89
800*4882a593Smuzhiyun			23 00 02 C7 89
801*4882a593Smuzhiyun			23 00 02 03 9E
802*4882a593Smuzhiyun			23 00 02 29 9E
803*4882a593Smuzhiyun			23 00 02 53 9E
804*4882a593Smuzhiyun			23 00 02 7A 9E
805*4882a593Smuzhiyun			23 00 02 A0 9E
806*4882a593Smuzhiyun			23 00 02 C8 9E
807*4882a593Smuzhiyun			23 00 02 09 00
808*4882a593Smuzhiyun			23 00 02 05 B0
809*4882a593Smuzhiyun			23 00 02 31 00
810*4882a593Smuzhiyun			23 00 02 2B B0
811*4882a593Smuzhiyun			23 00 02 5A 00
812*4882a593Smuzhiyun			23 00 02 55 B0
813*4882a593Smuzhiyun			23 00 02 80 00
814*4882a593Smuzhiyun			23 00 02 7C B0
815*4882a593Smuzhiyun			23 00 02 A7 00
816*4882a593Smuzhiyun			23 00 02 A3 B0
817*4882a593Smuzhiyun			23 00 02 CE 00
818*4882a593Smuzhiyun			23 00 02 CA B0
819*4882a593Smuzhiyun			23 00 02 06 C0
820*4882a593Smuzhiyun			23 00 02 2D C0
821*4882a593Smuzhiyun			23 00 02 56 C0
822*4882a593Smuzhiyun			23 00 02 7D C0
823*4882a593Smuzhiyun			23 00 02 A4 C0
824*4882a593Smuzhiyun			23 00 02 CB C0
825*4882a593Smuzhiyun			23 00 02 07 CF
826*4882a593Smuzhiyun			23 00 02 2F CF
827*4882a593Smuzhiyun			23 00 02 58 CF
828*4882a593Smuzhiyun			23 00 02 7E CF
829*4882a593Smuzhiyun			23 00 02 A5 CF
830*4882a593Smuzhiyun			23 00 02 CC CF
831*4882a593Smuzhiyun			23 00 02 08 DD
832*4882a593Smuzhiyun			23 00 02 30 DD
833*4882a593Smuzhiyun			23 00 02 59 DD
834*4882a593Smuzhiyun			23 00 02 7F DD
835*4882a593Smuzhiyun			23 00 02 A6 DD
836*4882a593Smuzhiyun			23 00 02 CD DD
837*4882a593Smuzhiyun			23 00 02 0E 15
838*4882a593Smuzhiyun			23 00 02 0A E9
839*4882a593Smuzhiyun			23 00 02 36 15
840*4882a593Smuzhiyun			23 00 02 32 E9
841*4882a593Smuzhiyun			23 00 02 5F 15
842*4882a593Smuzhiyun			23 00 02 5B E9
843*4882a593Smuzhiyun			23 00 02 85 15
844*4882a593Smuzhiyun			23 00 02 81 E9
845*4882a593Smuzhiyun			23 00 02 AD 15
846*4882a593Smuzhiyun			23 00 02 A9 E9
847*4882a593Smuzhiyun			23 00 02 D3 15
848*4882a593Smuzhiyun			23 00 02 CF E9
849*4882a593Smuzhiyun			23 00 02 0B 14
850*4882a593Smuzhiyun			23 00 02 33 14
851*4882a593Smuzhiyun			23 00 02 5C 14
852*4882a593Smuzhiyun			23 00 02 82 14
853*4882a593Smuzhiyun			23 00 02 AA 14
854*4882a593Smuzhiyun			23 00 02 D0 14
855*4882a593Smuzhiyun			23 00 02 0C 36
856*4882a593Smuzhiyun			23 00 02 34 36
857*4882a593Smuzhiyun			23 00 02 5D 36
858*4882a593Smuzhiyun			23 00 02 83 36
859*4882a593Smuzhiyun			23 00 02 AB 36
860*4882a593Smuzhiyun			23 00 02 D1 36
861*4882a593Smuzhiyun			23 00 02 0D 6B
862*4882a593Smuzhiyun			23 00 02 35 6B
863*4882a593Smuzhiyun			23 00 02 5E 6B
864*4882a593Smuzhiyun			23 00 02 84 6B
865*4882a593Smuzhiyun			23 00 02 AC 6B
866*4882a593Smuzhiyun			23 00 02 D2 6B
867*4882a593Smuzhiyun			23 00 02 13 5A
868*4882a593Smuzhiyun			23 00 02 0F 94
869*4882a593Smuzhiyun			23 00 02 3B 5A
870*4882a593Smuzhiyun			23 00 02 37 94
871*4882a593Smuzhiyun			23 00 02 64 5A
872*4882a593Smuzhiyun			23 00 02 60 94
873*4882a593Smuzhiyun			23 00 02 8A 5A
874*4882a593Smuzhiyun			23 00 02 86 94
875*4882a593Smuzhiyun			23 00 02 B2 5A
876*4882a593Smuzhiyun			23 00 02 AE 94
877*4882a593Smuzhiyun			23 00 02 D8 5A
878*4882a593Smuzhiyun			23 00 02 D4 94
879*4882a593Smuzhiyun			23 00 02 10 D1
880*4882a593Smuzhiyun			23 00 02 38 D1
881*4882a593Smuzhiyun			23 00 02 61 D1
882*4882a593Smuzhiyun			23 00 02 87 D1
883*4882a593Smuzhiyun			23 00 02 AF D1
884*4882a593Smuzhiyun			23 00 02 D5 D1
885*4882a593Smuzhiyun			23 00 02 11 04
886*4882a593Smuzhiyun			23 00 02 39 04
887*4882a593Smuzhiyun			23 00 02 62 04
888*4882a593Smuzhiyun			23 00 02 88 04
889*4882a593Smuzhiyun			23 00 02 B0 04
890*4882a593Smuzhiyun			23 00 02 D6 04
891*4882a593Smuzhiyun			23 00 02 12 05
892*4882a593Smuzhiyun			23 00 02 3A 05
893*4882a593Smuzhiyun			23 00 02 63 05
894*4882a593Smuzhiyun			23 00 02 89 05
895*4882a593Smuzhiyun			23 00 02 B1 05
896*4882a593Smuzhiyun			23 00 02 D7 05
897*4882a593Smuzhiyun			23 00 02 18 AA
898*4882a593Smuzhiyun			23 00 02 14 36
899*4882a593Smuzhiyun			23 00 02 42 AA
900*4882a593Smuzhiyun			23 00 02 3D 36
901*4882a593Smuzhiyun			23 00 02 69 AA
902*4882a593Smuzhiyun			23 00 02 65 36
903*4882a593Smuzhiyun			23 00 02 8F AA
904*4882a593Smuzhiyun			23 00 02 8B 36
905*4882a593Smuzhiyun			23 00 02 B7 AA
906*4882a593Smuzhiyun			23 00 02 B3 36
907*4882a593Smuzhiyun			23 00 02 DD AA
908*4882a593Smuzhiyun			23 00 02 D9 36
909*4882a593Smuzhiyun			23 00 02 15 74
910*4882a593Smuzhiyun			23 00 02 3F 74
911*4882a593Smuzhiyun			23 00 02 66 74
912*4882a593Smuzhiyun			23 00 02 8C 74
913*4882a593Smuzhiyun			23 00 02 B4 74
914*4882a593Smuzhiyun			23 00 02 DA 74
915*4882a593Smuzhiyun			23 00 02 16 9F
916*4882a593Smuzhiyun			23 00 02 40 9F
917*4882a593Smuzhiyun			23 00 02 67 9F
918*4882a593Smuzhiyun			23 00 02 8D 9F
919*4882a593Smuzhiyun			23 00 02 B5 9F
920*4882a593Smuzhiyun			23 00 02 DB 9F
921*4882a593Smuzhiyun			23 00 02 17 DC
922*4882a593Smuzhiyun			23 00 02 41 DC
923*4882a593Smuzhiyun			23 00 02 68 DC
924*4882a593Smuzhiyun			23 00 02 8E DC
925*4882a593Smuzhiyun			23 00 02 B6 DC
926*4882a593Smuzhiyun			23 00 02 DC DC
927*4882a593Smuzhiyun			23 00 02 1D FF
928*4882a593Smuzhiyun			23 00 02 19 03
929*4882a593Smuzhiyun			23 00 02 47 FF
930*4882a593Smuzhiyun			23 00 02 43 03
931*4882a593Smuzhiyun			23 00 02 6E FF
932*4882a593Smuzhiyun			23 00 02 6A 03
933*4882a593Smuzhiyun			23 00 02 94 FF
934*4882a593Smuzhiyun			23 00 02 90 03
935*4882a593Smuzhiyun			23 00 02 BC FF
936*4882a593Smuzhiyun			23 00 02 B8 03
937*4882a593Smuzhiyun			23 00 02 E2 FF
938*4882a593Smuzhiyun			23 00 02 DE 03
939*4882a593Smuzhiyun			23 00 02 1A 35
940*4882a593Smuzhiyun			23 00 02 44 35
941*4882a593Smuzhiyun			23 00 02 6B 35
942*4882a593Smuzhiyun			23 00 02 91 35
943*4882a593Smuzhiyun			23 00 02 B9 35
944*4882a593Smuzhiyun			23 00 02 DF 35
945*4882a593Smuzhiyun			23 00 02 1B 45
946*4882a593Smuzhiyun			23 00 02 45 45
947*4882a593Smuzhiyun			23 00 02 6C 45
948*4882a593Smuzhiyun			23 00 02 92 45
949*4882a593Smuzhiyun			23 00 02 BA 45
950*4882a593Smuzhiyun			23 00 02 E0 45
951*4882a593Smuzhiyun			23 00 02 1C 55
952*4882a593Smuzhiyun			23 00 02 46 55
953*4882a593Smuzhiyun			23 00 02 6D 55
954*4882a593Smuzhiyun			23 00 02 93 55
955*4882a593Smuzhiyun			23 00 02 BB 55
956*4882a593Smuzhiyun			23 00 02 E1 55
957*4882a593Smuzhiyun			23 00 02 22 FF
958*4882a593Smuzhiyun			23 00 02 1E 68
959*4882a593Smuzhiyun			23 00 02 4C FF
960*4882a593Smuzhiyun			23 00 02 48 68
961*4882a593Smuzhiyun			23 00 02 73 FF
962*4882a593Smuzhiyun			23 00 02 6F 68
963*4882a593Smuzhiyun			23 00 02 99 FF
964*4882a593Smuzhiyun			23 00 02 95 68
965*4882a593Smuzhiyun			23 00 02 C1 FF
966*4882a593Smuzhiyun			23 00 02 BD 68
967*4882a593Smuzhiyun			23 00 02 E7 FF
968*4882a593Smuzhiyun			23 00 02 E3 68
969*4882a593Smuzhiyun			23 00 02 1F 7E
970*4882a593Smuzhiyun			23 00 02 49 7E
971*4882a593Smuzhiyun			23 00 02 70 7E
972*4882a593Smuzhiyun			23 00 02 96 7E
973*4882a593Smuzhiyun			23 00 02 BE 7E
974*4882a593Smuzhiyun			23 00 02 E4 7E
975*4882a593Smuzhiyun			23 00 02 20 97
976*4882a593Smuzhiyun			23 00 02 4A 97
977*4882a593Smuzhiyun			23 00 02 71 97
978*4882a593Smuzhiyun			23 00 02 97 97
979*4882a593Smuzhiyun			23 00 02 BF 97
980*4882a593Smuzhiyun			23 00 02 E5 97
981*4882a593Smuzhiyun			23 00 02 21 B5
982*4882a593Smuzhiyun			23 00 02 4B B5
983*4882a593Smuzhiyun			23 00 02 72 B5
984*4882a593Smuzhiyun			23 00 02 98 B5
985*4882a593Smuzhiyun			23 00 02 C0 B5
986*4882a593Smuzhiyun			23 00 02 E6 B5
987*4882a593Smuzhiyun			23 00 02 25 F0
988*4882a593Smuzhiyun			23 00 02 23 E8
989*4882a593Smuzhiyun			23 00 02 4F F0
990*4882a593Smuzhiyun			23 00 02 4D E8
991*4882a593Smuzhiyun			23 00 02 76 F0
992*4882a593Smuzhiyun			23 00 02 74 E8
993*4882a593Smuzhiyun			23 00 02 9C F0
994*4882a593Smuzhiyun			23 00 02 9A E8
995*4882a593Smuzhiyun			23 00 02 C4 F0
996*4882a593Smuzhiyun			23 00 02 C2 E8
997*4882a593Smuzhiyun			23 00 02 EA F0
998*4882a593Smuzhiyun			23 00 02 E8 E8
999*4882a593Smuzhiyun			23 00 02 24 FF
1000*4882a593Smuzhiyun			23 00 02 4E FF
1001*4882a593Smuzhiyun			23 00 02 75 FF
1002*4882a593Smuzhiyun			23 00 02 9B FF
1003*4882a593Smuzhiyun			23 00 02 C3 FF
1004*4882a593Smuzhiyun			23 00 02 E9 FF
1005*4882a593Smuzhiyun			23 00 02 FE 3D
1006*4882a593Smuzhiyun			23 00 02 00 04
1007*4882a593Smuzhiyun			23 00 02 FE 23
1008*4882a593Smuzhiyun			23 00 02 08 82
1009*4882a593Smuzhiyun			23 00 02 0A 00
1010*4882a593Smuzhiyun			23 00 02 0B 00
1011*4882a593Smuzhiyun			23 00 02 0C 01
1012*4882a593Smuzhiyun			23 00 02 16 00
1013*4882a593Smuzhiyun			23 00 02 18 02
1014*4882a593Smuzhiyun			23 00 02 1B 04
1015*4882a593Smuzhiyun			23 00 02 19 04
1016*4882a593Smuzhiyun			23 00 02 1C 81
1017*4882a593Smuzhiyun			23 00 02 1F 00
1018*4882a593Smuzhiyun			23 00 02 20 03
1019*4882a593Smuzhiyun			23 00 02 23 04
1020*4882a593Smuzhiyun			23 00 02 21 01
1021*4882a593Smuzhiyun			23 00 02 54 63
1022*4882a593Smuzhiyun			23 00 02 55 54
1023*4882a593Smuzhiyun			23 00 02 6E 45
1024*4882a593Smuzhiyun			23 00 02 6D 36
1025*4882a593Smuzhiyun			23 00 02 FE 3D
1026*4882a593Smuzhiyun			23 00 02 55 78
1027*4882a593Smuzhiyun			23 00 02 FE 20
1028*4882a593Smuzhiyun			23 00 02 26 30
1029*4882a593Smuzhiyun			23 00 02 FE 3D
1030*4882a593Smuzhiyun			23 00 02 20 71
1031*4882a593Smuzhiyun			23 00 02 50 8F
1032*4882a593Smuzhiyun			23 00 02 51 8F
1033*4882a593Smuzhiyun			23 00 02 FE 00
1034*4882a593Smuzhiyun			23 00 02 35 00
1035*4882a593Smuzhiyun			05 78 01 11
1036*4882a593Smuzhiyun			05 1E 01 29
1037*4882a593Smuzhiyun		];
1038*4882a593Smuzhiyun
1039*4882a593Smuzhiyun		panel-exit-sequence = [
1040*4882a593Smuzhiyun			05 00 01 28
1041*4882a593Smuzhiyun			05 00 01 10
1042*4882a593Smuzhiyun		];
1043*4882a593Smuzhiyun
1044*4882a593Smuzhiyun		disp_timings1: display-timings {
1045*4882a593Smuzhiyun			native-mode = <&dsi1_timing0>;
1046*4882a593Smuzhiyun			dsi1_timing0: timing0 {
1047*4882a593Smuzhiyun				clock-frequency = <132000000>;
1048*4882a593Smuzhiyun				hactive = <1080>;
1049*4882a593Smuzhiyun				vactive = <1920>;
1050*4882a593Smuzhiyun				hfront-porch = <15>;
1051*4882a593Smuzhiyun				hsync-len = <2>;
1052*4882a593Smuzhiyun				hback-porch = <30>;
1053*4882a593Smuzhiyun				vfront-porch = <15>;
1054*4882a593Smuzhiyun				vsync-len = <2>;
1055*4882a593Smuzhiyun				vback-porch = <15>;
1056*4882a593Smuzhiyun				hsync-active = <0>;
1057*4882a593Smuzhiyun				vsync-active = <0>;
1058*4882a593Smuzhiyun				de-active = <0>;
1059*4882a593Smuzhiyun				pixelclk-active = <1>;
1060*4882a593Smuzhiyun			};
1061*4882a593Smuzhiyun		};
1062*4882a593Smuzhiyun
1063*4882a593Smuzhiyun		ports {
1064*4882a593Smuzhiyun			#address-cells = <1>;
1065*4882a593Smuzhiyun			#size-cells = <0>;
1066*4882a593Smuzhiyun
1067*4882a593Smuzhiyun			port@0 {
1068*4882a593Smuzhiyun				reg = <0>;
1069*4882a593Smuzhiyun				panel_in_dsi1: endpoint {
1070*4882a593Smuzhiyun					remote-endpoint = <&dsi1_out_panel>;
1071*4882a593Smuzhiyun				};
1072*4882a593Smuzhiyun			};
1073*4882a593Smuzhiyun		};
1074*4882a593Smuzhiyun	};
1075*4882a593Smuzhiyun
1076*4882a593Smuzhiyun	ports {
1077*4882a593Smuzhiyun		#address-cells = <1>;
1078*4882a593Smuzhiyun		#size-cells = <0>;
1079*4882a593Smuzhiyun
1080*4882a593Smuzhiyun		port@1 {
1081*4882a593Smuzhiyun			reg = <1>;
1082*4882a593Smuzhiyun			dsi1_out_panel: endpoint {
1083*4882a593Smuzhiyun				remote-endpoint = <&panel_in_dsi1>;
1084*4882a593Smuzhiyun			};
1085*4882a593Smuzhiyun		};
1086*4882a593Smuzhiyun	};
1087*4882a593Smuzhiyun
1088*4882a593Smuzhiyun};
1089*4882a593Smuzhiyun
1090*4882a593Smuzhiyun&gpu {
1091*4882a593Smuzhiyun	mali-supply = <&vdd_gpu>;
1092*4882a593Smuzhiyun	status = "okay";
1093*4882a593Smuzhiyun};
1094*4882a593Smuzhiyun
1095*4882a593Smuzhiyun&hdmi {
1096*4882a593Smuzhiyun	status = "okay";
1097*4882a593Smuzhiyun	rockchip,phy-table =
1098*4882a593Smuzhiyun		<92812500  0x8009 0x0000 0x0270>,
1099*4882a593Smuzhiyun		<165000000 0x800b 0x0000 0x026d>,
1100*4882a593Smuzhiyun		<185625000 0x800b 0x0000 0x01ed>,
1101*4882a593Smuzhiyun		<297000000 0x800b 0x0000 0x01ad>,
1102*4882a593Smuzhiyun		<594000000 0x8029 0x0000 0x0088>,
1103*4882a593Smuzhiyun		<000000000 0x0000 0x0000 0x0000>;
1104*4882a593Smuzhiyun};
1105*4882a593Smuzhiyun
1106*4882a593Smuzhiyun&hdmi_in_vp0 {
1107*4882a593Smuzhiyun	status = "okay";
1108*4882a593Smuzhiyun};
1109*4882a593Smuzhiyun
1110*4882a593Smuzhiyun&hdmi_in_vp1 {
1111*4882a593Smuzhiyun	status = "disabled";
1112*4882a593Smuzhiyun};
1113*4882a593Smuzhiyun
1114*4882a593Smuzhiyun&hdmi_sound {
1115*4882a593Smuzhiyun	status = "okay";
1116*4882a593Smuzhiyun};
1117*4882a593Smuzhiyun
1118*4882a593Smuzhiyun&i2c0 {
1119*4882a593Smuzhiyun	status = "okay";
1120*4882a593Smuzhiyun	vdd_cpu: tcs4525@1c {
1121*4882a593Smuzhiyun		compatible = "tcs,tcs452x";
1122*4882a593Smuzhiyun		reg = <0x1c>;
1123*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
1124*4882a593Smuzhiyun		regulator-compatible = "fan53555-reg";
1125*4882a593Smuzhiyun		regulator-name = "vdd_cpu";
1126*4882a593Smuzhiyun		regulator-min-microvolt = <712500>;
1127*4882a593Smuzhiyun		regulator-max-microvolt = <1390000>;
1128*4882a593Smuzhiyun		regulator-init-microvolt = <900000>;
1129*4882a593Smuzhiyun		regulator-ramp-delay = <2300>;
1130*4882a593Smuzhiyun		fcs,suspend-voltage-selector = <1>;
1131*4882a593Smuzhiyun		regulator-boot-on;
1132*4882a593Smuzhiyun		regulator-always-on;
1133*4882a593Smuzhiyun		regulator-state-mem {
1134*4882a593Smuzhiyun			regulator-off-in-suspend;
1135*4882a593Smuzhiyun		};
1136*4882a593Smuzhiyun	};
1137*4882a593Smuzhiyun
1138*4882a593Smuzhiyun	rk809: pmic@20 {
1139*4882a593Smuzhiyun		compatible = "rockchip,rk809";
1140*4882a593Smuzhiyun		reg = <0x20>;
1141*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
1142*4882a593Smuzhiyun		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
1143*4882a593Smuzhiyun
1144*4882a593Smuzhiyun		pinctrl-names = "default", "pmic-sleep",
1145*4882a593Smuzhiyun				"pmic-power-off", "pmic-reset";
1146*4882a593Smuzhiyun		pinctrl-0 = <&pmic_int>;
1147*4882a593Smuzhiyun		pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
1148*4882a593Smuzhiyun		pinctrl-2 = <&soc_slppin_pin>, <&rk817_slppin_pwrdn>;
1149*4882a593Smuzhiyun		pinctrl-3 = <&soc_slppin_pin>, <&rk817_slppin_rst>;
1150*4882a593Smuzhiyun
1151*4882a593Smuzhiyun		rockchip,system-power-controller;
1152*4882a593Smuzhiyun		wakeup-source;
1153*4882a593Smuzhiyun		#clock-cells = <1>;
1154*4882a593Smuzhiyun		clock-output-names = "rk808-clkout1", "rk808-clkout2";
1155*4882a593Smuzhiyun		//fb-inner-reg-idxs = <2>;
1156*4882a593Smuzhiyun		/* 1: rst regs (default in codes), 0: rst the pmic */
1157*4882a593Smuzhiyun		pmic-reset-func = <0>;
1158*4882a593Smuzhiyun		/* not save the PMIC_POWER_EN register in uboot */
1159*4882a593Smuzhiyun		not-save-power-en = <1>;
1160*4882a593Smuzhiyun
1161*4882a593Smuzhiyun		vcc1-supply = <&vcc3v3_sys>;
1162*4882a593Smuzhiyun		vcc2-supply = <&vcc3v3_sys>;
1163*4882a593Smuzhiyun		vcc3-supply = <&vcc3v3_sys>;
1164*4882a593Smuzhiyun		vcc4-supply = <&vcc3v3_sys>;
1165*4882a593Smuzhiyun		vcc5-supply = <&vcc3v3_sys>;
1166*4882a593Smuzhiyun		vcc6-supply = <&vcc3v3_sys>;
1167*4882a593Smuzhiyun		vcc7-supply = <&vcc3v3_sys>;
1168*4882a593Smuzhiyun		vcc8-supply = <&vcc3v3_sys>;
1169*4882a593Smuzhiyun		vcc9-supply = <&vcc3v3_sys>;
1170*4882a593Smuzhiyun
1171*4882a593Smuzhiyun		pwrkey {
1172*4882a593Smuzhiyun			status = "okay";
1173*4882a593Smuzhiyun		};
1174*4882a593Smuzhiyun
1175*4882a593Smuzhiyun		pinctrl_rk8xx: pinctrl_rk8xx {
1176*4882a593Smuzhiyun			gpio-controller;
1177*4882a593Smuzhiyun			#gpio-cells = <2>;
1178*4882a593Smuzhiyun
1179*4882a593Smuzhiyun			rk817_slppin_null: rk817_slppin_null {
1180*4882a593Smuzhiyun				pins = "gpio_slp";
1181*4882a593Smuzhiyun				function = "pin_fun0";
1182*4882a593Smuzhiyun			};
1183*4882a593Smuzhiyun
1184*4882a593Smuzhiyun			rk817_slppin_slp: rk817_slppin_slp {
1185*4882a593Smuzhiyun				pins = "gpio_slp";
1186*4882a593Smuzhiyun				function = "pin_fun1";
1187*4882a593Smuzhiyun			};
1188*4882a593Smuzhiyun
1189*4882a593Smuzhiyun			rk817_slppin_pwrdn: rk817_slppin_pwrdn {
1190*4882a593Smuzhiyun				pins = "gpio_slp";
1191*4882a593Smuzhiyun				function = "pin_fun2";
1192*4882a593Smuzhiyun			};
1193*4882a593Smuzhiyun
1194*4882a593Smuzhiyun			rk817_slppin_rst: rk817_slppin_rst {
1195*4882a593Smuzhiyun				pins = "gpio_slp";
1196*4882a593Smuzhiyun				function = "pin_fun3";
1197*4882a593Smuzhiyun			};
1198*4882a593Smuzhiyun		};
1199*4882a593Smuzhiyun
1200*4882a593Smuzhiyun		regulators {
1201*4882a593Smuzhiyun			vdd_logic: DCDC_REG1 {
1202*4882a593Smuzhiyun				regulator-always-on;
1203*4882a593Smuzhiyun				regulator-boot-on;
1204*4882a593Smuzhiyun				regulator-min-microvolt = <500000>;
1205*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
1206*4882a593Smuzhiyun				regulator-init-microvolt = <900000>;
1207*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
1208*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
1209*4882a593Smuzhiyun				regulator-name = "vdd_logic";
1210*4882a593Smuzhiyun				regulator-state-mem {
1211*4882a593Smuzhiyun					regulator-off-in-suspend;
1212*4882a593Smuzhiyun				};
1213*4882a593Smuzhiyun			};
1214*4882a593Smuzhiyun
1215*4882a593Smuzhiyun			vdd_gpu: DCDC_REG2 {
1216*4882a593Smuzhiyun				regulator-always-on;
1217*4882a593Smuzhiyun				regulator-boot-on;
1218*4882a593Smuzhiyun				regulator-min-microvolt = <500000>;
1219*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
1220*4882a593Smuzhiyun				regulator-init-microvolt = <900000>;
1221*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
1222*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
1223*4882a593Smuzhiyun				regulator-name = "vdd_gpu";
1224*4882a593Smuzhiyun				regulator-state-mem {
1225*4882a593Smuzhiyun					regulator-off-in-suspend;
1226*4882a593Smuzhiyun				};
1227*4882a593Smuzhiyun			};
1228*4882a593Smuzhiyun
1229*4882a593Smuzhiyun			vcc_ddr: DCDC_REG3 {
1230*4882a593Smuzhiyun				regulator-always-on;
1231*4882a593Smuzhiyun				regulator-boot-on;
1232*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
1233*4882a593Smuzhiyun				regulator-name = "vcc_ddr";
1234*4882a593Smuzhiyun				regulator-state-mem {
1235*4882a593Smuzhiyun					regulator-on-in-suspend;
1236*4882a593Smuzhiyun				};
1237*4882a593Smuzhiyun			};
1238*4882a593Smuzhiyun
1239*4882a593Smuzhiyun			vdd_npu: DCDC_REG4 {
1240*4882a593Smuzhiyun				regulator-always-on;
1241*4882a593Smuzhiyun				regulator-boot-on;
1242*4882a593Smuzhiyun				regulator-min-microvolt = <500000>;
1243*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
1244*4882a593Smuzhiyun				regulator-init-microvolt = <900000>;
1245*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
1246*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
1247*4882a593Smuzhiyun				regulator-name = "vdd_npu";
1248*4882a593Smuzhiyun				regulator-state-mem {
1249*4882a593Smuzhiyun					regulator-off-in-suspend;
1250*4882a593Smuzhiyun				};
1251*4882a593Smuzhiyun			};
1252*4882a593Smuzhiyun
1253*4882a593Smuzhiyun			vdda0v9_image: LDO_REG1 {
1254*4882a593Smuzhiyun				regulator-boot-on;
1255*4882a593Smuzhiyun				regulator-always-on;
1256*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
1257*4882a593Smuzhiyun				regulator-max-microvolt = <900000>;
1258*4882a593Smuzhiyun				regulator-name = "vdda0v9_image";
1259*4882a593Smuzhiyun				regulator-state-mem {
1260*4882a593Smuzhiyun					regulator-off-in-suspend;
1261*4882a593Smuzhiyun				};
1262*4882a593Smuzhiyun			};
1263*4882a593Smuzhiyun
1264*4882a593Smuzhiyun			vdda_0v9: LDO_REG2 {
1265*4882a593Smuzhiyun				regulator-always-on;
1266*4882a593Smuzhiyun				regulator-boot-on;
1267*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
1268*4882a593Smuzhiyun				regulator-max-microvolt = <900000>;
1269*4882a593Smuzhiyun				regulator-name = "vdda_0v9";
1270*4882a593Smuzhiyun				regulator-state-mem {
1271*4882a593Smuzhiyun					regulator-off-in-suspend;
1272*4882a593Smuzhiyun				};
1273*4882a593Smuzhiyun			};
1274*4882a593Smuzhiyun
1275*4882a593Smuzhiyun			vdda0v9_pmu: LDO_REG3 {
1276*4882a593Smuzhiyun				regulator-always-on;
1277*4882a593Smuzhiyun				regulator-boot-on;
1278*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
1279*4882a593Smuzhiyun				regulator-max-microvolt = <900000>;
1280*4882a593Smuzhiyun				regulator-name = "vdda0v9_pmu";
1281*4882a593Smuzhiyun				regulator-state-mem {
1282*4882a593Smuzhiyun					regulator-on-in-suspend;
1283*4882a593Smuzhiyun					regulator-suspend-microvolt = <900000>;
1284*4882a593Smuzhiyun				};
1285*4882a593Smuzhiyun			};
1286*4882a593Smuzhiyun
1287*4882a593Smuzhiyun			vccio_acodec: LDO_REG4 {
1288*4882a593Smuzhiyun				regulator-always-on;
1289*4882a593Smuzhiyun				regulator-boot-on;
1290*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
1291*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
1292*4882a593Smuzhiyun				regulator-name = "vccio_acodec";
1293*4882a593Smuzhiyun				regulator-state-mem {
1294*4882a593Smuzhiyun					regulator-off-in-suspend;
1295*4882a593Smuzhiyun				};
1296*4882a593Smuzhiyun			};
1297*4882a593Smuzhiyun
1298*4882a593Smuzhiyun			vccio_sd: LDO_REG5 {
1299*4882a593Smuzhiyun				regulator-always-on;
1300*4882a593Smuzhiyun				regulator-boot-on;
1301*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
1302*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
1303*4882a593Smuzhiyun				regulator-name = "vccio_sd";
1304*4882a593Smuzhiyun				regulator-state-mem {
1305*4882a593Smuzhiyun					regulator-off-in-suspend;
1306*4882a593Smuzhiyun				};
1307*4882a593Smuzhiyun			};
1308*4882a593Smuzhiyun
1309*4882a593Smuzhiyun			vcc3v3_pmu: LDO_REG6 {
1310*4882a593Smuzhiyun				regulator-always-on;
1311*4882a593Smuzhiyun				regulator-boot-on;
1312*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
1313*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
1314*4882a593Smuzhiyun				regulator-name = "vcc3v3_pmu";
1315*4882a593Smuzhiyun				regulator-state-mem {
1316*4882a593Smuzhiyun					regulator-on-in-suspend;
1317*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
1318*4882a593Smuzhiyun				};
1319*4882a593Smuzhiyun			};
1320*4882a593Smuzhiyun
1321*4882a593Smuzhiyun			vcca_1v8: LDO_REG7 {
1322*4882a593Smuzhiyun				regulator-always-on;
1323*4882a593Smuzhiyun				regulator-boot-on;
1324*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
1325*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
1326*4882a593Smuzhiyun				regulator-name = "vcca_1v8";
1327*4882a593Smuzhiyun				regulator-state-mem {
1328*4882a593Smuzhiyun					regulator-off-in-suspend;
1329*4882a593Smuzhiyun				};
1330*4882a593Smuzhiyun			};
1331*4882a593Smuzhiyun
1332*4882a593Smuzhiyun			vcca1v8_pmu: LDO_REG8 {
1333*4882a593Smuzhiyun				regulator-always-on;
1334*4882a593Smuzhiyun				regulator-boot-on;
1335*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
1336*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
1337*4882a593Smuzhiyun				regulator-name = "vcca1v8_pmu";
1338*4882a593Smuzhiyun				regulator-state-mem {
1339*4882a593Smuzhiyun					regulator-on-in-suspend;
1340*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
1341*4882a593Smuzhiyun				};
1342*4882a593Smuzhiyun			};
1343*4882a593Smuzhiyun
1344*4882a593Smuzhiyun			vcca1v8_image: LDO_REG9 {
1345*4882a593Smuzhiyun				regulator-always-on;
1346*4882a593Smuzhiyun				regulator-boot-on;
1347*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
1348*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
1349*4882a593Smuzhiyun				regulator-name = "vcca1v8_image";
1350*4882a593Smuzhiyun				regulator-state-mem {
1351*4882a593Smuzhiyun					regulator-off-in-suspend;
1352*4882a593Smuzhiyun				};
1353*4882a593Smuzhiyun			};
1354*4882a593Smuzhiyun
1355*4882a593Smuzhiyun			vcc_1v8: DCDC_REG5 {
1356*4882a593Smuzhiyun				regulator-always-on;
1357*4882a593Smuzhiyun				regulator-boot-on;
1358*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
1359*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
1360*4882a593Smuzhiyun				regulator-name = "vcc_1v8";
1361*4882a593Smuzhiyun				regulator-state-mem {
1362*4882a593Smuzhiyun					regulator-off-in-suspend;
1363*4882a593Smuzhiyun				};
1364*4882a593Smuzhiyun			};
1365*4882a593Smuzhiyun
1366*4882a593Smuzhiyun			vcc_3v3: SWITCH_REG1 {
1367*4882a593Smuzhiyun				regulator-always-on;
1368*4882a593Smuzhiyun				regulator-boot-on;
1369*4882a593Smuzhiyun				regulator-name = "vcc_3v3";
1370*4882a593Smuzhiyun				regulator-state-mem {
1371*4882a593Smuzhiyun					regulator-off-in-suspend;
1372*4882a593Smuzhiyun				};
1373*4882a593Smuzhiyun			};
1374*4882a593Smuzhiyun
1375*4882a593Smuzhiyun			vcc3v3_sd: SWITCH_REG2 {
1376*4882a593Smuzhiyun				regulator-always-on;
1377*4882a593Smuzhiyun				regulator-boot-on;
1378*4882a593Smuzhiyun				regulator-name = "vcc3v3_sd";
1379*4882a593Smuzhiyun				regulator-state-mem {
1380*4882a593Smuzhiyun					regulator-off-in-suspend;
1381*4882a593Smuzhiyun				};
1382*4882a593Smuzhiyun			};
1383*4882a593Smuzhiyun		};
1384*4882a593Smuzhiyun
1385*4882a593Smuzhiyun		rk809_codec: codec {
1386*4882a593Smuzhiyun			#sound-dai-cells = <0>;
1387*4882a593Smuzhiyun			compatible = "rockchip,rk809-codec", "rockchip,rk817-codec";
1388*4882a593Smuzhiyun			clocks = <&cru I2S1_MCLKOUT>;
1389*4882a593Smuzhiyun			clock-names = "mclk";
1390*4882a593Smuzhiyun			assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>;
1391*4882a593Smuzhiyun			assigned-clock-rates = <12288000>;
1392*4882a593Smuzhiyun			assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>;
1393*4882a593Smuzhiyun			pinctrl-names = "default";
1394*4882a593Smuzhiyun			pinctrl-0 = <&i2s1m0_mclk>;
1395*4882a593Smuzhiyun			hp-volume = <20>;
1396*4882a593Smuzhiyun			spk-volume = <3>;
1397*4882a593Smuzhiyun			mic-in-differential;
1398*4882a593Smuzhiyun			status = "okay";
1399*4882a593Smuzhiyun		};
1400*4882a593Smuzhiyun	};
1401*4882a593Smuzhiyun};
1402*4882a593Smuzhiyun
1403*4882a593Smuzhiyun&i2c5 {
1404*4882a593Smuzhiyun	status = "okay";
1405*4882a593Smuzhiyun
1406*4882a593Smuzhiyun	mxc6655xa: mxc6655xa@15 {
1407*4882a593Smuzhiyun		status = "okay";
1408*4882a593Smuzhiyun		compatible = "gs_mxc6655xa";
1409*4882a593Smuzhiyun		pinctrl-names = "default";
1410*4882a593Smuzhiyun		pinctrl-0 = <&mxc6655xa_irq_pin>;
1411*4882a593Smuzhiyun		reg = <0x15>;
1412*4882a593Smuzhiyun		irq-gpio = <&gpio3 RK_PC1 IRQ_TYPE_LEVEL_LOW>;
1413*4882a593Smuzhiyun		irq_enable = <0>;
1414*4882a593Smuzhiyun		poll_delay_ms = <30>;
1415*4882a593Smuzhiyun		type = <SENSOR_TYPE_ACCEL>;
1416*4882a593Smuzhiyun		power-off-in-suspend = <1>;
1417*4882a593Smuzhiyun		layout = <1>;
1418*4882a593Smuzhiyun	};
1419*4882a593Smuzhiyun};
1420*4882a593Smuzhiyun
1421*4882a593Smuzhiyun&i2s0_8ch {
1422*4882a593Smuzhiyun	status = "okay";
1423*4882a593Smuzhiyun};
1424*4882a593Smuzhiyun
1425*4882a593Smuzhiyun&i2s1_8ch {
1426*4882a593Smuzhiyun	status = "okay";
1427*4882a593Smuzhiyun	rockchip,clk-trcm = <1>;
1428*4882a593Smuzhiyun	pinctrl-names = "default";
1429*4882a593Smuzhiyun	pinctrl-0 = <&i2s1m0_sclktx
1430*4882a593Smuzhiyun		     &i2s1m0_lrcktx
1431*4882a593Smuzhiyun		     &i2s1m0_sdi0
1432*4882a593Smuzhiyun		     &i2s1m0_sdo0>;
1433*4882a593Smuzhiyun};
1434*4882a593Smuzhiyun
1435*4882a593Smuzhiyun&i2s3_2ch {
1436*4882a593Smuzhiyun	status = "okay";
1437*4882a593Smuzhiyun};
1438*4882a593Smuzhiyun
1439*4882a593Smuzhiyun&iep {
1440*4882a593Smuzhiyun	status = "okay";
1441*4882a593Smuzhiyun};
1442*4882a593Smuzhiyun
1443*4882a593Smuzhiyun&iep_mmu {
1444*4882a593Smuzhiyun	status = "okay";
1445*4882a593Smuzhiyun};
1446*4882a593Smuzhiyun
1447*4882a593Smuzhiyun&jpegd {
1448*4882a593Smuzhiyun	status = "okay";
1449*4882a593Smuzhiyun};
1450*4882a593Smuzhiyun
1451*4882a593Smuzhiyun&jpegd_mmu {
1452*4882a593Smuzhiyun	status = "okay";
1453*4882a593Smuzhiyun};
1454*4882a593Smuzhiyun
1455*4882a593Smuzhiyun&mpp_srv {
1456*4882a593Smuzhiyun	status = "okay";
1457*4882a593Smuzhiyun};
1458*4882a593Smuzhiyun
1459*4882a593Smuzhiyun&nandc0 {
1460*4882a593Smuzhiyun	#address-cells = <1>;
1461*4882a593Smuzhiyun	#size-cells = <0>;
1462*4882a593Smuzhiyun	status = "okay";
1463*4882a593Smuzhiyun
1464*4882a593Smuzhiyun	nand@0 {
1465*4882a593Smuzhiyun		reg = <0>;
1466*4882a593Smuzhiyun		nand-bus-width = <8>;
1467*4882a593Smuzhiyun		nand-ecc-mode = "hw";
1468*4882a593Smuzhiyun		nand-ecc-strength = <16>;
1469*4882a593Smuzhiyun		nand-ecc-step-size = <1024>;
1470*4882a593Smuzhiyun	};
1471*4882a593Smuzhiyun};
1472*4882a593Smuzhiyun
1473*4882a593Smuzhiyun/**
1474*4882a593Smuzhiyun * Model: TB-RK3568X
1475*4882a593Smuzhiyun *  -----------------------------------------------------------
1476*4882a593Smuzhiyun * There are 10 independent IO domains in RK3566/RK3568, including PMUIO[0:2] and VCCIO[1:7].
1477*4882a593Smuzhiyun * 1/ PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured;
1478*4882a593Smuzhiyun * 2/ PMUIO2 and VCCIO1,VCCIO[3:7] domains require that their hardware power supply voltages
1479*4882a593Smuzhiyun *    must be consistent with the software configuration correspondingly
1480*4882a593Smuzhiyun *	a/ When the hardware IO level is connected to 1.8V, the software voltage configuration
1481*4882a593Smuzhiyun *	   should also be configured to 1.8V accordingly;
1482*4882a593Smuzhiyun *	b/ When the hardware IO level is connected to 3.3V, the software voltage configuration
1483*4882a593Smuzhiyun *	   should also be configured to 3.3V accordingly;
1484*4882a593Smuzhiyun * 3/ VCCIO2 voltage control selection (0xFDC20140)
1485*4882a593Smuzhiyun *	BIT[0]: 0x0: from GPIO_0A7 (default)
1486*4882a593Smuzhiyun *	BIT[0]: 0x1: from GRF
1487*4882a593Smuzhiyun *    Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7:
1488*4882a593Smuzhiyun *	L:VCCIO2 must supply 3.3V
1489*4882a593Smuzhiyun *	H:VCCIO2 must supply 1.8V
1490*4882a593Smuzhiyun * | supply        | domain | net          | source  | voltage |
1491*4882a593Smuzhiyun *  -----------------------------------------------------------
1492*4882a593Smuzhiyun * | pmuio1-supply | PMUIO1 | vcc3v3_pmu   | LDO6    | 3.3V    |
1493*4882a593Smuzhiyun * | pmuio2-supply | PMUIO2 | vcc3v3_pmu   | LDO6    | 3.3V    |
1494*4882a593Smuzhiyun * | vccio1-supply | VCCIO1 | vccio_acodec | LDO4    | 1.8V    |
1495*4882a593Smuzhiyun * | vccio2-supply | VCCIO2 | vccio_flash  | vcc_1v8 | 1.8V    |
1496*4882a593Smuzhiyun * | vccio3-supply | VCCIO3 | vccio_sd     | LDO5    | 3.3V    |
1497*4882a593Smuzhiyun * | vccio4-supply | VCCIO4 | vcc_1v8      | DCDC5   | 1.8V    |
1498*4882a593Smuzhiyun * | vccio5-supply | VCCIO5 | vcc_3v3      | SWITCH1 | 3.3V    |
1499*4882a593Smuzhiyun * | vccio6-supply | VCCIO6 | vcc_1v8      | DCDC5   | 1.8V    |
1500*4882a593Smuzhiyun * | vccio7-supply | VCCIO7 | vcc_3v3      | SWITCH1 | 3.3V    |
1501*4882a593Smuzhiyun *  -----------------------------------------------------------
1502*4882a593Smuzhiyun */
1503*4882a593Smuzhiyun&pmu_io_domains {
1504*4882a593Smuzhiyun	status = "okay";
1505*4882a593Smuzhiyun	pmuio1-supply = <&vcc3v3_pmu>;
1506*4882a593Smuzhiyun	pmuio2-supply = <&vcc3v3_pmu>;
1507*4882a593Smuzhiyun	vccio1-supply = <&vccio_acodec>;
1508*4882a593Smuzhiyun	// vccio2-supply = <&vccio_flash>;
1509*4882a593Smuzhiyun	vccio3-supply = <&vccio_sd>;
1510*4882a593Smuzhiyun	vccio4-supply = <&vcc_1v8>;
1511*4882a593Smuzhiyun	vccio5-supply = <&vcc_3v3>;
1512*4882a593Smuzhiyun	vccio6-supply = <&vcc_1v8>;
1513*4882a593Smuzhiyun	vccio7-supply = <&vcc_3v3>;
1514*4882a593Smuzhiyun};
1515*4882a593Smuzhiyun
1516*4882a593Smuzhiyun&pwm0 {
1517*4882a593Smuzhiyun	status = "okay";
1518*4882a593Smuzhiyun};
1519*4882a593Smuzhiyun
1520*4882a593Smuzhiyun&pwm4 {
1521*4882a593Smuzhiyun	status = "okay";
1522*4882a593Smuzhiyun};
1523*4882a593Smuzhiyun
1524*4882a593Smuzhiyun&pwm5 {
1525*4882a593Smuzhiyun	status = "okay";
1526*4882a593Smuzhiyun};
1527*4882a593Smuzhiyun
1528*4882a593Smuzhiyun&pwm7 {
1529*4882a593Smuzhiyun	status = "okay";
1530*4882a593Smuzhiyun
1531*4882a593Smuzhiyun	compatible = "rockchip,remotectl-pwm";
1532*4882a593Smuzhiyun	remote_pwm_id = <3>;
1533*4882a593Smuzhiyun	handle_cpu_id = <1>;
1534*4882a593Smuzhiyun	remote_support_psci = <0>;
1535*4882a593Smuzhiyun	pinctrl-names = "default";
1536*4882a593Smuzhiyun	pinctrl-0 = <&pwm7_pins>;
1537*4882a593Smuzhiyun
1538*4882a593Smuzhiyun	ir_key1 {
1539*4882a593Smuzhiyun		rockchip,usercode = <0x4040>;
1540*4882a593Smuzhiyun		rockchip,key_table =
1541*4882a593Smuzhiyun			<0xf2	KEY_REPLY>,
1542*4882a593Smuzhiyun			<0xba	KEY_BACK>,
1543*4882a593Smuzhiyun			<0xf4	KEY_UP>,
1544*4882a593Smuzhiyun			<0xf1	KEY_DOWN>,
1545*4882a593Smuzhiyun			<0xef	KEY_LEFT>,
1546*4882a593Smuzhiyun			<0xee	KEY_RIGHT>,
1547*4882a593Smuzhiyun			<0xbd	KEY_HOME>,
1548*4882a593Smuzhiyun			<0xea	KEY_VOLUMEUP>,
1549*4882a593Smuzhiyun			<0xe3	KEY_VOLUMEDOWN>,
1550*4882a593Smuzhiyun			<0xe2	KEY_SEARCH>,
1551*4882a593Smuzhiyun			<0xb2	KEY_POWER>,
1552*4882a593Smuzhiyun			<0xbc	KEY_MUTE>,
1553*4882a593Smuzhiyun			<0xec	KEY_MENU>,
1554*4882a593Smuzhiyun			<0xbf	0x190>,
1555*4882a593Smuzhiyun			<0xe0	0x191>,
1556*4882a593Smuzhiyun			<0xe1	0x192>,
1557*4882a593Smuzhiyun			<0xe9	183>,
1558*4882a593Smuzhiyun			<0xe6	248>,
1559*4882a593Smuzhiyun			<0xe8	185>,
1560*4882a593Smuzhiyun			<0xe7	186>,
1561*4882a593Smuzhiyun			<0xf0	388>,
1562*4882a593Smuzhiyun			<0xbe	0x175>;
1563*4882a593Smuzhiyun	};
1564*4882a593Smuzhiyun
1565*4882a593Smuzhiyun	ir_key2 {
1566*4882a593Smuzhiyun		rockchip,usercode = <0xff00>;
1567*4882a593Smuzhiyun		rockchip,key_table =
1568*4882a593Smuzhiyun			<0xf9	KEY_HOME>,
1569*4882a593Smuzhiyun			<0xbf	KEY_BACK>,
1570*4882a593Smuzhiyun			<0xfb	KEY_MENU>,
1571*4882a593Smuzhiyun			<0xaa	KEY_REPLY>,
1572*4882a593Smuzhiyun			<0xb9	KEY_UP>,
1573*4882a593Smuzhiyun			<0xe9	KEY_DOWN>,
1574*4882a593Smuzhiyun			<0xb8	KEY_LEFT>,
1575*4882a593Smuzhiyun			<0xea	KEY_RIGHT>,
1576*4882a593Smuzhiyun			<0xeb	KEY_VOLUMEDOWN>,
1577*4882a593Smuzhiyun			<0xef	KEY_VOLUMEUP>,
1578*4882a593Smuzhiyun			<0xf7	KEY_MUTE>,
1579*4882a593Smuzhiyun			<0xe7	KEY_POWER>,
1580*4882a593Smuzhiyun			<0xfc	KEY_POWER>,
1581*4882a593Smuzhiyun			<0xa9	KEY_VOLUMEDOWN>,
1582*4882a593Smuzhiyun			<0xa8	KEY_VOLUMEDOWN>,
1583*4882a593Smuzhiyun			<0xe0	KEY_VOLUMEDOWN>,
1584*4882a593Smuzhiyun			<0xa5	KEY_VOLUMEDOWN>,
1585*4882a593Smuzhiyun			<0xab	183>,
1586*4882a593Smuzhiyun			<0xb7	388>,
1587*4882a593Smuzhiyun			<0xe8	388>,
1588*4882a593Smuzhiyun			<0xf8	184>,
1589*4882a593Smuzhiyun			<0xaf	185>,
1590*4882a593Smuzhiyun			<0xed	KEY_VOLUMEDOWN>,
1591*4882a593Smuzhiyun			<0xee	186>,
1592*4882a593Smuzhiyun			<0xb3	KEY_VOLUMEDOWN>,
1593*4882a593Smuzhiyun			<0xf1	KEY_VOLUMEDOWN>,
1594*4882a593Smuzhiyun			<0xf2	KEY_VOLUMEDOWN>,
1595*4882a593Smuzhiyun			<0xf3	KEY_SEARCH>,
1596*4882a593Smuzhiyun			<0xb4	KEY_VOLUMEDOWN>,
1597*4882a593Smuzhiyun			<0xbe	KEY_SEARCH>;
1598*4882a593Smuzhiyun	};
1599*4882a593Smuzhiyun
1600*4882a593Smuzhiyun	ir_key3 {
1601*4882a593Smuzhiyun		rockchip,usercode = <0x1dcc>;
1602*4882a593Smuzhiyun		rockchip,key_table =
1603*4882a593Smuzhiyun			<0xee	KEY_REPLY>,
1604*4882a593Smuzhiyun			<0xf0	KEY_BACK>,
1605*4882a593Smuzhiyun			<0xf8	KEY_UP>,
1606*4882a593Smuzhiyun			<0xbb	KEY_DOWN>,
1607*4882a593Smuzhiyun			<0xef	KEY_LEFT>,
1608*4882a593Smuzhiyun			<0xed	KEY_RIGHT>,
1609*4882a593Smuzhiyun			<0xfc	KEY_HOME>,
1610*4882a593Smuzhiyun			<0xf1	KEY_VOLUMEUP>,
1611*4882a593Smuzhiyun			<0xfd	KEY_VOLUMEDOWN>,
1612*4882a593Smuzhiyun			<0xb7	KEY_SEARCH>,
1613*4882a593Smuzhiyun			<0xff	KEY_POWER>,
1614*4882a593Smuzhiyun			<0xf3	KEY_MUTE>,
1615*4882a593Smuzhiyun			<0xbf	KEY_MENU>,
1616*4882a593Smuzhiyun			<0xf9	0x191>,
1617*4882a593Smuzhiyun			<0xf5	0x192>,
1618*4882a593Smuzhiyun			<0xb3	388>,
1619*4882a593Smuzhiyun			<0xbe	KEY_1>,
1620*4882a593Smuzhiyun			<0xba	KEY_2>,
1621*4882a593Smuzhiyun			<0xb2	KEY_3>,
1622*4882a593Smuzhiyun			<0xbd	KEY_4>,
1623*4882a593Smuzhiyun			<0xf9	KEY_5>,
1624*4882a593Smuzhiyun			<0xb1	KEY_6>,
1625*4882a593Smuzhiyun			<0xfc	KEY_7>,
1626*4882a593Smuzhiyun			<0xf8	KEY_8>,
1627*4882a593Smuzhiyun			<0xb0	KEY_9>,
1628*4882a593Smuzhiyun			<0xb6	KEY_0>,
1629*4882a593Smuzhiyun			<0xb5	KEY_BACKSPACE>;
1630*4882a593Smuzhiyun	};
1631*4882a593Smuzhiyun};
1632*4882a593Smuzhiyun
1633*4882a593Smuzhiyun&rk_rga {
1634*4882a593Smuzhiyun	status = "okay";
1635*4882a593Smuzhiyun};
1636*4882a593Smuzhiyun
1637*4882a593Smuzhiyun&rkvdec {
1638*4882a593Smuzhiyun	status = "okay";
1639*4882a593Smuzhiyun};
1640*4882a593Smuzhiyun
1641*4882a593Smuzhiyun&rkvdec_mmu {
1642*4882a593Smuzhiyun	status = "okay";
1643*4882a593Smuzhiyun};
1644*4882a593Smuzhiyun
1645*4882a593Smuzhiyun&rkvenc {
1646*4882a593Smuzhiyun	venc-supply = <&vdd_logic>;
1647*4882a593Smuzhiyun	status = "okay";
1648*4882a593Smuzhiyun};
1649*4882a593Smuzhiyun
1650*4882a593Smuzhiyun&rkvenc_mmu {
1651*4882a593Smuzhiyun	status = "okay";
1652*4882a593Smuzhiyun};
1653*4882a593Smuzhiyun
1654*4882a593Smuzhiyun&rknpu {
1655*4882a593Smuzhiyun	rknpu-supply = <&vdd_npu>;
1656*4882a593Smuzhiyun	status = "okay";
1657*4882a593Smuzhiyun};
1658*4882a593Smuzhiyun
1659*4882a593Smuzhiyun&rknpu_mmu {
1660*4882a593Smuzhiyun	status = "okay";
1661*4882a593Smuzhiyun};
1662*4882a593Smuzhiyun
1663*4882a593Smuzhiyun&route_hdmi {
1664*4882a593Smuzhiyun	status = "okay";
1665*4882a593Smuzhiyun	connect = <&vp0_out_hdmi>;
1666*4882a593Smuzhiyun};
1667*4882a593Smuzhiyun
1668*4882a593Smuzhiyun&saradc {
1669*4882a593Smuzhiyun	status = "okay";
1670*4882a593Smuzhiyun	vref-supply = <&vcca_1v8>;
1671*4882a593Smuzhiyun};
1672*4882a593Smuzhiyun
1673*4882a593Smuzhiyun&sdhci {
1674*4882a593Smuzhiyun	bus-width = <8>;
1675*4882a593Smuzhiyun	supports-emmc;
1676*4882a593Smuzhiyun	non-removable;
1677*4882a593Smuzhiyun	max-frequency = <200000000>;
1678*4882a593Smuzhiyun	status = "okay";
1679*4882a593Smuzhiyun};
1680*4882a593Smuzhiyun
1681*4882a593Smuzhiyun&sdmmc0 {
1682*4882a593Smuzhiyun	max-frequency = <150000000>;
1683*4882a593Smuzhiyun	supports-sd;
1684*4882a593Smuzhiyun	bus-width = <4>;
1685*4882a593Smuzhiyun	cap-mmc-highspeed;
1686*4882a593Smuzhiyun	cap-sd-highspeed;
1687*4882a593Smuzhiyun	disable-wp;
1688*4882a593Smuzhiyun	sd-uhs-sdr104;
1689*4882a593Smuzhiyun	vmmc-supply = <&vcc3v3_sd>;
1690*4882a593Smuzhiyun	vqmmc-supply = <&vccio_sd>;
1691*4882a593Smuzhiyun	pinctrl-names = "default";
1692*4882a593Smuzhiyun	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
1693*4882a593Smuzhiyun	status = "okay";
1694*4882a593Smuzhiyun};
1695*4882a593Smuzhiyun
1696*4882a593Smuzhiyun&sfc {
1697*4882a593Smuzhiyun	status = "okay";
1698*4882a593Smuzhiyun};
1699*4882a593Smuzhiyun
1700*4882a593Smuzhiyun&spdif_8ch {
1701*4882a593Smuzhiyun	status = "okay";
1702*4882a593Smuzhiyun};
1703*4882a593Smuzhiyun
1704*4882a593Smuzhiyun&tsadc {
1705*4882a593Smuzhiyun	status = "okay";
1706*4882a593Smuzhiyun};
1707*4882a593Smuzhiyun
1708*4882a593Smuzhiyun&u2phy0_host {
1709*4882a593Smuzhiyun	phy-supply = <&vcc5v0_host>;
1710*4882a593Smuzhiyun	status = "okay";
1711*4882a593Smuzhiyun};
1712*4882a593Smuzhiyun
1713*4882a593Smuzhiyun&u2phy0_otg {
1714*4882a593Smuzhiyun	vbus-supply = <&vcc5v0_otg>;
1715*4882a593Smuzhiyun	status = "okay";
1716*4882a593Smuzhiyun};
1717*4882a593Smuzhiyun
1718*4882a593Smuzhiyun&u2phy1_host {
1719*4882a593Smuzhiyun	phy-supply = <&vcc5v0_host>;
1720*4882a593Smuzhiyun	status = "okay";
1721*4882a593Smuzhiyun};
1722*4882a593Smuzhiyun
1723*4882a593Smuzhiyun&u2phy1_otg {
1724*4882a593Smuzhiyun	phy-supply = <&vcc5v0_host>;
1725*4882a593Smuzhiyun	status = "okay";
1726*4882a593Smuzhiyun};
1727*4882a593Smuzhiyun
1728*4882a593Smuzhiyun&usb2phy0 {
1729*4882a593Smuzhiyun	status = "okay";
1730*4882a593Smuzhiyun};
1731*4882a593Smuzhiyun
1732*4882a593Smuzhiyun&usb2phy1 {
1733*4882a593Smuzhiyun	status = "okay";
1734*4882a593Smuzhiyun};
1735*4882a593Smuzhiyun
1736*4882a593Smuzhiyun&usb_host0_ehci {
1737*4882a593Smuzhiyun	status = "okay";
1738*4882a593Smuzhiyun};
1739*4882a593Smuzhiyun
1740*4882a593Smuzhiyun&usb_host0_ohci {
1741*4882a593Smuzhiyun	status = "okay";
1742*4882a593Smuzhiyun};
1743*4882a593Smuzhiyun
1744*4882a593Smuzhiyun&usb_host1_ehci {
1745*4882a593Smuzhiyun	status = "okay";
1746*4882a593Smuzhiyun};
1747*4882a593Smuzhiyun
1748*4882a593Smuzhiyun&usb_host1_ohci {
1749*4882a593Smuzhiyun	status = "okay";
1750*4882a593Smuzhiyun};
1751*4882a593Smuzhiyun
1752*4882a593Smuzhiyun&usbdrd_dwc3 {
1753*4882a593Smuzhiyun	dr_mode = "otg";
1754*4882a593Smuzhiyun	extcon = <&usb2phy0>;
1755*4882a593Smuzhiyun	status = "okay";
1756*4882a593Smuzhiyun};
1757*4882a593Smuzhiyun
1758*4882a593Smuzhiyun&usbdrd30 {
1759*4882a593Smuzhiyun	status = "okay";
1760*4882a593Smuzhiyun};
1761*4882a593Smuzhiyun
1762*4882a593Smuzhiyun&usbhost_dwc3 {
1763*4882a593Smuzhiyun	status = "okay";
1764*4882a593Smuzhiyun};
1765*4882a593Smuzhiyun
1766*4882a593Smuzhiyun&usbhost30 {
1767*4882a593Smuzhiyun	status = "okay";
1768*4882a593Smuzhiyun};
1769*4882a593Smuzhiyun
1770*4882a593Smuzhiyun&vad {
1771*4882a593Smuzhiyun	rockchip,audio-src = <&i2s1_8ch>;
1772*4882a593Smuzhiyun	rockchip,buffer-time-ms = <128>;
1773*4882a593Smuzhiyun	rockchip,det-channel = <0>;
1774*4882a593Smuzhiyun	rockchip,mode = <0>;
1775*4882a593Smuzhiyun};
1776*4882a593Smuzhiyun
1777*4882a593Smuzhiyun&vdpu {
1778*4882a593Smuzhiyun	status = "okay";
1779*4882a593Smuzhiyun};
1780*4882a593Smuzhiyun
1781*4882a593Smuzhiyun&vdpu_mmu {
1782*4882a593Smuzhiyun	status = "okay";
1783*4882a593Smuzhiyun};
1784*4882a593Smuzhiyun
1785*4882a593Smuzhiyun&vepu {
1786*4882a593Smuzhiyun	status = "okay";
1787*4882a593Smuzhiyun};
1788*4882a593Smuzhiyun
1789*4882a593Smuzhiyun&vepu_mmu {
1790*4882a593Smuzhiyun	status = "okay";
1791*4882a593Smuzhiyun};
1792*4882a593Smuzhiyun
1793*4882a593Smuzhiyun&vop {
1794*4882a593Smuzhiyun	status = "okay";
1795*4882a593Smuzhiyun	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
1796*4882a593Smuzhiyun	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
1797*4882a593Smuzhiyun};
1798*4882a593Smuzhiyun
1799*4882a593Smuzhiyun&vop_mmu {
1800*4882a593Smuzhiyun	status = "okay";
1801*4882a593Smuzhiyun};
1802*4882a593Smuzhiyun
1803*4882a593Smuzhiyun&pinctrl {
1804*4882a593Smuzhiyun
1805*4882a593Smuzhiyun	mxc6655xa {
1806*4882a593Smuzhiyun		mxc6655xa_irq_pin: mxc6655xa_irq_pin {
1807*4882a593Smuzhiyun			rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
1808*4882a593Smuzhiyun		};
1809*4882a593Smuzhiyun	};
1810*4882a593Smuzhiyun
1811*4882a593Smuzhiyun	pmic {
1812*4882a593Smuzhiyun		pmic_int: pmic_int {
1813*4882a593Smuzhiyun			rockchip,pins =
1814*4882a593Smuzhiyun				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
1815*4882a593Smuzhiyun		};
1816*4882a593Smuzhiyun
1817*4882a593Smuzhiyun		soc_slppin_pin: soc_slppin_pin {
1818*4882a593Smuzhiyun			rockchip,pins =
1819*4882a593Smuzhiyun				<0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low_pull_down>;
1820*4882a593Smuzhiyun		};
1821*4882a593Smuzhiyun
1822*4882a593Smuzhiyun		soc_slppin_slp: soc_slppin_slp {
1823*4882a593Smuzhiyun			rockchip,pins =
1824*4882a593Smuzhiyun				<0 RK_PA2 1 &pcfg_pull_up>;
1825*4882a593Smuzhiyun		};
1826*4882a593Smuzhiyun
1827*4882a593Smuzhiyun		soc_slppin_rst: soc_slppin_rst {
1828*4882a593Smuzhiyun			rockchip,pins =
1829*4882a593Smuzhiyun				<0 RK_PA2 2 &pcfg_pull_none>;
1830*4882a593Smuzhiyun		};
1831*4882a593Smuzhiyun	};
1832*4882a593Smuzhiyun
1833*4882a593Smuzhiyun	sdio-pwrseq {
1834*4882a593Smuzhiyun		wifi_enable_h: wifi-enable-h {
1835*4882a593Smuzhiyun			rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
1836*4882a593Smuzhiyun		};
1837*4882a593Smuzhiyun	};
1838*4882a593Smuzhiyun
1839*4882a593Smuzhiyun	touch {
1840*4882a593Smuzhiyun		touch_pin: touch-pin {
1841*4882a593Smuzhiyun			rockchip,pins =
1842*4882a593Smuzhiyun				<0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>,
1843*4882a593Smuzhiyun				<0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
1844*4882a593Smuzhiyun		};
1845*4882a593Smuzhiyun	};
1846*4882a593Smuzhiyun
1847*4882a593Smuzhiyun	usb {
1848*4882a593Smuzhiyun		vcc5v0_host_en: vcc5v0-host-en {
1849*4882a593Smuzhiyun			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1850*4882a593Smuzhiyun		};
1851*4882a593Smuzhiyun
1852*4882a593Smuzhiyun		vcc5v0_otg_en: vcc5v0-otg-en {
1853*4882a593Smuzhiyun			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1854*4882a593Smuzhiyun		};
1855*4882a593Smuzhiyun	};
1856*4882a593Smuzhiyun
1857*4882a593Smuzhiyun	wireless-bluetooth {
1858*4882a593Smuzhiyun		uart8_pin: uart8-pin {
1859*4882a593Smuzhiyun			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
1860*4882a593Smuzhiyun		};
1861*4882a593Smuzhiyun	};
1862*4882a593Smuzhiyun};
1863