1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include "rk3568-nvr.dtsi" 10*4882a593Smuzhiyun#include <dt-bindings/clock/rk618-cru.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun model = "Rockchip RK3568 NVR DEMO V10 Board"; 14*4882a593Smuzhiyun compatible = "rockchip,rk3568-nvr-demo-v10", "rockchip,rk3568"; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun gpio-leds { 17*4882a593Smuzhiyun compatible = "gpio-leds"; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun hdd-led { 20*4882a593Smuzhiyun gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; 21*4882a593Smuzhiyun default-state = "off"; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun net-led { 24*4882a593Smuzhiyun gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; 25*4882a593Smuzhiyun default-state = "off"; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun work-led { 28*4882a593Smuzhiyun gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; 29*4882a593Smuzhiyun linux,default-trigger = "timer"; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun i2s1_sound: i2s1-sound { 34*4882a593Smuzhiyun status = "okay"; 35*4882a593Smuzhiyun compatible = "simple-audio-card"; 36*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 37*4882a593Smuzhiyun simple-audio-card,mclk-fs = <256>; 38*4882a593Smuzhiyun simple-audio-card,name = "rockchip,i2s1-sound"; 39*4882a593Smuzhiyun simple-audio-card,cpu { 40*4882a593Smuzhiyun sound-dai = <&i2s1_8ch>; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun simple-audio-card,codec { 43*4882a593Smuzhiyun sound-dai = <&es8311>; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun vcc2v5_sys: vcc2v5-ddr { 48*4882a593Smuzhiyun compatible = "regulator-fixed"; 49*4882a593Smuzhiyun regulator-name = "vcc2v5-sys"; 50*4882a593Smuzhiyun regulator-always-on; 51*4882a593Smuzhiyun regulator-boot-on; 52*4882a593Smuzhiyun regulator-min-microvolt = <2500000>; 53*4882a593Smuzhiyun regulator-max-microvolt = <2500000>; 54*4882a593Smuzhiyun vin-supply = <&vcc3v3_sys>; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun vcc3v3_pcie: gpio-regulator { 58*4882a593Smuzhiyun compatible = "regulator-fixed"; 59*4882a593Smuzhiyun regulator-name = "vcc3v3_pcie"; 60*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 61*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 62*4882a593Smuzhiyun gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; 63*4882a593Smuzhiyun startup-delay-us = <5000>; 64*4882a593Smuzhiyun vin-supply = <&dc_12v>; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun pcie30_avdd0v9: pcie30-avdd0v9 { 68*4882a593Smuzhiyun compatible = "regulator-fixed"; 69*4882a593Smuzhiyun regulator-name = "pcie30_avdd0v9"; 70*4882a593Smuzhiyun regulator-always-on; 71*4882a593Smuzhiyun regulator-boot-on; 72*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 73*4882a593Smuzhiyun regulator-max-microvolt = <900000>; 74*4882a593Smuzhiyun vin-supply = <&vcc3v3_sys>; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun pcie30_avdd1v8: pcie30-avdd1v8 { 78*4882a593Smuzhiyun compatible = "regulator-fixed"; 79*4882a593Smuzhiyun regulator-name = "pcie30_avdd1v8"; 80*4882a593Smuzhiyun regulator-always-on; 81*4882a593Smuzhiyun regulator-boot-on; 82*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 83*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 84*4882a593Smuzhiyun vin-supply = <&vcc3v3_sys>; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun vcc3v3_bu: vcc3v3-bu { 88*4882a593Smuzhiyun compatible = "regulator-fixed"; 89*4882a593Smuzhiyun regulator-name = "vcc3v3_bu"; 90*4882a593Smuzhiyun regulator-always-on; 91*4882a593Smuzhiyun regulator-boot-on; 92*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 93*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 94*4882a593Smuzhiyun vin-supply = <&vcc5v0_sys>; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun}; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun&combphy1_usq { 99*4882a593Smuzhiyun pinctrl-names = "default"; 100*4882a593Smuzhiyun pinctrl-0 = <&sata_pm_reset>; 101*4882a593Smuzhiyun rockchip,dis-u3otg1-port; 102*4882a593Smuzhiyun status = "okay"; 103*4882a593Smuzhiyun}; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun&combphy2_psq{ 106*4882a593Smuzhiyun status = "okay"; 107*4882a593Smuzhiyun}; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun&gmac0 { 110*4882a593Smuzhiyun phy-mode = "rgmii"; 111*4882a593Smuzhiyun clock_in_out = "output"; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; 114*4882a593Smuzhiyun snps,reset-active-low; 115*4882a593Smuzhiyun /* Reset time is 20ms, 100ms for rtl8211f */ 116*4882a593Smuzhiyun snps,reset-delays-us = <0 20000 100000>; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; 119*4882a593Smuzhiyun assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; 120*4882a593Smuzhiyun assigned-clock-rates = <0>, <125000000>; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun pinctrl-names = "default"; 123*4882a593Smuzhiyun pinctrl-0 = <&gmac0_miim 124*4882a593Smuzhiyun &gmac0_tx_bus2 125*4882a593Smuzhiyun &gmac0_rx_bus2 126*4882a593Smuzhiyun &gmac0_rgmii_clk 127*4882a593Smuzhiyun &gmac0_rgmii_bus>; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun tx_delay = <0x43>; 130*4882a593Smuzhiyun rx_delay = <0x33>; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun phy-handle = <&rgmii_phy0>; 133*4882a593Smuzhiyun status = "okay"; 134*4882a593Smuzhiyun}; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun&gmac1 { 137*4882a593Smuzhiyun phy-mode = "rgmii"; 138*4882a593Smuzhiyun clock_in_out = "output"; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun snps,reset-gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>; 141*4882a593Smuzhiyun snps,reset-active-low; 142*4882a593Smuzhiyun /* Reset time is 20ms, 100ms for rtl8211f */ 143*4882a593Smuzhiyun snps,reset-delays-us = <0 20000 100000>; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; 146*4882a593Smuzhiyun assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; 147*4882a593Smuzhiyun assigned-clock-rates = <0>, <125000000>; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun pinctrl-names = "default"; 150*4882a593Smuzhiyun pinctrl-0 = <&gmac1m1_miim 151*4882a593Smuzhiyun &gmac1m1_tx_bus2 152*4882a593Smuzhiyun &gmac1m1_rx_bus2 153*4882a593Smuzhiyun &gmac1m1_rgmii_clk 154*4882a593Smuzhiyun &gmac1m1_rgmii_bus>; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun tx_delay = <0x4f>; 157*4882a593Smuzhiyun rx_delay = <0x2d>; 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun phy-handle = <&rgmii_phy1>; 160*4882a593Smuzhiyun status = "okay"; 161*4882a593Smuzhiyun}; 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun&i2c1 { 164*4882a593Smuzhiyun status = "okay"; 165*4882a593Smuzhiyun hym8563: hym8563@51 { 166*4882a593Smuzhiyun compatible = "haoyu,hym8563"; 167*4882a593Smuzhiyun reg = <0x51>; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun pinctrl-names = "default"; 170*4882a593Smuzhiyun pinctrl-0 = <&rtc_int>; 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 173*4882a593Smuzhiyun interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>; 174*4882a593Smuzhiyun }; 175*4882a593Smuzhiyun}; 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun&i2c3 { 178*4882a593Smuzhiyun status = "okay"; 179*4882a593Smuzhiyun clock-frequency = <400000>; 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun es8311: es8311@18 { 182*4882a593Smuzhiyun compatible = "everest,es8311"; 183*4882a593Smuzhiyun reg = <0x18>; 184*4882a593Smuzhiyun clocks = <&cru I2S1_MCLKOUT>; 185*4882a593Smuzhiyun clock-names = "mclk"; 186*4882a593Smuzhiyun adc-pga-gain = <6>; /* 18dB */ 187*4882a593Smuzhiyun adc-volume = <0xbf>; /* 0dB */ 188*4882a593Smuzhiyun dac-volume = <0xbf>; /* 0dB */ 189*4882a593Smuzhiyun aec-mode = "dac left, adc right"; 190*4882a593Smuzhiyun pinctrl-names = "default"; 191*4882a593Smuzhiyun pinctrl-0 = <&i2s1m0_mclk>; 192*4882a593Smuzhiyun assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; 193*4882a593Smuzhiyun assigned-clock-rates = <12288000>; 194*4882a593Smuzhiyun assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; 195*4882a593Smuzhiyun spk-ctl-gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_HIGH>; 196*4882a593Smuzhiyun #sound-dai-cells = <0>; 197*4882a593Smuzhiyun }; 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun rk618@50 { 200*4882a593Smuzhiyun compatible = "rockchip,rk618"; 201*4882a593Smuzhiyun reg = <0x50>; 202*4882a593Smuzhiyun pinctrl-names = "default"; 203*4882a593Smuzhiyun pinctrl-0 = <&i2s3m1_mclk &rk618_int>; 204*4882a593Smuzhiyun clocks = <&cru I2S3_MCLKOUT>; 205*4882a593Smuzhiyun clock-names = "clkin"; 206*4882a593Smuzhiyun assigned-clocks =<&cru I2S3_MCLKOUT>, <&cru I2S3_MCLK_IOE>; 207*4882a593Smuzhiyun assigned-clock-parents = <&cru I2S3_MCLKOUT_TX>, <&cru I2S3_MCLKOUT>; 208*4882a593Smuzhiyun assigned-clock-rates = <11289600>; 209*4882a593Smuzhiyun reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; 210*4882a593Smuzhiyun status = "okay"; 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun clock: cru { 213*4882a593Smuzhiyun compatible = "rockchip,rk618-cru"; 214*4882a593Smuzhiyun clocks = <&cru I2S3_MCLKOUT>, <&cru DCLK_VOP2>; 215*4882a593Smuzhiyun clock-names = "clkin", "lcdc0_dclkp"; 216*4882a593Smuzhiyun assigned-clocks = <&clock SCALER_PLLIN_CLK>, 217*4882a593Smuzhiyun <&clock VIF_PLLIN_CLK>, 218*4882a593Smuzhiyun <&clock SCALER_CLK>, 219*4882a593Smuzhiyun <&clock VIF0_PRE_CLK>, 220*4882a593Smuzhiyun <&clock CODEC_CLK>, 221*4882a593Smuzhiyun <&clock DITHER_CLK>; 222*4882a593Smuzhiyun assigned-clock-parents = <&cru I2S3_MCLKOUT_TX>, 223*4882a593Smuzhiyun <&clock LCDC0_CLK>, 224*4882a593Smuzhiyun <&clock SCALER_PLL_CLK>, 225*4882a593Smuzhiyun <&clock VIF_PLL_CLK>, 226*4882a593Smuzhiyun <&cru I2S3_MCLKOUT>, 227*4882a593Smuzhiyun <&clock VIF0_CLK>; 228*4882a593Smuzhiyun #clock-cells = <1>; 229*4882a593Smuzhiyun status = "okay"; 230*4882a593Smuzhiyun }; 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun hdmi { 233*4882a593Smuzhiyun compatible = "rockchip,rk618-hdmi"; 234*4882a593Smuzhiyun clocks = <&clock HDMI_CLK>; 235*4882a593Smuzhiyun clock-names = "hdmi"; 236*4882a593Smuzhiyun assigned-clocks = <&clock HDMI_CLK>; 237*4882a593Smuzhiyun assigned-clock-parents = <&clock VIF0_CLK>; 238*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 239*4882a593Smuzhiyun interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 240*4882a593Smuzhiyun status = "okay"; 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun ports { 243*4882a593Smuzhiyun #address-cells = <1>; 244*4882a593Smuzhiyun #size-cells = <0>; 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun port@0 { 247*4882a593Smuzhiyun reg = <0>; 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun hdmi_in_rgb: endpoint { 250*4882a593Smuzhiyun remote-endpoint = <&rgb_out_hdmi>; 251*4882a593Smuzhiyun }; 252*4882a593Smuzhiyun }; 253*4882a593Smuzhiyun }; 254*4882a593Smuzhiyun }; 255*4882a593Smuzhiyun }; 256*4882a593Smuzhiyun}; 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun&mdio0 { 259*4882a593Smuzhiyun rgmii_phy0: phy@0 { 260*4882a593Smuzhiyun compatible = "ethernet-phy-ieee802.3-c22"; 261*4882a593Smuzhiyun reg = <0x0>; 262*4882a593Smuzhiyun }; 263*4882a593Smuzhiyun}; 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun&mdio1 { 266*4882a593Smuzhiyun rgmii_phy1: phy@0 { 267*4882a593Smuzhiyun compatible = "ethernet-phy-ieee802.3-c22"; 268*4882a593Smuzhiyun reg = <0x0>; 269*4882a593Smuzhiyun }; 270*4882a593Smuzhiyun}; 271*4882a593Smuzhiyun 272*4882a593Smuzhiyun&pcie30phy { 273*4882a593Smuzhiyun status = "okay"; 274*4882a593Smuzhiyun}; 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun&pcie3x1 { 277*4882a593Smuzhiyun reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; 278*4882a593Smuzhiyun vpcie3v3-supply = <&vcc3v3_pcie>; 279*4882a593Smuzhiyun status = "okay"; 280*4882a593Smuzhiyun}; 281*4882a593Smuzhiyun 282*4882a593Smuzhiyun&pcie3x2 { 283*4882a593Smuzhiyun reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; 284*4882a593Smuzhiyun vpcie3v3-supply = <&vcc3v3_pcie>; 285*4882a593Smuzhiyun status = "okay"; 286*4882a593Smuzhiyun}; 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun&pwm15 { 289*4882a593Smuzhiyun compatible = "rockchip,remotectl-pwm"; 290*4882a593Smuzhiyun pinctrl-names = "default"; 291*4882a593Smuzhiyun pinctrl-0 = <&pwm15m1_pins>; 292*4882a593Smuzhiyun remote_pwm_id = <3>; 293*4882a593Smuzhiyun handle_cpu_id = <1>; 294*4882a593Smuzhiyun remote_support_psci = <0>; 295*4882a593Smuzhiyun status = "okay"; 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun ir_key1 { 298*4882a593Smuzhiyun rockchip,usercode = <0x4040>; 299*4882a593Smuzhiyun rockchip,key_table = 300*4882a593Smuzhiyun <0xf2 KEY_REPLY>, 301*4882a593Smuzhiyun <0xba KEY_BACK>, 302*4882a593Smuzhiyun <0xf4 KEY_UP>, 303*4882a593Smuzhiyun <0xf1 KEY_DOWN>, 304*4882a593Smuzhiyun <0xef KEY_LEFT>, 305*4882a593Smuzhiyun <0xee KEY_RIGHT>, 306*4882a593Smuzhiyun <0xbd KEY_HOME>, 307*4882a593Smuzhiyun <0xea KEY_VOLUMEUP>, 308*4882a593Smuzhiyun <0xe3 KEY_VOLUMEDOWN>, 309*4882a593Smuzhiyun <0xe2 KEY_SEARCH>, 310*4882a593Smuzhiyun <0xb2 KEY_POWER>, 311*4882a593Smuzhiyun <0xbc KEY_MUTE>, 312*4882a593Smuzhiyun <0xec KEY_MENU>, 313*4882a593Smuzhiyun <0xbf 0x190>, 314*4882a593Smuzhiyun <0xe0 0x191>, 315*4882a593Smuzhiyun <0xe1 0x192>, 316*4882a593Smuzhiyun <0xe9 183>, 317*4882a593Smuzhiyun <0xe6 248>, 318*4882a593Smuzhiyun <0xe8 185>, 319*4882a593Smuzhiyun <0xe7 186>, 320*4882a593Smuzhiyun <0xf0 388>, 321*4882a593Smuzhiyun <0xbe 0x175>; 322*4882a593Smuzhiyun }; 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun ir_key2 { 325*4882a593Smuzhiyun rockchip,usercode = <0xff00>; 326*4882a593Smuzhiyun rockchip,key_table = 327*4882a593Smuzhiyun <0xf9 KEY_HOME>, 328*4882a593Smuzhiyun <0xbf KEY_BACK>, 329*4882a593Smuzhiyun <0xfb KEY_MENU>, 330*4882a593Smuzhiyun <0xaa KEY_REPLY>, 331*4882a593Smuzhiyun <0xb9 KEY_UP>, 332*4882a593Smuzhiyun <0xe9 KEY_DOWN>, 333*4882a593Smuzhiyun <0xb8 KEY_LEFT>, 334*4882a593Smuzhiyun <0xea KEY_RIGHT>, 335*4882a593Smuzhiyun <0xeb KEY_VOLUMEDOWN>, 336*4882a593Smuzhiyun <0xef KEY_VOLUMEUP>, 337*4882a593Smuzhiyun <0xf7 KEY_MUTE>, 338*4882a593Smuzhiyun <0xe7 KEY_POWER>, 339*4882a593Smuzhiyun <0xfc KEY_POWER>, 340*4882a593Smuzhiyun <0xa9 KEY_VOLUMEDOWN>, 341*4882a593Smuzhiyun <0xa8 KEY_PLAYPAUSE>, 342*4882a593Smuzhiyun <0xe0 KEY_VOLUMEDOWN>, 343*4882a593Smuzhiyun <0xa5 KEY_VOLUMEDOWN>, 344*4882a593Smuzhiyun <0xab 183>, 345*4882a593Smuzhiyun <0xb7 388>, 346*4882a593Smuzhiyun <0xe8 388>, 347*4882a593Smuzhiyun <0xf8 184>, 348*4882a593Smuzhiyun <0xaf 185>, 349*4882a593Smuzhiyun <0xed KEY_VOLUMEDOWN>, 350*4882a593Smuzhiyun <0xee 186>, 351*4882a593Smuzhiyun <0xb3 KEY_VOLUMEDOWN>, 352*4882a593Smuzhiyun <0xf1 KEY_VOLUMEDOWN>, 353*4882a593Smuzhiyun <0xf2 KEY_VOLUMEDOWN>, 354*4882a593Smuzhiyun <0xf3 KEY_SEARCH>, 355*4882a593Smuzhiyun <0xb4 KEY_VOLUMEDOWN>, 356*4882a593Smuzhiyun <0xa4 KEY_SETUP>, 357*4882a593Smuzhiyun <0xbe KEY_SEARCH>; 358*4882a593Smuzhiyun }; 359*4882a593Smuzhiyun 360*4882a593Smuzhiyun ir_key3 { 361*4882a593Smuzhiyun rockchip,usercode = <0x1dcc>; 362*4882a593Smuzhiyun rockchip,key_table = 363*4882a593Smuzhiyun <0xee KEY_REPLY>, 364*4882a593Smuzhiyun <0xf0 KEY_BACK>, 365*4882a593Smuzhiyun <0xf8 KEY_UP>, 366*4882a593Smuzhiyun <0xbb KEY_DOWN>, 367*4882a593Smuzhiyun <0xef KEY_LEFT>, 368*4882a593Smuzhiyun <0xed KEY_RIGHT>, 369*4882a593Smuzhiyun <0xfc KEY_HOME>, 370*4882a593Smuzhiyun <0xf1 KEY_VOLUMEUP>, 371*4882a593Smuzhiyun <0xfd KEY_VOLUMEDOWN>, 372*4882a593Smuzhiyun <0xb7 KEY_SEARCH>, 373*4882a593Smuzhiyun <0xff KEY_POWER>, 374*4882a593Smuzhiyun <0xf3 KEY_MUTE>, 375*4882a593Smuzhiyun <0xbf KEY_MENU>, 376*4882a593Smuzhiyun <0xf9 0x191>, 377*4882a593Smuzhiyun <0xf5 0x192>, 378*4882a593Smuzhiyun <0xb3 388>, 379*4882a593Smuzhiyun <0xbe KEY_1>, 380*4882a593Smuzhiyun <0xba KEY_2>, 381*4882a593Smuzhiyun <0xb2 KEY_3>, 382*4882a593Smuzhiyun <0xbd KEY_4>, 383*4882a593Smuzhiyun <0xf9 KEY_5>, 384*4882a593Smuzhiyun <0xb1 KEY_6>, 385*4882a593Smuzhiyun <0xfc KEY_7>, 386*4882a593Smuzhiyun <0xf8 KEY_8>, 387*4882a593Smuzhiyun <0xb0 KEY_9>, 388*4882a593Smuzhiyun <0xb6 KEY_0>, 389*4882a593Smuzhiyun <0xb5 KEY_BACKSPACE>; 390*4882a593Smuzhiyun }; 391*4882a593Smuzhiyun}; 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun&rgb { 394*4882a593Smuzhiyun status = "okay"; 395*4882a593Smuzhiyun pinctrl-names = "default"; 396*4882a593Smuzhiyun pinctrl-0 = <&lcdc_ctl>; 397*4882a593Smuzhiyun ports { 398*4882a593Smuzhiyun port@1 { 399*4882a593Smuzhiyun reg = <1>; 400*4882a593Smuzhiyun 401*4882a593Smuzhiyun rgb_out_hdmi: endpoint { 402*4882a593Smuzhiyun remote-endpoint = <&hdmi_in_rgb>; 403*4882a593Smuzhiyun }; 404*4882a593Smuzhiyun }; 405*4882a593Smuzhiyun }; 406*4882a593Smuzhiyun}; 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun&rgb_in_vp2 { 409*4882a593Smuzhiyun status = "okay"; 410*4882a593Smuzhiyun}; 411*4882a593Smuzhiyun 412*4882a593Smuzhiyun&sata1 { 413*4882a593Smuzhiyun status = "okay"; 414*4882a593Smuzhiyun}; 415*4882a593Smuzhiyun 416*4882a593Smuzhiyun&sata2 { 417*4882a593Smuzhiyun status = "okay"; 418*4882a593Smuzhiyun}; 419*4882a593Smuzhiyun 420*4882a593Smuzhiyun&pinctrl { 421*4882a593Smuzhiyun rk618 { 422*4882a593Smuzhiyun rk618_reset: rk618-reeset { 423*4882a593Smuzhiyun rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_output_high>; 424*4882a593Smuzhiyun }; 425*4882a593Smuzhiyun rk618_int: rk618-int { 426*4882a593Smuzhiyun rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 427*4882a593Smuzhiyun }; 428*4882a593Smuzhiyun }; 429*4882a593Smuzhiyun 430*4882a593Smuzhiyun rtc { 431*4882a593Smuzhiyun rtc_int: rtc-int { 432*4882a593Smuzhiyun rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; 433*4882a593Smuzhiyun }; 434*4882a593Smuzhiyun }; 435*4882a593Smuzhiyun 436*4882a593Smuzhiyun sata { 437*4882a593Smuzhiyun sata_pm_reset: sata-pm-reset { 438*4882a593Smuzhiyun rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>; 439*4882a593Smuzhiyun }; 440*4882a593Smuzhiyun }; 441*4882a593Smuzhiyun}; 442