1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include <dt-bindings/display/media-bus-format.h> 8*4882a593Smuzhiyun#include "rk3568-evb2-lp4x-v10.dtsi" 9*4882a593Smuzhiyun#include "rk3568-android.dtsi" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun&dsi0 { 12*4882a593Smuzhiyun status = "disabled"; 13*4882a593Smuzhiyun}; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun&hdmi { 16*4882a593Smuzhiyun status = "disabled"; 17*4882a593Smuzhiyun}; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun&i2c3 { 20*4882a593Smuzhiyun clock-frequency = <400000>; 21*4882a593Smuzhiyun status = "okay"; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun sii9022: sii9022@39 { 24*4882a593Smuzhiyun compatible = "sil,sii9022"; 25*4882a593Smuzhiyun reg = <0x39>; 26*4882a593Smuzhiyun pinctrl-names = "default"; 27*4882a593Smuzhiyun pinctrl-0 = <&sii902x_hdmi_int>; 28*4882a593Smuzhiyun interrupt-parent = <&gpio3>; 29*4882a593Smuzhiyun interrupts = <RK_PA0 IRQ_TYPE_LEVEL_HIGH>; 30*4882a593Smuzhiyun reset-gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>; 31*4882a593Smuzhiyun enable-gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; 32*4882a593Smuzhiyun bus-format = <MEDIA_BUS_FMT_YUYV8_1X16>; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun ports { 35*4882a593Smuzhiyun #address-cells = <1>; 36*4882a593Smuzhiyun #size-cells = <0>; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun port@0 { 39*4882a593Smuzhiyun reg = <0>; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun sii9022_in_rgb: endpoint { 42*4882a593Smuzhiyun remote-endpoint = <&rgb_out_sii9022>; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun}; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun&video_phy0 { 50*4882a593Smuzhiyun status = "disabled"; 51*4882a593Smuzhiyun}; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun&rgb { 54*4882a593Smuzhiyun status = "okay"; 55*4882a593Smuzhiyun pinctrl-names = "default"; 56*4882a593Smuzhiyun pinctrl-0 = <&bt1120_pins>; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun ports { 59*4882a593Smuzhiyun port@1 { 60*4882a593Smuzhiyun reg = <1>; 61*4882a593Smuzhiyun #address-cells = <1>; 62*4882a593Smuzhiyun #size-cells = <0>; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun rgb_out_sii9022: endpoint@0 { 65*4882a593Smuzhiyun reg = <0>; 66*4882a593Smuzhiyun remote-endpoint = <&sii9022_in_rgb>; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun}; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun&rgb_in_vp2 { 73*4882a593Smuzhiyun status = "okay"; 74*4882a593Smuzhiyun}; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun&vcc3v3_lcd1_n { 77*4882a593Smuzhiyun status = "disabled"; 78*4882a593Smuzhiyun gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; 79*4882a593Smuzhiyun enable-active-high; 80*4882a593Smuzhiyun}; 81