1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 8*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h> 9*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h> 10*4882a593Smuzhiyun#include <dt-bindings/input/rk-input.h> 11*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h> 12*4882a593Smuzhiyun#include <dt-bindings/sensor-dev.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun/ { 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun adc_keys: adc-keys { 17*4882a593Smuzhiyun compatible = "adc-keys"; 18*4882a593Smuzhiyun io-channels = <&saradc 0>; 19*4882a593Smuzhiyun io-channel-names = "buttons"; 20*4882a593Smuzhiyun keyup-threshold-microvolt = <1800000>; 21*4882a593Smuzhiyun poll-interval = <100>; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun vol-up-key { 24*4882a593Smuzhiyun label = "volume up"; 25*4882a593Smuzhiyun linux,code = <KEY_VOLUMEUP>; 26*4882a593Smuzhiyun press-threshold-microvolt = <1750>; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun vol-down-key { 30*4882a593Smuzhiyun label = "volume down"; 31*4882a593Smuzhiyun linux,code = <KEY_VOLUMEDOWN>; 32*4882a593Smuzhiyun press-threshold-microvolt = <297500>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun menu-key { 36*4882a593Smuzhiyun label = "menu"; 37*4882a593Smuzhiyun linux,code = <KEY_MENU>; 38*4882a593Smuzhiyun press-threshold-microvolt = <980000>; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun back-key { 42*4882a593Smuzhiyun label = "back"; 43*4882a593Smuzhiyun linux,code = <KEY_BACK>; 44*4882a593Smuzhiyun press-threshold-microvolt = <1305500>; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun audiopwmout_diff: audiopwmout-diff { 49*4882a593Smuzhiyun status = "disabled"; 50*4882a593Smuzhiyun compatible = "simple-audio-card"; 51*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 52*4882a593Smuzhiyun simple-audio-card,name = "rockchip,audiopwmout-diff"; 53*4882a593Smuzhiyun simple-audio-card,mclk-fs = <256>; 54*4882a593Smuzhiyun simple-audio-card,bitclock-master = <&master>; 55*4882a593Smuzhiyun simple-audio-card,frame-master = <&master>; 56*4882a593Smuzhiyun simple-audio-card,cpu { 57*4882a593Smuzhiyun sound-dai = <&i2s3_2ch>; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun master: simple-audio-card,codec { 60*4882a593Smuzhiyun sound-dai = <&dig_acodec>; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun backlight: backlight { 65*4882a593Smuzhiyun compatible = "pwm-backlight"; 66*4882a593Smuzhiyun pwms = <&pwm4 0 25000 0>; 67*4882a593Smuzhiyun brightness-levels = < 68*4882a593Smuzhiyun 0 20 20 21 21 22 22 23 69*4882a593Smuzhiyun 23 24 24 25 25 26 26 27 70*4882a593Smuzhiyun 27 28 28 29 29 30 30 31 71*4882a593Smuzhiyun 31 32 32 33 33 34 34 35 72*4882a593Smuzhiyun 35 36 36 37 37 38 38 39 73*4882a593Smuzhiyun 40 41 42 43 44 45 46 47 74*4882a593Smuzhiyun 48 49 50 51 52 53 54 55 75*4882a593Smuzhiyun 56 57 58 59 60 61 62 63 76*4882a593Smuzhiyun 64 65 66 67 68 69 70 71 77*4882a593Smuzhiyun 72 73 74 75 76 77 78 79 78*4882a593Smuzhiyun 80 81 82 83 84 85 86 87 79*4882a593Smuzhiyun 88 89 90 91 92 93 94 95 80*4882a593Smuzhiyun 96 97 98 99 100 101 102 103 81*4882a593Smuzhiyun 104 105 106 107 108 109 110 111 82*4882a593Smuzhiyun 112 113 114 115 116 117 118 119 83*4882a593Smuzhiyun 120 121 122 123 124 125 126 127 84*4882a593Smuzhiyun 128 129 130 131 132 133 134 135 85*4882a593Smuzhiyun 136 137 138 139 140 141 142 143 86*4882a593Smuzhiyun 144 145 146 147 148 149 150 151 87*4882a593Smuzhiyun 152 153 154 155 156 157 158 159 88*4882a593Smuzhiyun 160 161 162 163 164 165 166 167 89*4882a593Smuzhiyun 168 169 170 171 172 173 174 175 90*4882a593Smuzhiyun 176 177 178 179 180 181 182 183 91*4882a593Smuzhiyun 184 185 186 187 188 189 190 191 92*4882a593Smuzhiyun 192 193 194 195 196 197 198 199 93*4882a593Smuzhiyun 200 201 202 203 204 205 206 207 94*4882a593Smuzhiyun 208 209 210 211 212 213 214 215 95*4882a593Smuzhiyun 216 217 218 219 220 221 222 223 96*4882a593Smuzhiyun 224 225 226 227 228 229 230 231 97*4882a593Smuzhiyun 232 233 234 235 236 237 238 239 98*4882a593Smuzhiyun 240 241 242 243 244 245 246 247 99*4882a593Smuzhiyun 248 249 250 251 252 253 254 255 100*4882a593Smuzhiyun >; 101*4882a593Smuzhiyun default-brightness-level = <200>; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun backlight1: backlight1 { 105*4882a593Smuzhiyun compatible = "pwm-backlight"; 106*4882a593Smuzhiyun pwms = <&pwm5 0 25000 0>; 107*4882a593Smuzhiyun brightness-levels = < 108*4882a593Smuzhiyun 0 20 20 21 21 22 22 23 109*4882a593Smuzhiyun 23 24 24 25 25 26 26 27 110*4882a593Smuzhiyun 27 28 28 29 29 30 30 31 111*4882a593Smuzhiyun 31 32 32 33 33 34 34 35 112*4882a593Smuzhiyun 35 36 36 37 37 38 38 39 113*4882a593Smuzhiyun 40 41 42 43 44 45 46 47 114*4882a593Smuzhiyun 48 49 50 51 52 53 54 55 115*4882a593Smuzhiyun 56 57 58 59 60 61 62 63 116*4882a593Smuzhiyun 64 65 66 67 68 69 70 71 117*4882a593Smuzhiyun 72 73 74 75 76 77 78 79 118*4882a593Smuzhiyun 80 81 82 83 84 85 86 87 119*4882a593Smuzhiyun 88 89 90 91 92 93 94 95 120*4882a593Smuzhiyun 96 97 98 99 100 101 102 103 121*4882a593Smuzhiyun 104 105 106 107 108 109 110 111 122*4882a593Smuzhiyun 112 113 114 115 116 117 118 119 123*4882a593Smuzhiyun 120 121 122 123 124 125 126 127 124*4882a593Smuzhiyun 128 129 130 131 132 133 134 135 125*4882a593Smuzhiyun 136 137 138 139 140 141 142 143 126*4882a593Smuzhiyun 144 145 146 147 148 149 150 151 127*4882a593Smuzhiyun 152 153 154 155 156 157 158 159 128*4882a593Smuzhiyun 160 161 162 163 164 165 166 167 129*4882a593Smuzhiyun 168 169 170 171 172 173 174 175 130*4882a593Smuzhiyun 176 177 178 179 180 181 182 183 131*4882a593Smuzhiyun 184 185 186 187 188 189 190 191 132*4882a593Smuzhiyun 192 193 194 195 196 197 198 199 133*4882a593Smuzhiyun 200 201 202 203 204 205 206 207 134*4882a593Smuzhiyun 208 209 210 211 212 213 214 215 135*4882a593Smuzhiyun 216 217 218 219 220 221 222 223 136*4882a593Smuzhiyun 224 225 226 227 228 229 230 231 137*4882a593Smuzhiyun 232 233 234 235 236 237 238 239 138*4882a593Smuzhiyun 240 241 242 243 244 245 246 247 139*4882a593Smuzhiyun 248 249 250 251 252 253 254 255 140*4882a593Smuzhiyun >; 141*4882a593Smuzhiyun default-brightness-level = <200>; 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun bt_sco: bt-sco { 145*4882a593Smuzhiyun status = "disabled"; 146*4882a593Smuzhiyun compatible = "delta,dfbmcs320"; 147*4882a593Smuzhiyun #sound-dai-cells = <1>; 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun bt_sound: bt-sound { 151*4882a593Smuzhiyun status = "disabled"; 152*4882a593Smuzhiyun compatible = "simple-audio-card"; 153*4882a593Smuzhiyun simple-audio-card,format = "dsp_a"; 154*4882a593Smuzhiyun simple-audio-card,bitclock-inversion = <0>; 155*4882a593Smuzhiyun simple-audio-card,mclk-fs = <256>; 156*4882a593Smuzhiyun simple-audio-card,name = "rockchip,bt"; 157*4882a593Smuzhiyun simple-audio-card,cpu { 158*4882a593Smuzhiyun sound-dai = <&i2s3_2ch>; 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun simple-audio-card,codec { 161*4882a593Smuzhiyun sound-dai = <&bt_sco 1>; 162*4882a593Smuzhiyun }; 163*4882a593Smuzhiyun }; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun dc_12v: dc-12v { 166*4882a593Smuzhiyun compatible = "regulator-fixed"; 167*4882a593Smuzhiyun regulator-name = "dc_12v"; 168*4882a593Smuzhiyun regulator-always-on; 169*4882a593Smuzhiyun regulator-boot-on; 170*4882a593Smuzhiyun regulator-min-microvolt = <12000000>; 171*4882a593Smuzhiyun regulator-max-microvolt = <12000000>; 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun hdmi_sound: hdmi-sound { 175*4882a593Smuzhiyun compatible = "simple-audio-card"; 176*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 177*4882a593Smuzhiyun simple-audio-card,mclk-fs = <128>; 178*4882a593Smuzhiyun simple-audio-card,name = "rockchip,hdmi"; 179*4882a593Smuzhiyun status = "disabled"; 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun simple-audio-card,cpu { 182*4882a593Smuzhiyun sound-dai = <&i2s0_8ch>; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun simple-audio-card,codec { 185*4882a593Smuzhiyun sound-dai = <&hdmi>; 186*4882a593Smuzhiyun }; 187*4882a593Smuzhiyun }; 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun leds: leds { 190*4882a593Smuzhiyun compatible = "gpio-leds"; 191*4882a593Smuzhiyun work_led: work { 192*4882a593Smuzhiyun gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; 193*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 194*4882a593Smuzhiyun }; 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun pdmics: dummy-codec { 198*4882a593Smuzhiyun status = "disabled"; 199*4882a593Smuzhiyun compatible = "rockchip,dummy-codec"; 200*4882a593Smuzhiyun #sound-dai-cells = <0>; 201*4882a593Smuzhiyun }; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun pdm_mic_array: pdm-mic-array { 204*4882a593Smuzhiyun status = "disabled"; 205*4882a593Smuzhiyun compatible = "simple-audio-card"; 206*4882a593Smuzhiyun simple-audio-card,name = "rockchip,pdm-mic-array"; 207*4882a593Smuzhiyun simple-audio-card,cpu { 208*4882a593Smuzhiyun sound-dai = <&pdm>; 209*4882a593Smuzhiyun }; 210*4882a593Smuzhiyun simple-audio-card,codec { 211*4882a593Smuzhiyun sound-dai = <&pdmics>; 212*4882a593Smuzhiyun }; 213*4882a593Smuzhiyun }; 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun rk809_sound: rk809-sound { 216*4882a593Smuzhiyun status = "okay"; 217*4882a593Smuzhiyun compatible = "rockchip,multicodecs-card"; 218*4882a593Smuzhiyun rockchip,card-name = "rockchip-rk809"; 219*4882a593Smuzhiyun hp-det-gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; 220*4882a593Smuzhiyun rockchip,format = "i2s"; 221*4882a593Smuzhiyun rockchip,mclk-fs = <256>; 222*4882a593Smuzhiyun rockchip,cpu = <&i2s1_8ch>; 223*4882a593Smuzhiyun rockchip,codec = <&rk809_codec>; 224*4882a593Smuzhiyun pinctrl-names = "default"; 225*4882a593Smuzhiyun pinctrl-0 = <&hp_det>; 226*4882a593Smuzhiyun }; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun spdif-sound { 229*4882a593Smuzhiyun status = "okay"; 230*4882a593Smuzhiyun compatible = "simple-audio-card"; 231*4882a593Smuzhiyun simple-audio-card,name = "ROCKCHIP,SPDIF"; 232*4882a593Smuzhiyun simple-audio-card,mclk-fs = <128>; 233*4882a593Smuzhiyun simple-audio-card,cpu { 234*4882a593Smuzhiyun sound-dai = <&spdif_8ch>; 235*4882a593Smuzhiyun }; 236*4882a593Smuzhiyun simple-audio-card,codec { 237*4882a593Smuzhiyun sound-dai = <&spdif_out>; 238*4882a593Smuzhiyun }; 239*4882a593Smuzhiyun }; 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun spdif_out: spdif-out { 242*4882a593Smuzhiyun status = "okay"; 243*4882a593Smuzhiyun compatible = "linux,spdif-dit"; 244*4882a593Smuzhiyun #sound-dai-cells = <0>; 245*4882a593Smuzhiyun }; 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun vad_sound: vad-sound { 248*4882a593Smuzhiyun status = "disabled"; 249*4882a593Smuzhiyun compatible = "rockchip,multicodecs-card"; 250*4882a593Smuzhiyun rockchip,card-name = "rockchip,rk3568-vad"; 251*4882a593Smuzhiyun rockchip,cpu = <&i2s1_8ch>; 252*4882a593Smuzhiyun rockchip,codec = <&rk809_codec>, <&vad>; 253*4882a593Smuzhiyun }; 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun vcc3v3_sys: vcc3v3-sys { 256*4882a593Smuzhiyun compatible = "regulator-fixed"; 257*4882a593Smuzhiyun regulator-name = "vcc3v3_sys"; 258*4882a593Smuzhiyun regulator-always-on; 259*4882a593Smuzhiyun regulator-boot-on; 260*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 261*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 262*4882a593Smuzhiyun vin-supply = <&dc_12v>; 263*4882a593Smuzhiyun }; 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun vcc5v0_sys: vcc5v0-sys { 266*4882a593Smuzhiyun compatible = "regulator-fixed"; 267*4882a593Smuzhiyun regulator-name = "vcc5v0_sys"; 268*4882a593Smuzhiyun regulator-always-on; 269*4882a593Smuzhiyun regulator-boot-on; 270*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 271*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 272*4882a593Smuzhiyun vin-supply = <&dc_12v>; 273*4882a593Smuzhiyun }; 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun vcc5v0_usb: vcc5v0-usb { 276*4882a593Smuzhiyun compatible = "regulator-fixed"; 277*4882a593Smuzhiyun regulator-name = "vcc5v0_usb"; 278*4882a593Smuzhiyun regulator-always-on; 279*4882a593Smuzhiyun regulator-boot-on; 280*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 281*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 282*4882a593Smuzhiyun vin-supply = <&dc_12v>; 283*4882a593Smuzhiyun }; 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun vcc5v0_host: vcc5v0-host-regulator { 286*4882a593Smuzhiyun compatible = "regulator-fixed"; 287*4882a593Smuzhiyun regulator-name = "vcc5v0_host"; 288*4882a593Smuzhiyun regulator-boot-on; 289*4882a593Smuzhiyun regulator-always-on; 290*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 291*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 292*4882a593Smuzhiyun enable-active-high; 293*4882a593Smuzhiyun gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; 294*4882a593Smuzhiyun vin-supply = <&vcc5v0_usb>; 295*4882a593Smuzhiyun pinctrl-names = "default"; 296*4882a593Smuzhiyun pinctrl-0 = <&vcc5v0_host_en>; 297*4882a593Smuzhiyun }; 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun vcc5v0_otg: vcc5v0-otg-regulator { 300*4882a593Smuzhiyun compatible = "regulator-fixed"; 301*4882a593Smuzhiyun regulator-name = "vcc5v0_otg"; 302*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 303*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 304*4882a593Smuzhiyun enable-active-high; 305*4882a593Smuzhiyun gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; 306*4882a593Smuzhiyun vin-supply = <&vcc5v0_usb>; 307*4882a593Smuzhiyun pinctrl-names = "default"; 308*4882a593Smuzhiyun pinctrl-0 = <&vcc5v0_otg_en>; 309*4882a593Smuzhiyun }; 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun vcc3v3_lcd0_n: vcc3v3-lcd0-n { 312*4882a593Smuzhiyun compatible = "regulator-fixed"; 313*4882a593Smuzhiyun regulator-name = "vcc3v3_lcd0_n"; 314*4882a593Smuzhiyun regulator-boot-on; 315*4882a593Smuzhiyun regulator-state-mem { 316*4882a593Smuzhiyun regulator-off-in-suspend; 317*4882a593Smuzhiyun }; 318*4882a593Smuzhiyun }; 319*4882a593Smuzhiyun 320*4882a593Smuzhiyun vcc3v3_lcd1_n: vcc3v3-lcd1-n { 321*4882a593Smuzhiyun compatible = "regulator-fixed"; 322*4882a593Smuzhiyun regulator-name = "vcc3v3_lcd1_n"; 323*4882a593Smuzhiyun regulator-boot-on; 324*4882a593Smuzhiyun regulator-state-mem { 325*4882a593Smuzhiyun regulator-off-in-suspend; 326*4882a593Smuzhiyun }; 327*4882a593Smuzhiyun }; 328*4882a593Smuzhiyun 329*4882a593Smuzhiyun sdio_pwrseq: sdio-pwrseq { 330*4882a593Smuzhiyun compatible = "mmc-pwrseq-simple"; 331*4882a593Smuzhiyun clocks = <&rk809 1>; 332*4882a593Smuzhiyun clock-names = "ext_clock"; 333*4882a593Smuzhiyun pinctrl-names = "default"; 334*4882a593Smuzhiyun pinctrl-0 = <&wifi_enable_h>; 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun /* 337*4882a593Smuzhiyun * On the module itself this is one of these (depending 338*4882a593Smuzhiyun * on the actual card populated): 339*4882a593Smuzhiyun * - SDIO_RESET_L_WL_REG_ON 340*4882a593Smuzhiyun * - PDN (power down when low) 341*4882a593Smuzhiyun */ 342*4882a593Smuzhiyun post-power-on-delay-ms = <200>; 343*4882a593Smuzhiyun reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; 344*4882a593Smuzhiyun }; 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun wireless_wlan: wireless-wlan { 347*4882a593Smuzhiyun compatible = "wlan-platdata"; 348*4882a593Smuzhiyun rockchip,grf = <&grf>; 349*4882a593Smuzhiyun wifi_chip_type = "ap6398s"; 350*4882a593Smuzhiyun WIFI,poweren_gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; 351*4882a593Smuzhiyun status = "okay"; 352*4882a593Smuzhiyun }; 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun wireless_bluetooth: wireless-bluetooth { 355*4882a593Smuzhiyun compatible = "bluetooth-platdata"; 356*4882a593Smuzhiyun clocks = <&rk809 1>; 357*4882a593Smuzhiyun clock-names = "ext_clock"; 358*4882a593Smuzhiyun //wifi-bt-power-toggle; 359*4882a593Smuzhiyun uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; 360*4882a593Smuzhiyun pinctrl-names = "default", "rts_gpio"; 361*4882a593Smuzhiyun pinctrl-0 = <&uart8m0_rtsn>; 362*4882a593Smuzhiyun pinctrl-1 = <&uart8_gpios>; 363*4882a593Smuzhiyun BT,reset_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; 364*4882a593Smuzhiyun BT,wake_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; 365*4882a593Smuzhiyun BT,wake_host_irq = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; 366*4882a593Smuzhiyun status = "okay"; 367*4882a593Smuzhiyun }; 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun test-power { 370*4882a593Smuzhiyun status = "okay"; 371*4882a593Smuzhiyun }; 372*4882a593Smuzhiyun}; 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun&bus_npu { 375*4882a593Smuzhiyun bus-supply = <&vdd_logic>; 376*4882a593Smuzhiyun pvtm-supply = <&vdd_cpu>; 377*4882a593Smuzhiyun status = "okay"; 378*4882a593Smuzhiyun}; 379*4882a593Smuzhiyun 380*4882a593Smuzhiyun&can0 { 381*4882a593Smuzhiyun assigned-clocks = <&cru CLK_CAN0>; 382*4882a593Smuzhiyun assigned-clock-rates = <150000000>; 383*4882a593Smuzhiyun pinctrl-names = "default"; 384*4882a593Smuzhiyun pinctrl-0 = <&can0m1_pins>; 385*4882a593Smuzhiyun status = "disabled"; 386*4882a593Smuzhiyun}; 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun&can1 { 389*4882a593Smuzhiyun assigned-clocks = <&cru CLK_CAN1>; 390*4882a593Smuzhiyun assigned-clock-rates = <150000000>; 391*4882a593Smuzhiyun pinctrl-names = "default"; 392*4882a593Smuzhiyun pinctrl-0 = <&can1m1_pins>; 393*4882a593Smuzhiyun status = "disabled"; 394*4882a593Smuzhiyun}; 395*4882a593Smuzhiyun 396*4882a593Smuzhiyun&can2 { 397*4882a593Smuzhiyun assigned-clocks = <&cru CLK_CAN2>; 398*4882a593Smuzhiyun assigned-clock-rates = <150000000>; 399*4882a593Smuzhiyun pinctrl-names = "default"; 400*4882a593Smuzhiyun pinctrl-0 = <&can2m1_pins>; 401*4882a593Smuzhiyun status = "disabled"; 402*4882a593Smuzhiyun}; 403*4882a593Smuzhiyun 404*4882a593Smuzhiyun&cpu0 { 405*4882a593Smuzhiyun cpu-supply = <&vdd_cpu>; 406*4882a593Smuzhiyun}; 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun&dfi { 409*4882a593Smuzhiyun status = "okay"; 410*4882a593Smuzhiyun}; 411*4882a593Smuzhiyun 412*4882a593Smuzhiyun&dmc { 413*4882a593Smuzhiyun center-supply = <&vdd_logic>; 414*4882a593Smuzhiyun status = "okay"; 415*4882a593Smuzhiyun}; 416*4882a593Smuzhiyun 417*4882a593Smuzhiyun&dsi0 { 418*4882a593Smuzhiyun status = "disabled"; 419*4882a593Smuzhiyun //rockchip,lane-rate = <1000>; 420*4882a593Smuzhiyun dsi0_panel: panel@0 { 421*4882a593Smuzhiyun status = "okay"; 422*4882a593Smuzhiyun compatible = "simple-panel-dsi"; 423*4882a593Smuzhiyun reg = <0>; 424*4882a593Smuzhiyun backlight = <&backlight>; 425*4882a593Smuzhiyun reset-delay-ms = <60>; 426*4882a593Smuzhiyun enable-delay-ms = <60>; 427*4882a593Smuzhiyun prepare-delay-ms = <60>; 428*4882a593Smuzhiyun unprepare-delay-ms = <60>; 429*4882a593Smuzhiyun disable-delay-ms = <60>; 430*4882a593Smuzhiyun dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 431*4882a593Smuzhiyun MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; 432*4882a593Smuzhiyun dsi,format = <MIPI_DSI_FMT_RGB888>; 433*4882a593Smuzhiyun dsi,lanes = <4>; 434*4882a593Smuzhiyun panel-init-sequence = [ 435*4882a593Smuzhiyun 23 00 02 FE 21 436*4882a593Smuzhiyun 23 00 02 04 00 437*4882a593Smuzhiyun 23 00 02 00 64 438*4882a593Smuzhiyun 23 00 02 2A 00 439*4882a593Smuzhiyun 23 00 02 26 64 440*4882a593Smuzhiyun 23 00 02 54 00 441*4882a593Smuzhiyun 23 00 02 50 64 442*4882a593Smuzhiyun 23 00 02 7B 00 443*4882a593Smuzhiyun 23 00 02 77 64 444*4882a593Smuzhiyun 23 00 02 A2 00 445*4882a593Smuzhiyun 23 00 02 9D 64 446*4882a593Smuzhiyun 23 00 02 C9 00 447*4882a593Smuzhiyun 23 00 02 C5 64 448*4882a593Smuzhiyun 23 00 02 01 71 449*4882a593Smuzhiyun 23 00 02 27 71 450*4882a593Smuzhiyun 23 00 02 51 71 451*4882a593Smuzhiyun 23 00 02 78 71 452*4882a593Smuzhiyun 23 00 02 9E 71 453*4882a593Smuzhiyun 23 00 02 C6 71 454*4882a593Smuzhiyun 23 00 02 02 89 455*4882a593Smuzhiyun 23 00 02 28 89 456*4882a593Smuzhiyun 23 00 02 52 89 457*4882a593Smuzhiyun 23 00 02 79 89 458*4882a593Smuzhiyun 23 00 02 9F 89 459*4882a593Smuzhiyun 23 00 02 C7 89 460*4882a593Smuzhiyun 23 00 02 03 9E 461*4882a593Smuzhiyun 23 00 02 29 9E 462*4882a593Smuzhiyun 23 00 02 53 9E 463*4882a593Smuzhiyun 23 00 02 7A 9E 464*4882a593Smuzhiyun 23 00 02 A0 9E 465*4882a593Smuzhiyun 23 00 02 C8 9E 466*4882a593Smuzhiyun 23 00 02 09 00 467*4882a593Smuzhiyun 23 00 02 05 B0 468*4882a593Smuzhiyun 23 00 02 31 00 469*4882a593Smuzhiyun 23 00 02 2B B0 470*4882a593Smuzhiyun 23 00 02 5A 00 471*4882a593Smuzhiyun 23 00 02 55 B0 472*4882a593Smuzhiyun 23 00 02 80 00 473*4882a593Smuzhiyun 23 00 02 7C B0 474*4882a593Smuzhiyun 23 00 02 A7 00 475*4882a593Smuzhiyun 23 00 02 A3 B0 476*4882a593Smuzhiyun 23 00 02 CE 00 477*4882a593Smuzhiyun 23 00 02 CA B0 478*4882a593Smuzhiyun 23 00 02 06 C0 479*4882a593Smuzhiyun 23 00 02 2D C0 480*4882a593Smuzhiyun 23 00 02 56 C0 481*4882a593Smuzhiyun 23 00 02 7D C0 482*4882a593Smuzhiyun 23 00 02 A4 C0 483*4882a593Smuzhiyun 23 00 02 CB C0 484*4882a593Smuzhiyun 23 00 02 07 CF 485*4882a593Smuzhiyun 23 00 02 2F CF 486*4882a593Smuzhiyun 23 00 02 58 CF 487*4882a593Smuzhiyun 23 00 02 7E CF 488*4882a593Smuzhiyun 23 00 02 A5 CF 489*4882a593Smuzhiyun 23 00 02 CC CF 490*4882a593Smuzhiyun 23 00 02 08 DD 491*4882a593Smuzhiyun 23 00 02 30 DD 492*4882a593Smuzhiyun 23 00 02 59 DD 493*4882a593Smuzhiyun 23 00 02 7F DD 494*4882a593Smuzhiyun 23 00 02 A6 DD 495*4882a593Smuzhiyun 23 00 02 CD DD 496*4882a593Smuzhiyun 23 00 02 0E 15 497*4882a593Smuzhiyun 23 00 02 0A E9 498*4882a593Smuzhiyun 23 00 02 36 15 499*4882a593Smuzhiyun 23 00 02 32 E9 500*4882a593Smuzhiyun 23 00 02 5F 15 501*4882a593Smuzhiyun 23 00 02 5B E9 502*4882a593Smuzhiyun 23 00 02 85 15 503*4882a593Smuzhiyun 23 00 02 81 E9 504*4882a593Smuzhiyun 23 00 02 AD 15 505*4882a593Smuzhiyun 23 00 02 A9 E9 506*4882a593Smuzhiyun 23 00 02 D3 15 507*4882a593Smuzhiyun 23 00 02 CF E9 508*4882a593Smuzhiyun 23 00 02 0B 14 509*4882a593Smuzhiyun 23 00 02 33 14 510*4882a593Smuzhiyun 23 00 02 5C 14 511*4882a593Smuzhiyun 23 00 02 82 14 512*4882a593Smuzhiyun 23 00 02 AA 14 513*4882a593Smuzhiyun 23 00 02 D0 14 514*4882a593Smuzhiyun 23 00 02 0C 36 515*4882a593Smuzhiyun 23 00 02 34 36 516*4882a593Smuzhiyun 23 00 02 5D 36 517*4882a593Smuzhiyun 23 00 02 83 36 518*4882a593Smuzhiyun 23 00 02 AB 36 519*4882a593Smuzhiyun 23 00 02 D1 36 520*4882a593Smuzhiyun 23 00 02 0D 6B 521*4882a593Smuzhiyun 23 00 02 35 6B 522*4882a593Smuzhiyun 23 00 02 5E 6B 523*4882a593Smuzhiyun 23 00 02 84 6B 524*4882a593Smuzhiyun 23 00 02 AC 6B 525*4882a593Smuzhiyun 23 00 02 D2 6B 526*4882a593Smuzhiyun 23 00 02 13 5A 527*4882a593Smuzhiyun 23 00 02 0F 94 528*4882a593Smuzhiyun 23 00 02 3B 5A 529*4882a593Smuzhiyun 23 00 02 37 94 530*4882a593Smuzhiyun 23 00 02 64 5A 531*4882a593Smuzhiyun 23 00 02 60 94 532*4882a593Smuzhiyun 23 00 02 8A 5A 533*4882a593Smuzhiyun 23 00 02 86 94 534*4882a593Smuzhiyun 23 00 02 B2 5A 535*4882a593Smuzhiyun 23 00 02 AE 94 536*4882a593Smuzhiyun 23 00 02 D8 5A 537*4882a593Smuzhiyun 23 00 02 D4 94 538*4882a593Smuzhiyun 23 00 02 10 D1 539*4882a593Smuzhiyun 23 00 02 38 D1 540*4882a593Smuzhiyun 23 00 02 61 D1 541*4882a593Smuzhiyun 23 00 02 87 D1 542*4882a593Smuzhiyun 23 00 02 AF D1 543*4882a593Smuzhiyun 23 00 02 D5 D1 544*4882a593Smuzhiyun 23 00 02 11 04 545*4882a593Smuzhiyun 23 00 02 39 04 546*4882a593Smuzhiyun 23 00 02 62 04 547*4882a593Smuzhiyun 23 00 02 88 04 548*4882a593Smuzhiyun 23 00 02 B0 04 549*4882a593Smuzhiyun 23 00 02 D6 04 550*4882a593Smuzhiyun 23 00 02 12 05 551*4882a593Smuzhiyun 23 00 02 3A 05 552*4882a593Smuzhiyun 23 00 02 63 05 553*4882a593Smuzhiyun 23 00 02 89 05 554*4882a593Smuzhiyun 23 00 02 B1 05 555*4882a593Smuzhiyun 23 00 02 D7 05 556*4882a593Smuzhiyun 23 00 02 18 AA 557*4882a593Smuzhiyun 23 00 02 14 36 558*4882a593Smuzhiyun 23 00 02 42 AA 559*4882a593Smuzhiyun 23 00 02 3D 36 560*4882a593Smuzhiyun 23 00 02 69 AA 561*4882a593Smuzhiyun 23 00 02 65 36 562*4882a593Smuzhiyun 23 00 02 8F AA 563*4882a593Smuzhiyun 23 00 02 8B 36 564*4882a593Smuzhiyun 23 00 02 B7 AA 565*4882a593Smuzhiyun 23 00 02 B3 36 566*4882a593Smuzhiyun 23 00 02 DD AA 567*4882a593Smuzhiyun 23 00 02 D9 36 568*4882a593Smuzhiyun 23 00 02 15 74 569*4882a593Smuzhiyun 23 00 02 3F 74 570*4882a593Smuzhiyun 23 00 02 66 74 571*4882a593Smuzhiyun 23 00 02 8C 74 572*4882a593Smuzhiyun 23 00 02 B4 74 573*4882a593Smuzhiyun 23 00 02 DA 74 574*4882a593Smuzhiyun 23 00 02 16 9F 575*4882a593Smuzhiyun 23 00 02 40 9F 576*4882a593Smuzhiyun 23 00 02 67 9F 577*4882a593Smuzhiyun 23 00 02 8D 9F 578*4882a593Smuzhiyun 23 00 02 B5 9F 579*4882a593Smuzhiyun 23 00 02 DB 9F 580*4882a593Smuzhiyun 23 00 02 17 DC 581*4882a593Smuzhiyun 23 00 02 41 DC 582*4882a593Smuzhiyun 23 00 02 68 DC 583*4882a593Smuzhiyun 23 00 02 8E DC 584*4882a593Smuzhiyun 23 00 02 B6 DC 585*4882a593Smuzhiyun 23 00 02 DC DC 586*4882a593Smuzhiyun 23 00 02 1D FF 587*4882a593Smuzhiyun 23 00 02 19 03 588*4882a593Smuzhiyun 23 00 02 47 FF 589*4882a593Smuzhiyun 23 00 02 43 03 590*4882a593Smuzhiyun 23 00 02 6E FF 591*4882a593Smuzhiyun 23 00 02 6A 03 592*4882a593Smuzhiyun 23 00 02 94 FF 593*4882a593Smuzhiyun 23 00 02 90 03 594*4882a593Smuzhiyun 23 00 02 BC FF 595*4882a593Smuzhiyun 23 00 02 B8 03 596*4882a593Smuzhiyun 23 00 02 E2 FF 597*4882a593Smuzhiyun 23 00 02 DE 03 598*4882a593Smuzhiyun 23 00 02 1A 35 599*4882a593Smuzhiyun 23 00 02 44 35 600*4882a593Smuzhiyun 23 00 02 6B 35 601*4882a593Smuzhiyun 23 00 02 91 35 602*4882a593Smuzhiyun 23 00 02 B9 35 603*4882a593Smuzhiyun 23 00 02 DF 35 604*4882a593Smuzhiyun 23 00 02 1B 45 605*4882a593Smuzhiyun 23 00 02 45 45 606*4882a593Smuzhiyun 23 00 02 6C 45 607*4882a593Smuzhiyun 23 00 02 92 45 608*4882a593Smuzhiyun 23 00 02 BA 45 609*4882a593Smuzhiyun 23 00 02 E0 45 610*4882a593Smuzhiyun 23 00 02 1C 55 611*4882a593Smuzhiyun 23 00 02 46 55 612*4882a593Smuzhiyun 23 00 02 6D 55 613*4882a593Smuzhiyun 23 00 02 93 55 614*4882a593Smuzhiyun 23 00 02 BB 55 615*4882a593Smuzhiyun 23 00 02 E1 55 616*4882a593Smuzhiyun 23 00 02 22 FF 617*4882a593Smuzhiyun 23 00 02 1E 68 618*4882a593Smuzhiyun 23 00 02 4C FF 619*4882a593Smuzhiyun 23 00 02 48 68 620*4882a593Smuzhiyun 23 00 02 73 FF 621*4882a593Smuzhiyun 23 00 02 6F 68 622*4882a593Smuzhiyun 23 00 02 99 FF 623*4882a593Smuzhiyun 23 00 02 95 68 624*4882a593Smuzhiyun 23 00 02 C1 FF 625*4882a593Smuzhiyun 23 00 02 BD 68 626*4882a593Smuzhiyun 23 00 02 E7 FF 627*4882a593Smuzhiyun 23 00 02 E3 68 628*4882a593Smuzhiyun 23 00 02 1F 7E 629*4882a593Smuzhiyun 23 00 02 49 7E 630*4882a593Smuzhiyun 23 00 02 70 7E 631*4882a593Smuzhiyun 23 00 02 96 7E 632*4882a593Smuzhiyun 23 00 02 BE 7E 633*4882a593Smuzhiyun 23 00 02 E4 7E 634*4882a593Smuzhiyun 23 00 02 20 97 635*4882a593Smuzhiyun 23 00 02 4A 97 636*4882a593Smuzhiyun 23 00 02 71 97 637*4882a593Smuzhiyun 23 00 02 97 97 638*4882a593Smuzhiyun 23 00 02 BF 97 639*4882a593Smuzhiyun 23 00 02 E5 97 640*4882a593Smuzhiyun 23 00 02 21 B5 641*4882a593Smuzhiyun 23 00 02 4B B5 642*4882a593Smuzhiyun 23 00 02 72 B5 643*4882a593Smuzhiyun 23 00 02 98 B5 644*4882a593Smuzhiyun 23 00 02 C0 B5 645*4882a593Smuzhiyun 23 00 02 E6 B5 646*4882a593Smuzhiyun 23 00 02 25 F0 647*4882a593Smuzhiyun 23 00 02 23 E8 648*4882a593Smuzhiyun 23 00 02 4F F0 649*4882a593Smuzhiyun 23 00 02 4D E8 650*4882a593Smuzhiyun 23 00 02 76 F0 651*4882a593Smuzhiyun 23 00 02 74 E8 652*4882a593Smuzhiyun 23 00 02 9C F0 653*4882a593Smuzhiyun 23 00 02 9A E8 654*4882a593Smuzhiyun 23 00 02 C4 F0 655*4882a593Smuzhiyun 23 00 02 C2 E8 656*4882a593Smuzhiyun 23 00 02 EA F0 657*4882a593Smuzhiyun 23 00 02 E8 E8 658*4882a593Smuzhiyun 23 00 02 24 FF 659*4882a593Smuzhiyun 23 00 02 4E FF 660*4882a593Smuzhiyun 23 00 02 75 FF 661*4882a593Smuzhiyun 23 00 02 9B FF 662*4882a593Smuzhiyun 23 00 02 C3 FF 663*4882a593Smuzhiyun 23 00 02 E9 FF 664*4882a593Smuzhiyun 23 00 02 FE 3D 665*4882a593Smuzhiyun 23 00 02 00 04 666*4882a593Smuzhiyun 23 00 02 FE 23 667*4882a593Smuzhiyun 23 00 02 08 82 668*4882a593Smuzhiyun 23 00 02 0A 00 669*4882a593Smuzhiyun 23 00 02 0B 00 670*4882a593Smuzhiyun 23 00 02 0C 01 671*4882a593Smuzhiyun 23 00 02 16 00 672*4882a593Smuzhiyun 23 00 02 18 02 673*4882a593Smuzhiyun 23 00 02 1B 04 674*4882a593Smuzhiyun 23 00 02 19 04 675*4882a593Smuzhiyun 23 00 02 1C 81 676*4882a593Smuzhiyun 23 00 02 1F 00 677*4882a593Smuzhiyun 23 00 02 20 03 678*4882a593Smuzhiyun 23 00 02 23 04 679*4882a593Smuzhiyun 23 00 02 21 01 680*4882a593Smuzhiyun 23 00 02 54 63 681*4882a593Smuzhiyun 23 00 02 55 54 682*4882a593Smuzhiyun 23 00 02 6E 45 683*4882a593Smuzhiyun 23 00 02 6D 36 684*4882a593Smuzhiyun 23 00 02 FE 3D 685*4882a593Smuzhiyun 23 00 02 55 78 686*4882a593Smuzhiyun 23 00 02 FE 20 687*4882a593Smuzhiyun 23 00 02 26 30 688*4882a593Smuzhiyun 23 00 02 FE 3D 689*4882a593Smuzhiyun 23 00 02 20 71 690*4882a593Smuzhiyun 23 00 02 50 8F 691*4882a593Smuzhiyun 23 00 02 51 8F 692*4882a593Smuzhiyun 23 00 02 FE 00 693*4882a593Smuzhiyun 23 00 02 35 00 694*4882a593Smuzhiyun 05 78 01 11 695*4882a593Smuzhiyun 05 1E 01 29 696*4882a593Smuzhiyun ]; 697*4882a593Smuzhiyun 698*4882a593Smuzhiyun panel-exit-sequence = [ 699*4882a593Smuzhiyun 05 00 01 28 700*4882a593Smuzhiyun 05 00 01 10 701*4882a593Smuzhiyun ]; 702*4882a593Smuzhiyun 703*4882a593Smuzhiyun disp_timings0: display-timings { 704*4882a593Smuzhiyun native-mode = <&dsi0_timing0>; 705*4882a593Smuzhiyun dsi0_timing0: timing0 { 706*4882a593Smuzhiyun clock-frequency = <132000000>; 707*4882a593Smuzhiyun hactive = <1080>; 708*4882a593Smuzhiyun vactive = <1920>; 709*4882a593Smuzhiyun hfront-porch = <15>; 710*4882a593Smuzhiyun hsync-len = <2>; 711*4882a593Smuzhiyun hback-porch = <30>; 712*4882a593Smuzhiyun vfront-porch = <15>; 713*4882a593Smuzhiyun vsync-len = <2>; 714*4882a593Smuzhiyun vback-porch = <15>; 715*4882a593Smuzhiyun hsync-active = <0>; 716*4882a593Smuzhiyun vsync-active = <0>; 717*4882a593Smuzhiyun de-active = <0>; 718*4882a593Smuzhiyun pixelclk-active = <1>; 719*4882a593Smuzhiyun }; 720*4882a593Smuzhiyun }; 721*4882a593Smuzhiyun 722*4882a593Smuzhiyun ports { 723*4882a593Smuzhiyun #address-cells = <1>; 724*4882a593Smuzhiyun #size-cells = <0>; 725*4882a593Smuzhiyun 726*4882a593Smuzhiyun port@0 { 727*4882a593Smuzhiyun reg = <0>; 728*4882a593Smuzhiyun panel_in_dsi: endpoint { 729*4882a593Smuzhiyun remote-endpoint = <&dsi_out_panel>; 730*4882a593Smuzhiyun }; 731*4882a593Smuzhiyun }; 732*4882a593Smuzhiyun }; 733*4882a593Smuzhiyun }; 734*4882a593Smuzhiyun 735*4882a593Smuzhiyun ports { 736*4882a593Smuzhiyun #address-cells = <1>; 737*4882a593Smuzhiyun #size-cells = <0>; 738*4882a593Smuzhiyun 739*4882a593Smuzhiyun port@1 { 740*4882a593Smuzhiyun reg = <1>; 741*4882a593Smuzhiyun dsi_out_panel: endpoint { 742*4882a593Smuzhiyun remote-endpoint = <&panel_in_dsi>; 743*4882a593Smuzhiyun }; 744*4882a593Smuzhiyun }; 745*4882a593Smuzhiyun }; 746*4882a593Smuzhiyun 747*4882a593Smuzhiyun}; 748*4882a593Smuzhiyun 749*4882a593Smuzhiyun&dsi1 { 750*4882a593Smuzhiyun status = "disabled"; 751*4882a593Smuzhiyun //rockchip,lane-rate = <1000>; 752*4882a593Smuzhiyun dsi1_panel: panel@0 { 753*4882a593Smuzhiyun status = "okay"; 754*4882a593Smuzhiyun compatible = "simple-panel-dsi"; 755*4882a593Smuzhiyun reg = <0>; 756*4882a593Smuzhiyun backlight = <&backlight1>; 757*4882a593Smuzhiyun reset-delay-ms = <60>; 758*4882a593Smuzhiyun enable-delay-ms = <60>; 759*4882a593Smuzhiyun prepare-delay-ms = <60>; 760*4882a593Smuzhiyun unprepare-delay-ms = <60>; 761*4882a593Smuzhiyun disable-delay-ms = <60>; 762*4882a593Smuzhiyun dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 763*4882a593Smuzhiyun MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; 764*4882a593Smuzhiyun dsi,format = <MIPI_DSI_FMT_RGB888>; 765*4882a593Smuzhiyun dsi,lanes = <4>; 766*4882a593Smuzhiyun panel-init-sequence = [ 767*4882a593Smuzhiyun 23 00 02 FE 21 768*4882a593Smuzhiyun 23 00 02 04 00 769*4882a593Smuzhiyun 23 00 02 00 64 770*4882a593Smuzhiyun 23 00 02 2A 00 771*4882a593Smuzhiyun 23 00 02 26 64 772*4882a593Smuzhiyun 23 00 02 54 00 773*4882a593Smuzhiyun 23 00 02 50 64 774*4882a593Smuzhiyun 23 00 02 7B 00 775*4882a593Smuzhiyun 23 00 02 77 64 776*4882a593Smuzhiyun 23 00 02 A2 00 777*4882a593Smuzhiyun 23 00 02 9D 64 778*4882a593Smuzhiyun 23 00 02 C9 00 779*4882a593Smuzhiyun 23 00 02 C5 64 780*4882a593Smuzhiyun 23 00 02 01 71 781*4882a593Smuzhiyun 23 00 02 27 71 782*4882a593Smuzhiyun 23 00 02 51 71 783*4882a593Smuzhiyun 23 00 02 78 71 784*4882a593Smuzhiyun 23 00 02 9E 71 785*4882a593Smuzhiyun 23 00 02 C6 71 786*4882a593Smuzhiyun 23 00 02 02 89 787*4882a593Smuzhiyun 23 00 02 28 89 788*4882a593Smuzhiyun 23 00 02 52 89 789*4882a593Smuzhiyun 23 00 02 79 89 790*4882a593Smuzhiyun 23 00 02 9F 89 791*4882a593Smuzhiyun 23 00 02 C7 89 792*4882a593Smuzhiyun 23 00 02 03 9E 793*4882a593Smuzhiyun 23 00 02 29 9E 794*4882a593Smuzhiyun 23 00 02 53 9E 795*4882a593Smuzhiyun 23 00 02 7A 9E 796*4882a593Smuzhiyun 23 00 02 A0 9E 797*4882a593Smuzhiyun 23 00 02 C8 9E 798*4882a593Smuzhiyun 23 00 02 09 00 799*4882a593Smuzhiyun 23 00 02 05 B0 800*4882a593Smuzhiyun 23 00 02 31 00 801*4882a593Smuzhiyun 23 00 02 2B B0 802*4882a593Smuzhiyun 23 00 02 5A 00 803*4882a593Smuzhiyun 23 00 02 55 B0 804*4882a593Smuzhiyun 23 00 02 80 00 805*4882a593Smuzhiyun 23 00 02 7C B0 806*4882a593Smuzhiyun 23 00 02 A7 00 807*4882a593Smuzhiyun 23 00 02 A3 B0 808*4882a593Smuzhiyun 23 00 02 CE 00 809*4882a593Smuzhiyun 23 00 02 CA B0 810*4882a593Smuzhiyun 23 00 02 06 C0 811*4882a593Smuzhiyun 23 00 02 2D C0 812*4882a593Smuzhiyun 23 00 02 56 C0 813*4882a593Smuzhiyun 23 00 02 7D C0 814*4882a593Smuzhiyun 23 00 02 A4 C0 815*4882a593Smuzhiyun 23 00 02 CB C0 816*4882a593Smuzhiyun 23 00 02 07 CF 817*4882a593Smuzhiyun 23 00 02 2F CF 818*4882a593Smuzhiyun 23 00 02 58 CF 819*4882a593Smuzhiyun 23 00 02 7E CF 820*4882a593Smuzhiyun 23 00 02 A5 CF 821*4882a593Smuzhiyun 23 00 02 CC CF 822*4882a593Smuzhiyun 23 00 02 08 DD 823*4882a593Smuzhiyun 23 00 02 30 DD 824*4882a593Smuzhiyun 23 00 02 59 DD 825*4882a593Smuzhiyun 23 00 02 7F DD 826*4882a593Smuzhiyun 23 00 02 A6 DD 827*4882a593Smuzhiyun 23 00 02 CD DD 828*4882a593Smuzhiyun 23 00 02 0E 15 829*4882a593Smuzhiyun 23 00 02 0A E9 830*4882a593Smuzhiyun 23 00 02 36 15 831*4882a593Smuzhiyun 23 00 02 32 E9 832*4882a593Smuzhiyun 23 00 02 5F 15 833*4882a593Smuzhiyun 23 00 02 5B E9 834*4882a593Smuzhiyun 23 00 02 85 15 835*4882a593Smuzhiyun 23 00 02 81 E9 836*4882a593Smuzhiyun 23 00 02 AD 15 837*4882a593Smuzhiyun 23 00 02 A9 E9 838*4882a593Smuzhiyun 23 00 02 D3 15 839*4882a593Smuzhiyun 23 00 02 CF E9 840*4882a593Smuzhiyun 23 00 02 0B 14 841*4882a593Smuzhiyun 23 00 02 33 14 842*4882a593Smuzhiyun 23 00 02 5C 14 843*4882a593Smuzhiyun 23 00 02 82 14 844*4882a593Smuzhiyun 23 00 02 AA 14 845*4882a593Smuzhiyun 23 00 02 D0 14 846*4882a593Smuzhiyun 23 00 02 0C 36 847*4882a593Smuzhiyun 23 00 02 34 36 848*4882a593Smuzhiyun 23 00 02 5D 36 849*4882a593Smuzhiyun 23 00 02 83 36 850*4882a593Smuzhiyun 23 00 02 AB 36 851*4882a593Smuzhiyun 23 00 02 D1 36 852*4882a593Smuzhiyun 23 00 02 0D 6B 853*4882a593Smuzhiyun 23 00 02 35 6B 854*4882a593Smuzhiyun 23 00 02 5E 6B 855*4882a593Smuzhiyun 23 00 02 84 6B 856*4882a593Smuzhiyun 23 00 02 AC 6B 857*4882a593Smuzhiyun 23 00 02 D2 6B 858*4882a593Smuzhiyun 23 00 02 13 5A 859*4882a593Smuzhiyun 23 00 02 0F 94 860*4882a593Smuzhiyun 23 00 02 3B 5A 861*4882a593Smuzhiyun 23 00 02 37 94 862*4882a593Smuzhiyun 23 00 02 64 5A 863*4882a593Smuzhiyun 23 00 02 60 94 864*4882a593Smuzhiyun 23 00 02 8A 5A 865*4882a593Smuzhiyun 23 00 02 86 94 866*4882a593Smuzhiyun 23 00 02 B2 5A 867*4882a593Smuzhiyun 23 00 02 AE 94 868*4882a593Smuzhiyun 23 00 02 D8 5A 869*4882a593Smuzhiyun 23 00 02 D4 94 870*4882a593Smuzhiyun 23 00 02 10 D1 871*4882a593Smuzhiyun 23 00 02 38 D1 872*4882a593Smuzhiyun 23 00 02 61 D1 873*4882a593Smuzhiyun 23 00 02 87 D1 874*4882a593Smuzhiyun 23 00 02 AF D1 875*4882a593Smuzhiyun 23 00 02 D5 D1 876*4882a593Smuzhiyun 23 00 02 11 04 877*4882a593Smuzhiyun 23 00 02 39 04 878*4882a593Smuzhiyun 23 00 02 62 04 879*4882a593Smuzhiyun 23 00 02 88 04 880*4882a593Smuzhiyun 23 00 02 B0 04 881*4882a593Smuzhiyun 23 00 02 D6 04 882*4882a593Smuzhiyun 23 00 02 12 05 883*4882a593Smuzhiyun 23 00 02 3A 05 884*4882a593Smuzhiyun 23 00 02 63 05 885*4882a593Smuzhiyun 23 00 02 89 05 886*4882a593Smuzhiyun 23 00 02 B1 05 887*4882a593Smuzhiyun 23 00 02 D7 05 888*4882a593Smuzhiyun 23 00 02 18 AA 889*4882a593Smuzhiyun 23 00 02 14 36 890*4882a593Smuzhiyun 23 00 02 42 AA 891*4882a593Smuzhiyun 23 00 02 3D 36 892*4882a593Smuzhiyun 23 00 02 69 AA 893*4882a593Smuzhiyun 23 00 02 65 36 894*4882a593Smuzhiyun 23 00 02 8F AA 895*4882a593Smuzhiyun 23 00 02 8B 36 896*4882a593Smuzhiyun 23 00 02 B7 AA 897*4882a593Smuzhiyun 23 00 02 B3 36 898*4882a593Smuzhiyun 23 00 02 DD AA 899*4882a593Smuzhiyun 23 00 02 D9 36 900*4882a593Smuzhiyun 23 00 02 15 74 901*4882a593Smuzhiyun 23 00 02 3F 74 902*4882a593Smuzhiyun 23 00 02 66 74 903*4882a593Smuzhiyun 23 00 02 8C 74 904*4882a593Smuzhiyun 23 00 02 B4 74 905*4882a593Smuzhiyun 23 00 02 DA 74 906*4882a593Smuzhiyun 23 00 02 16 9F 907*4882a593Smuzhiyun 23 00 02 40 9F 908*4882a593Smuzhiyun 23 00 02 67 9F 909*4882a593Smuzhiyun 23 00 02 8D 9F 910*4882a593Smuzhiyun 23 00 02 B5 9F 911*4882a593Smuzhiyun 23 00 02 DB 9F 912*4882a593Smuzhiyun 23 00 02 17 DC 913*4882a593Smuzhiyun 23 00 02 41 DC 914*4882a593Smuzhiyun 23 00 02 68 DC 915*4882a593Smuzhiyun 23 00 02 8E DC 916*4882a593Smuzhiyun 23 00 02 B6 DC 917*4882a593Smuzhiyun 23 00 02 DC DC 918*4882a593Smuzhiyun 23 00 02 1D FF 919*4882a593Smuzhiyun 23 00 02 19 03 920*4882a593Smuzhiyun 23 00 02 47 FF 921*4882a593Smuzhiyun 23 00 02 43 03 922*4882a593Smuzhiyun 23 00 02 6E FF 923*4882a593Smuzhiyun 23 00 02 6A 03 924*4882a593Smuzhiyun 23 00 02 94 FF 925*4882a593Smuzhiyun 23 00 02 90 03 926*4882a593Smuzhiyun 23 00 02 BC FF 927*4882a593Smuzhiyun 23 00 02 B8 03 928*4882a593Smuzhiyun 23 00 02 E2 FF 929*4882a593Smuzhiyun 23 00 02 DE 03 930*4882a593Smuzhiyun 23 00 02 1A 35 931*4882a593Smuzhiyun 23 00 02 44 35 932*4882a593Smuzhiyun 23 00 02 6B 35 933*4882a593Smuzhiyun 23 00 02 91 35 934*4882a593Smuzhiyun 23 00 02 B9 35 935*4882a593Smuzhiyun 23 00 02 DF 35 936*4882a593Smuzhiyun 23 00 02 1B 45 937*4882a593Smuzhiyun 23 00 02 45 45 938*4882a593Smuzhiyun 23 00 02 6C 45 939*4882a593Smuzhiyun 23 00 02 92 45 940*4882a593Smuzhiyun 23 00 02 BA 45 941*4882a593Smuzhiyun 23 00 02 E0 45 942*4882a593Smuzhiyun 23 00 02 1C 55 943*4882a593Smuzhiyun 23 00 02 46 55 944*4882a593Smuzhiyun 23 00 02 6D 55 945*4882a593Smuzhiyun 23 00 02 93 55 946*4882a593Smuzhiyun 23 00 02 BB 55 947*4882a593Smuzhiyun 23 00 02 E1 55 948*4882a593Smuzhiyun 23 00 02 22 FF 949*4882a593Smuzhiyun 23 00 02 1E 68 950*4882a593Smuzhiyun 23 00 02 4C FF 951*4882a593Smuzhiyun 23 00 02 48 68 952*4882a593Smuzhiyun 23 00 02 73 FF 953*4882a593Smuzhiyun 23 00 02 6F 68 954*4882a593Smuzhiyun 23 00 02 99 FF 955*4882a593Smuzhiyun 23 00 02 95 68 956*4882a593Smuzhiyun 23 00 02 C1 FF 957*4882a593Smuzhiyun 23 00 02 BD 68 958*4882a593Smuzhiyun 23 00 02 E7 FF 959*4882a593Smuzhiyun 23 00 02 E3 68 960*4882a593Smuzhiyun 23 00 02 1F 7E 961*4882a593Smuzhiyun 23 00 02 49 7E 962*4882a593Smuzhiyun 23 00 02 70 7E 963*4882a593Smuzhiyun 23 00 02 96 7E 964*4882a593Smuzhiyun 23 00 02 BE 7E 965*4882a593Smuzhiyun 23 00 02 E4 7E 966*4882a593Smuzhiyun 23 00 02 20 97 967*4882a593Smuzhiyun 23 00 02 4A 97 968*4882a593Smuzhiyun 23 00 02 71 97 969*4882a593Smuzhiyun 23 00 02 97 97 970*4882a593Smuzhiyun 23 00 02 BF 97 971*4882a593Smuzhiyun 23 00 02 E5 97 972*4882a593Smuzhiyun 23 00 02 21 B5 973*4882a593Smuzhiyun 23 00 02 4B B5 974*4882a593Smuzhiyun 23 00 02 72 B5 975*4882a593Smuzhiyun 23 00 02 98 B5 976*4882a593Smuzhiyun 23 00 02 C0 B5 977*4882a593Smuzhiyun 23 00 02 E6 B5 978*4882a593Smuzhiyun 23 00 02 25 F0 979*4882a593Smuzhiyun 23 00 02 23 E8 980*4882a593Smuzhiyun 23 00 02 4F F0 981*4882a593Smuzhiyun 23 00 02 4D E8 982*4882a593Smuzhiyun 23 00 02 76 F0 983*4882a593Smuzhiyun 23 00 02 74 E8 984*4882a593Smuzhiyun 23 00 02 9C F0 985*4882a593Smuzhiyun 23 00 02 9A E8 986*4882a593Smuzhiyun 23 00 02 C4 F0 987*4882a593Smuzhiyun 23 00 02 C2 E8 988*4882a593Smuzhiyun 23 00 02 EA F0 989*4882a593Smuzhiyun 23 00 02 E8 E8 990*4882a593Smuzhiyun 23 00 02 24 FF 991*4882a593Smuzhiyun 23 00 02 4E FF 992*4882a593Smuzhiyun 23 00 02 75 FF 993*4882a593Smuzhiyun 23 00 02 9B FF 994*4882a593Smuzhiyun 23 00 02 C3 FF 995*4882a593Smuzhiyun 23 00 02 E9 FF 996*4882a593Smuzhiyun 23 00 02 FE 3D 997*4882a593Smuzhiyun 23 00 02 00 04 998*4882a593Smuzhiyun 23 00 02 FE 23 999*4882a593Smuzhiyun 23 00 02 08 82 1000*4882a593Smuzhiyun 23 00 02 0A 00 1001*4882a593Smuzhiyun 23 00 02 0B 00 1002*4882a593Smuzhiyun 23 00 02 0C 01 1003*4882a593Smuzhiyun 23 00 02 16 00 1004*4882a593Smuzhiyun 23 00 02 18 02 1005*4882a593Smuzhiyun 23 00 02 1B 04 1006*4882a593Smuzhiyun 23 00 02 19 04 1007*4882a593Smuzhiyun 23 00 02 1C 81 1008*4882a593Smuzhiyun 23 00 02 1F 00 1009*4882a593Smuzhiyun 23 00 02 20 03 1010*4882a593Smuzhiyun 23 00 02 23 04 1011*4882a593Smuzhiyun 23 00 02 21 01 1012*4882a593Smuzhiyun 23 00 02 54 63 1013*4882a593Smuzhiyun 23 00 02 55 54 1014*4882a593Smuzhiyun 23 00 02 6E 45 1015*4882a593Smuzhiyun 23 00 02 6D 36 1016*4882a593Smuzhiyun 23 00 02 FE 3D 1017*4882a593Smuzhiyun 23 00 02 55 78 1018*4882a593Smuzhiyun 23 00 02 FE 20 1019*4882a593Smuzhiyun 23 00 02 26 30 1020*4882a593Smuzhiyun 23 00 02 FE 3D 1021*4882a593Smuzhiyun 23 00 02 20 71 1022*4882a593Smuzhiyun 23 00 02 50 8F 1023*4882a593Smuzhiyun 23 00 02 51 8F 1024*4882a593Smuzhiyun 23 00 02 FE 00 1025*4882a593Smuzhiyun 23 00 02 35 00 1026*4882a593Smuzhiyun 05 78 01 11 1027*4882a593Smuzhiyun 05 1E 01 29 1028*4882a593Smuzhiyun ]; 1029*4882a593Smuzhiyun 1030*4882a593Smuzhiyun panel-exit-sequence = [ 1031*4882a593Smuzhiyun 05 00 01 28 1032*4882a593Smuzhiyun 05 00 01 10 1033*4882a593Smuzhiyun ]; 1034*4882a593Smuzhiyun 1035*4882a593Smuzhiyun disp_timings1: display-timings { 1036*4882a593Smuzhiyun native-mode = <&dsi1_timing0>; 1037*4882a593Smuzhiyun dsi1_timing0: timing0 { 1038*4882a593Smuzhiyun clock-frequency = <132000000>; 1039*4882a593Smuzhiyun hactive = <1080>; 1040*4882a593Smuzhiyun vactive = <1920>; 1041*4882a593Smuzhiyun hfront-porch = <15>; 1042*4882a593Smuzhiyun hsync-len = <2>; 1043*4882a593Smuzhiyun hback-porch = <30>; 1044*4882a593Smuzhiyun vfront-porch = <15>; 1045*4882a593Smuzhiyun vsync-len = <2>; 1046*4882a593Smuzhiyun vback-porch = <15>; 1047*4882a593Smuzhiyun hsync-active = <0>; 1048*4882a593Smuzhiyun vsync-active = <0>; 1049*4882a593Smuzhiyun de-active = <0>; 1050*4882a593Smuzhiyun pixelclk-active = <1>; 1051*4882a593Smuzhiyun }; 1052*4882a593Smuzhiyun }; 1053*4882a593Smuzhiyun 1054*4882a593Smuzhiyun ports { 1055*4882a593Smuzhiyun #address-cells = <1>; 1056*4882a593Smuzhiyun #size-cells = <0>; 1057*4882a593Smuzhiyun 1058*4882a593Smuzhiyun port@0 { 1059*4882a593Smuzhiyun reg = <0>; 1060*4882a593Smuzhiyun panel_in_dsi1: endpoint { 1061*4882a593Smuzhiyun remote-endpoint = <&dsi1_out_panel>; 1062*4882a593Smuzhiyun }; 1063*4882a593Smuzhiyun }; 1064*4882a593Smuzhiyun }; 1065*4882a593Smuzhiyun }; 1066*4882a593Smuzhiyun 1067*4882a593Smuzhiyun ports { 1068*4882a593Smuzhiyun #address-cells = <1>; 1069*4882a593Smuzhiyun #size-cells = <0>; 1070*4882a593Smuzhiyun 1071*4882a593Smuzhiyun port@1 { 1072*4882a593Smuzhiyun reg = <1>; 1073*4882a593Smuzhiyun dsi1_out_panel: endpoint { 1074*4882a593Smuzhiyun remote-endpoint = <&panel_in_dsi1>; 1075*4882a593Smuzhiyun }; 1076*4882a593Smuzhiyun }; 1077*4882a593Smuzhiyun }; 1078*4882a593Smuzhiyun 1079*4882a593Smuzhiyun}; 1080*4882a593Smuzhiyun 1081*4882a593Smuzhiyun&gpu { 1082*4882a593Smuzhiyun mali-supply = <&vdd_gpu>; 1083*4882a593Smuzhiyun status = "okay"; 1084*4882a593Smuzhiyun}; 1085*4882a593Smuzhiyun 1086*4882a593Smuzhiyun&hdmi { 1087*4882a593Smuzhiyun status = "okay"; 1088*4882a593Smuzhiyun rockchip,phy-table = 1089*4882a593Smuzhiyun <92812500 0x8009 0x0000 0x0270>, 1090*4882a593Smuzhiyun <165000000 0x800b 0x0000 0x026d>, 1091*4882a593Smuzhiyun <185625000 0x800b 0x0000 0x01ed>, 1092*4882a593Smuzhiyun <297000000 0x800b 0x0000 0x01ad>, 1093*4882a593Smuzhiyun <594000000 0x8029 0x0000 0x0088>, 1094*4882a593Smuzhiyun <000000000 0x0000 0x0000 0x0000>; 1095*4882a593Smuzhiyun}; 1096*4882a593Smuzhiyun 1097*4882a593Smuzhiyun&hdmi_in_vp0 { 1098*4882a593Smuzhiyun status = "okay"; 1099*4882a593Smuzhiyun}; 1100*4882a593Smuzhiyun 1101*4882a593Smuzhiyun&hdmi_in_vp1 { 1102*4882a593Smuzhiyun status = "disabled"; 1103*4882a593Smuzhiyun}; 1104*4882a593Smuzhiyun 1105*4882a593Smuzhiyun&hdmi_sound { 1106*4882a593Smuzhiyun status = "okay"; 1107*4882a593Smuzhiyun}; 1108*4882a593Smuzhiyun 1109*4882a593Smuzhiyun&i2c0 { 1110*4882a593Smuzhiyun status = "okay"; 1111*4882a593Smuzhiyun 1112*4882a593Smuzhiyun vdd_cpu: tcs4525@1c { 1113*4882a593Smuzhiyun compatible = "tcs,tcs4525"; 1114*4882a593Smuzhiyun reg = <0x1c>; 1115*4882a593Smuzhiyun vin-supply = <&vcc5v0_sys>; 1116*4882a593Smuzhiyun regulator-compatible = "fan53555-reg"; 1117*4882a593Smuzhiyun regulator-name = "vdd_cpu"; 1118*4882a593Smuzhiyun regulator-min-microvolt = <712500>; 1119*4882a593Smuzhiyun regulator-max-microvolt = <1390000>; 1120*4882a593Smuzhiyun regulator-init-microvolt = <900000>; 1121*4882a593Smuzhiyun regulator-ramp-delay = <2300>; 1122*4882a593Smuzhiyun fcs,suspend-voltage-selector = <1>; 1123*4882a593Smuzhiyun regulator-boot-on; 1124*4882a593Smuzhiyun regulator-always-on; 1125*4882a593Smuzhiyun regulator-state-mem { 1126*4882a593Smuzhiyun regulator-off-in-suspend; 1127*4882a593Smuzhiyun }; 1128*4882a593Smuzhiyun }; 1129*4882a593Smuzhiyun 1130*4882a593Smuzhiyun rk809: pmic@20 { 1131*4882a593Smuzhiyun compatible = "rockchip,rk809"; 1132*4882a593Smuzhiyun reg = <0x20>; 1133*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 1134*4882a593Smuzhiyun interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 1135*4882a593Smuzhiyun 1136*4882a593Smuzhiyun pinctrl-names = "default", "pmic-sleep", 1137*4882a593Smuzhiyun "pmic-power-off", "pmic-reset"; 1138*4882a593Smuzhiyun pinctrl-0 = <&pmic_int>; 1139*4882a593Smuzhiyun pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; 1140*4882a593Smuzhiyun pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; 1141*4882a593Smuzhiyun pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; 1142*4882a593Smuzhiyun 1143*4882a593Smuzhiyun rockchip,system-power-controller; 1144*4882a593Smuzhiyun wakeup-source; 1145*4882a593Smuzhiyun #clock-cells = <1>; 1146*4882a593Smuzhiyun clock-output-names = "rk808-clkout1", "rk808-clkout2"; 1147*4882a593Smuzhiyun //fb-inner-reg-idxs = <2>; 1148*4882a593Smuzhiyun /* 1: rst regs (default in codes), 0: rst the pmic */ 1149*4882a593Smuzhiyun pmic-reset-func = <0>; 1150*4882a593Smuzhiyun /* not save the PMIC_POWER_EN register in uboot */ 1151*4882a593Smuzhiyun not-save-power-en = <1>; 1152*4882a593Smuzhiyun 1153*4882a593Smuzhiyun vcc1-supply = <&vcc3v3_sys>; 1154*4882a593Smuzhiyun vcc2-supply = <&vcc3v3_sys>; 1155*4882a593Smuzhiyun vcc3-supply = <&vcc3v3_sys>; 1156*4882a593Smuzhiyun vcc4-supply = <&vcc3v3_sys>; 1157*4882a593Smuzhiyun vcc5-supply = <&vcc3v3_sys>; 1158*4882a593Smuzhiyun vcc6-supply = <&vcc3v3_sys>; 1159*4882a593Smuzhiyun vcc7-supply = <&vcc3v3_sys>; 1160*4882a593Smuzhiyun vcc8-supply = <&vcc3v3_sys>; 1161*4882a593Smuzhiyun vcc9-supply = <&vcc3v3_sys>; 1162*4882a593Smuzhiyun 1163*4882a593Smuzhiyun pwrkey { 1164*4882a593Smuzhiyun status = "okay"; 1165*4882a593Smuzhiyun }; 1166*4882a593Smuzhiyun 1167*4882a593Smuzhiyun pinctrl_rk8xx: pinctrl_rk8xx { 1168*4882a593Smuzhiyun gpio-controller; 1169*4882a593Smuzhiyun #gpio-cells = <2>; 1170*4882a593Smuzhiyun 1171*4882a593Smuzhiyun rk817_slppin_null: rk817_slppin_null { 1172*4882a593Smuzhiyun pins = "gpio_slp"; 1173*4882a593Smuzhiyun function = "pin_fun0"; 1174*4882a593Smuzhiyun }; 1175*4882a593Smuzhiyun 1176*4882a593Smuzhiyun rk817_slppin_slp: rk817_slppin_slp { 1177*4882a593Smuzhiyun pins = "gpio_slp"; 1178*4882a593Smuzhiyun function = "pin_fun1"; 1179*4882a593Smuzhiyun }; 1180*4882a593Smuzhiyun 1181*4882a593Smuzhiyun rk817_slppin_pwrdn: rk817_slppin_pwrdn { 1182*4882a593Smuzhiyun pins = "gpio_slp"; 1183*4882a593Smuzhiyun function = "pin_fun2"; 1184*4882a593Smuzhiyun }; 1185*4882a593Smuzhiyun 1186*4882a593Smuzhiyun rk817_slppin_rst: rk817_slppin_rst { 1187*4882a593Smuzhiyun pins = "gpio_slp"; 1188*4882a593Smuzhiyun function = "pin_fun3"; 1189*4882a593Smuzhiyun }; 1190*4882a593Smuzhiyun }; 1191*4882a593Smuzhiyun 1192*4882a593Smuzhiyun regulators { 1193*4882a593Smuzhiyun vdd_logic: DCDC_REG1 { 1194*4882a593Smuzhiyun regulator-always-on; 1195*4882a593Smuzhiyun regulator-boot-on; 1196*4882a593Smuzhiyun regulator-min-microvolt = <500000>; 1197*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 1198*4882a593Smuzhiyun regulator-init-microvolt = <900000>; 1199*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 1200*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 1201*4882a593Smuzhiyun regulator-name = "vdd_logic"; 1202*4882a593Smuzhiyun regulator-state-mem { 1203*4882a593Smuzhiyun regulator-off-in-suspend; 1204*4882a593Smuzhiyun }; 1205*4882a593Smuzhiyun }; 1206*4882a593Smuzhiyun 1207*4882a593Smuzhiyun vdd_gpu: DCDC_REG2 { 1208*4882a593Smuzhiyun regulator-always-on; 1209*4882a593Smuzhiyun regulator-boot-on; 1210*4882a593Smuzhiyun regulator-min-microvolt = <500000>; 1211*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 1212*4882a593Smuzhiyun regulator-init-microvolt = <900000>; 1213*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 1214*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 1215*4882a593Smuzhiyun regulator-name = "vdd_gpu"; 1216*4882a593Smuzhiyun regulator-state-mem { 1217*4882a593Smuzhiyun regulator-off-in-suspend; 1218*4882a593Smuzhiyun }; 1219*4882a593Smuzhiyun }; 1220*4882a593Smuzhiyun 1221*4882a593Smuzhiyun vcc_ddr: DCDC_REG3 { 1222*4882a593Smuzhiyun regulator-always-on; 1223*4882a593Smuzhiyun regulator-boot-on; 1224*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 1225*4882a593Smuzhiyun regulator-name = "vcc_ddr"; 1226*4882a593Smuzhiyun regulator-state-mem { 1227*4882a593Smuzhiyun regulator-on-in-suspend; 1228*4882a593Smuzhiyun }; 1229*4882a593Smuzhiyun }; 1230*4882a593Smuzhiyun 1231*4882a593Smuzhiyun vdd_npu: DCDC_REG4 { 1232*4882a593Smuzhiyun regulator-always-on; 1233*4882a593Smuzhiyun regulator-boot-on; 1234*4882a593Smuzhiyun regulator-min-microvolt = <500000>; 1235*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 1236*4882a593Smuzhiyun regulator-init-microvolt = <900000>; 1237*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 1238*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 1239*4882a593Smuzhiyun regulator-name = "vdd_npu"; 1240*4882a593Smuzhiyun regulator-state-mem { 1241*4882a593Smuzhiyun regulator-off-in-suspend; 1242*4882a593Smuzhiyun }; 1243*4882a593Smuzhiyun }; 1244*4882a593Smuzhiyun 1245*4882a593Smuzhiyun vdda0v9_image: LDO_REG1 { 1246*4882a593Smuzhiyun regulator-boot-on; 1247*4882a593Smuzhiyun regulator-always-on; 1248*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 1249*4882a593Smuzhiyun regulator-max-microvolt = <900000>; 1250*4882a593Smuzhiyun regulator-name = "vdda0v9_image"; 1251*4882a593Smuzhiyun regulator-state-mem { 1252*4882a593Smuzhiyun regulator-off-in-suspend; 1253*4882a593Smuzhiyun }; 1254*4882a593Smuzhiyun }; 1255*4882a593Smuzhiyun 1256*4882a593Smuzhiyun vdda_0v9: LDO_REG2 { 1257*4882a593Smuzhiyun regulator-always-on; 1258*4882a593Smuzhiyun regulator-boot-on; 1259*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 1260*4882a593Smuzhiyun regulator-max-microvolt = <900000>; 1261*4882a593Smuzhiyun regulator-name = "vdda_0v9"; 1262*4882a593Smuzhiyun regulator-state-mem { 1263*4882a593Smuzhiyun regulator-off-in-suspend; 1264*4882a593Smuzhiyun }; 1265*4882a593Smuzhiyun }; 1266*4882a593Smuzhiyun 1267*4882a593Smuzhiyun vdda0v9_pmu: LDO_REG3 { 1268*4882a593Smuzhiyun regulator-always-on; 1269*4882a593Smuzhiyun regulator-boot-on; 1270*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 1271*4882a593Smuzhiyun regulator-max-microvolt = <900000>; 1272*4882a593Smuzhiyun regulator-name = "vdda0v9_pmu"; 1273*4882a593Smuzhiyun regulator-state-mem { 1274*4882a593Smuzhiyun regulator-on-in-suspend; 1275*4882a593Smuzhiyun regulator-suspend-microvolt = <900000>; 1276*4882a593Smuzhiyun }; 1277*4882a593Smuzhiyun }; 1278*4882a593Smuzhiyun 1279*4882a593Smuzhiyun vccio_acodec: LDO_REG4 { 1280*4882a593Smuzhiyun regulator-always-on; 1281*4882a593Smuzhiyun regulator-boot-on; 1282*4882a593Smuzhiyun regulator-min-microvolt = <3000000>; 1283*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 1284*4882a593Smuzhiyun regulator-name = "vccio_acodec"; 1285*4882a593Smuzhiyun regulator-state-mem { 1286*4882a593Smuzhiyun regulator-off-in-suspend; 1287*4882a593Smuzhiyun }; 1288*4882a593Smuzhiyun }; 1289*4882a593Smuzhiyun 1290*4882a593Smuzhiyun vccio_sd: LDO_REG5 { 1291*4882a593Smuzhiyun regulator-always-on; 1292*4882a593Smuzhiyun regulator-boot-on; 1293*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 1294*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 1295*4882a593Smuzhiyun regulator-name = "vccio_sd"; 1296*4882a593Smuzhiyun regulator-state-mem { 1297*4882a593Smuzhiyun regulator-off-in-suspend; 1298*4882a593Smuzhiyun }; 1299*4882a593Smuzhiyun }; 1300*4882a593Smuzhiyun 1301*4882a593Smuzhiyun vcc3v3_pmu: LDO_REG6 { 1302*4882a593Smuzhiyun regulator-always-on; 1303*4882a593Smuzhiyun regulator-boot-on; 1304*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 1305*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 1306*4882a593Smuzhiyun regulator-name = "vcc3v3_pmu"; 1307*4882a593Smuzhiyun regulator-state-mem { 1308*4882a593Smuzhiyun regulator-on-in-suspend; 1309*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 1310*4882a593Smuzhiyun }; 1311*4882a593Smuzhiyun }; 1312*4882a593Smuzhiyun 1313*4882a593Smuzhiyun vcca_1v8: LDO_REG7 { 1314*4882a593Smuzhiyun regulator-always-on; 1315*4882a593Smuzhiyun regulator-boot-on; 1316*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 1317*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 1318*4882a593Smuzhiyun regulator-name = "vcca_1v8"; 1319*4882a593Smuzhiyun regulator-state-mem { 1320*4882a593Smuzhiyun regulator-off-in-suspend; 1321*4882a593Smuzhiyun }; 1322*4882a593Smuzhiyun }; 1323*4882a593Smuzhiyun 1324*4882a593Smuzhiyun vcca1v8_pmu: LDO_REG8 { 1325*4882a593Smuzhiyun regulator-always-on; 1326*4882a593Smuzhiyun regulator-boot-on; 1327*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 1328*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 1329*4882a593Smuzhiyun regulator-name = "vcca1v8_pmu"; 1330*4882a593Smuzhiyun regulator-state-mem { 1331*4882a593Smuzhiyun regulator-on-in-suspend; 1332*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 1333*4882a593Smuzhiyun }; 1334*4882a593Smuzhiyun }; 1335*4882a593Smuzhiyun 1336*4882a593Smuzhiyun vcca1v8_image: LDO_REG9 { 1337*4882a593Smuzhiyun regulator-always-on; 1338*4882a593Smuzhiyun regulator-boot-on; 1339*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 1340*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 1341*4882a593Smuzhiyun regulator-name = "vcca1v8_image"; 1342*4882a593Smuzhiyun regulator-state-mem { 1343*4882a593Smuzhiyun regulator-off-in-suspend; 1344*4882a593Smuzhiyun }; 1345*4882a593Smuzhiyun }; 1346*4882a593Smuzhiyun 1347*4882a593Smuzhiyun vcc_1v8: DCDC_REG5 { 1348*4882a593Smuzhiyun regulator-always-on; 1349*4882a593Smuzhiyun regulator-boot-on; 1350*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 1351*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 1352*4882a593Smuzhiyun regulator-name = "vcc_1v8"; 1353*4882a593Smuzhiyun regulator-state-mem { 1354*4882a593Smuzhiyun regulator-off-in-suspend; 1355*4882a593Smuzhiyun }; 1356*4882a593Smuzhiyun }; 1357*4882a593Smuzhiyun 1358*4882a593Smuzhiyun vcc_3v3: SWITCH_REG1 { 1359*4882a593Smuzhiyun regulator-always-on; 1360*4882a593Smuzhiyun regulator-boot-on; 1361*4882a593Smuzhiyun regulator-name = "vcc_3v3"; 1362*4882a593Smuzhiyun regulator-state-mem { 1363*4882a593Smuzhiyun regulator-off-in-suspend; 1364*4882a593Smuzhiyun }; 1365*4882a593Smuzhiyun }; 1366*4882a593Smuzhiyun 1367*4882a593Smuzhiyun vcc3v3_sd: SWITCH_REG2 { 1368*4882a593Smuzhiyun regulator-always-on; 1369*4882a593Smuzhiyun regulator-boot-on; 1370*4882a593Smuzhiyun regulator-name = "vcc3v3_sd"; 1371*4882a593Smuzhiyun regulator-state-mem { 1372*4882a593Smuzhiyun regulator-off-in-suspend; 1373*4882a593Smuzhiyun }; 1374*4882a593Smuzhiyun }; 1375*4882a593Smuzhiyun }; 1376*4882a593Smuzhiyun 1377*4882a593Smuzhiyun rk809_codec: codec { 1378*4882a593Smuzhiyun #sound-dai-cells = <1>; 1379*4882a593Smuzhiyun compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; 1380*4882a593Smuzhiyun clocks = <&cru I2S1_MCLKOUT>; 1381*4882a593Smuzhiyun clock-names = "mclk"; 1382*4882a593Smuzhiyun assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; 1383*4882a593Smuzhiyun assigned-clock-rates = <12288000>; 1384*4882a593Smuzhiyun assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; 1385*4882a593Smuzhiyun pinctrl-names = "default"; 1386*4882a593Smuzhiyun pinctrl-0 = <&i2s1m0_mclk>; 1387*4882a593Smuzhiyun hp-volume = <20>; 1388*4882a593Smuzhiyun spk-volume = <3>; 1389*4882a593Smuzhiyun mic-in-differential; 1390*4882a593Smuzhiyun status = "okay"; 1391*4882a593Smuzhiyun }; 1392*4882a593Smuzhiyun }; 1393*4882a593Smuzhiyun}; 1394*4882a593Smuzhiyun 1395*4882a593Smuzhiyun&i2c1 { 1396*4882a593Smuzhiyun status = "okay"; 1397*4882a593Smuzhiyun 1398*4882a593Smuzhiyun gt1x: gt1x@14 { 1399*4882a593Smuzhiyun compatible = "goodix,gt1x"; 1400*4882a593Smuzhiyun reg = <0x14>; 1401*4882a593Smuzhiyun pinctrl-names = "default"; 1402*4882a593Smuzhiyun pinctrl-0 = <&touch_gpio>; 1403*4882a593Smuzhiyun goodix,rst-gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; 1404*4882a593Smuzhiyun goodix,irq-gpio = <&gpio0 RK_PB5 IRQ_TYPE_LEVEL_LOW>; 1405*4882a593Smuzhiyun }; 1406*4882a593Smuzhiyun}; 1407*4882a593Smuzhiyun 1408*4882a593Smuzhiyun&i2c5 { 1409*4882a593Smuzhiyun status = "okay"; 1410*4882a593Smuzhiyun 1411*4882a593Smuzhiyun mxc6655xa: mxc6655xa@15 { 1412*4882a593Smuzhiyun status = "okay"; 1413*4882a593Smuzhiyun compatible = "gs_mxc6655xa"; 1414*4882a593Smuzhiyun pinctrl-names = "default"; 1415*4882a593Smuzhiyun pinctrl-0 = <&mxc6655xa_irq_gpio>; 1416*4882a593Smuzhiyun reg = <0x15>; 1417*4882a593Smuzhiyun irq-gpio = <&gpio3 RK_PC1 IRQ_TYPE_LEVEL_LOW>; 1418*4882a593Smuzhiyun irq_enable = <0>; 1419*4882a593Smuzhiyun poll_delay_ms = <30>; 1420*4882a593Smuzhiyun type = <SENSOR_TYPE_ACCEL>; 1421*4882a593Smuzhiyun power-off-in-suspend = <1>; 1422*4882a593Smuzhiyun layout = <1>; 1423*4882a593Smuzhiyun }; 1424*4882a593Smuzhiyun}; 1425*4882a593Smuzhiyun 1426*4882a593Smuzhiyun&i2s0_8ch { 1427*4882a593Smuzhiyun status = "okay"; 1428*4882a593Smuzhiyun}; 1429*4882a593Smuzhiyun 1430*4882a593Smuzhiyun&i2s1_8ch { 1431*4882a593Smuzhiyun status = "okay"; 1432*4882a593Smuzhiyun rockchip,clk-trcm = <1>; 1433*4882a593Smuzhiyun pinctrl-names = "default"; 1434*4882a593Smuzhiyun pinctrl-0 = <&i2s1m0_sclktx 1435*4882a593Smuzhiyun &i2s1m0_lrcktx 1436*4882a593Smuzhiyun &i2s1m0_sdi0 1437*4882a593Smuzhiyun &i2s1m0_sdo0>; 1438*4882a593Smuzhiyun}; 1439*4882a593Smuzhiyun 1440*4882a593Smuzhiyun&i2s3_2ch { 1441*4882a593Smuzhiyun pinctrl-0 = <&i2s3m0_sclk &i2s3m0_lrck &i2s3m0_sdi &i2s3m0_sdo>; 1442*4882a593Smuzhiyun rockchip,bclk-fs = <32>; 1443*4882a593Smuzhiyun status = "disabled"; 1444*4882a593Smuzhiyun}; 1445*4882a593Smuzhiyun 1446*4882a593Smuzhiyun&iep { 1447*4882a593Smuzhiyun status = "okay"; 1448*4882a593Smuzhiyun}; 1449*4882a593Smuzhiyun 1450*4882a593Smuzhiyun&iep_mmu { 1451*4882a593Smuzhiyun status = "okay"; 1452*4882a593Smuzhiyun}; 1453*4882a593Smuzhiyun 1454*4882a593Smuzhiyun&jpegd { 1455*4882a593Smuzhiyun status = "okay"; 1456*4882a593Smuzhiyun}; 1457*4882a593Smuzhiyun 1458*4882a593Smuzhiyun&jpegd_mmu { 1459*4882a593Smuzhiyun status = "okay"; 1460*4882a593Smuzhiyun}; 1461*4882a593Smuzhiyun 1462*4882a593Smuzhiyun&mpp_srv { 1463*4882a593Smuzhiyun status = "okay"; 1464*4882a593Smuzhiyun}; 1465*4882a593Smuzhiyun 1466*4882a593Smuzhiyun&nandc0 { 1467*4882a593Smuzhiyun #address-cells = <1>; 1468*4882a593Smuzhiyun #size-cells = <0>; 1469*4882a593Smuzhiyun status = "okay"; 1470*4882a593Smuzhiyun 1471*4882a593Smuzhiyun nand@0 { 1472*4882a593Smuzhiyun reg = <0>; 1473*4882a593Smuzhiyun nand-bus-width = <8>; 1474*4882a593Smuzhiyun nand-ecc-mode = "hw"; 1475*4882a593Smuzhiyun nand-ecc-strength = <16>; 1476*4882a593Smuzhiyun nand-ecc-step-size = <1024>; 1477*4882a593Smuzhiyun }; 1478*4882a593Smuzhiyun}; 1479*4882a593Smuzhiyun 1480*4882a593Smuzhiyun&pinctrl { 1481*4882a593Smuzhiyun 1482*4882a593Smuzhiyun headphone { 1483*4882a593Smuzhiyun hp_det: hp-det { 1484*4882a593Smuzhiyun rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>; 1485*4882a593Smuzhiyun }; 1486*4882a593Smuzhiyun }; 1487*4882a593Smuzhiyun 1488*4882a593Smuzhiyun mxc6655xa { 1489*4882a593Smuzhiyun mxc6655xa_irq_gpio: mxc6655xa_irq_gpio { 1490*4882a593Smuzhiyun rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; 1491*4882a593Smuzhiyun }; 1492*4882a593Smuzhiyun }; 1493*4882a593Smuzhiyun 1494*4882a593Smuzhiyun pmic { 1495*4882a593Smuzhiyun pmic_int: pmic_int { 1496*4882a593Smuzhiyun rockchip,pins = 1497*4882a593Smuzhiyun <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; 1498*4882a593Smuzhiyun }; 1499*4882a593Smuzhiyun 1500*4882a593Smuzhiyun soc_slppin_gpio: soc_slppin_gpio { 1501*4882a593Smuzhiyun rockchip,pins = 1502*4882a593Smuzhiyun <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>; 1503*4882a593Smuzhiyun }; 1504*4882a593Smuzhiyun 1505*4882a593Smuzhiyun soc_slppin_slp: soc_slppin_slp { 1506*4882a593Smuzhiyun rockchip,pins = 1507*4882a593Smuzhiyun <0 RK_PA2 1 &pcfg_pull_none>; 1508*4882a593Smuzhiyun }; 1509*4882a593Smuzhiyun 1510*4882a593Smuzhiyun soc_slppin_rst: soc_slppin_rst { 1511*4882a593Smuzhiyun rockchip,pins = 1512*4882a593Smuzhiyun <0 RK_PA2 2 &pcfg_pull_none>; 1513*4882a593Smuzhiyun }; 1514*4882a593Smuzhiyun }; 1515*4882a593Smuzhiyun 1516*4882a593Smuzhiyun touch { 1517*4882a593Smuzhiyun touch_gpio: touch-gpio { 1518*4882a593Smuzhiyun rockchip,pins = 1519*4882a593Smuzhiyun <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, 1520*4882a593Smuzhiyun <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; 1521*4882a593Smuzhiyun }; 1522*4882a593Smuzhiyun }; 1523*4882a593Smuzhiyun 1524*4882a593Smuzhiyun sdio-pwrseq { 1525*4882a593Smuzhiyun wifi_enable_h: wifi-enable-h { 1526*4882a593Smuzhiyun rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; 1527*4882a593Smuzhiyun }; 1528*4882a593Smuzhiyun }; 1529*4882a593Smuzhiyun 1530*4882a593Smuzhiyun usb { 1531*4882a593Smuzhiyun vcc5v0_host_en: vcc5v0-host-en { 1532*4882a593Smuzhiyun rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1533*4882a593Smuzhiyun }; 1534*4882a593Smuzhiyun 1535*4882a593Smuzhiyun vcc5v0_otg_en: vcc5v0-otg-en { 1536*4882a593Smuzhiyun rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 1537*4882a593Smuzhiyun }; 1538*4882a593Smuzhiyun }; 1539*4882a593Smuzhiyun 1540*4882a593Smuzhiyun wireless-bluetooth { 1541*4882a593Smuzhiyun uart8_gpios: uart8-gpios { 1542*4882a593Smuzhiyun rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; 1543*4882a593Smuzhiyun }; 1544*4882a593Smuzhiyun }; 1545*4882a593Smuzhiyun}; 1546*4882a593Smuzhiyun 1547*4882a593Smuzhiyun /* 1548*4882a593Smuzhiyun * There are 10 independent IO domains in RK3566/RK3568, including PMUIO[0:2] and VCCIO[1:7]. 1549*4882a593Smuzhiyun * 1/ PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured; 1550*4882a593Smuzhiyun * 2/ PMUIO2 and VCCIO1,VCCIO[3:7] domains require that their hardware power supply voltages 1551*4882a593Smuzhiyun * must be consistent with the software configuration correspondingly 1552*4882a593Smuzhiyun * a/ When the hardware IO level is connected to 1.8V, the software voltage configuration 1553*4882a593Smuzhiyun * should also be configured to 1.8V accordingly; 1554*4882a593Smuzhiyun * b/ When the hardware IO level is connected to 3.3V, the software voltage configuration 1555*4882a593Smuzhiyun * should also be configured to 3.3V accordingly; 1556*4882a593Smuzhiyun * 3/ VCCIO2 voltage control selection (0xFDC20140) 1557*4882a593Smuzhiyun * BIT[0]: 0x0: from GPIO_0A7 (default) 1558*4882a593Smuzhiyun * BIT[0]: 0x1: from GRF 1559*4882a593Smuzhiyun * Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7: 1560*4882a593Smuzhiyun * L:VCCIO2 must supply 3.3V 1561*4882a593Smuzhiyun * H:VCCIO2 must supply 1.8V 1562*4882a593Smuzhiyun */ 1563*4882a593Smuzhiyun&pmu_io_domains { 1564*4882a593Smuzhiyun status = "okay"; 1565*4882a593Smuzhiyun pmuio2-supply = <&vcc3v3_pmu>; 1566*4882a593Smuzhiyun vccio1-supply = <&vccio_acodec>; 1567*4882a593Smuzhiyun vccio3-supply = <&vccio_sd>; 1568*4882a593Smuzhiyun vccio4-supply = <&vcc_3v3>; 1569*4882a593Smuzhiyun vccio5-supply = <&vcc_3v3>; 1570*4882a593Smuzhiyun vccio6-supply = <&vcc_3v3>; 1571*4882a593Smuzhiyun vccio7-supply = <&vcc_3v3>; 1572*4882a593Smuzhiyun}; 1573*4882a593Smuzhiyun 1574*4882a593Smuzhiyun&pwm4 { 1575*4882a593Smuzhiyun status = "okay"; 1576*4882a593Smuzhiyun}; 1577*4882a593Smuzhiyun 1578*4882a593Smuzhiyun&pwm5 { 1579*4882a593Smuzhiyun status = "okay"; 1580*4882a593Smuzhiyun}; 1581*4882a593Smuzhiyun 1582*4882a593Smuzhiyun&pwm7 { 1583*4882a593Smuzhiyun status = "okay"; 1584*4882a593Smuzhiyun 1585*4882a593Smuzhiyun compatible = "rockchip,remotectl-pwm"; 1586*4882a593Smuzhiyun remote_pwm_id = <3>; 1587*4882a593Smuzhiyun handle_cpu_id = <1>; 1588*4882a593Smuzhiyun remote_support_psci = <0>; 1589*4882a593Smuzhiyun pinctrl-names = "default"; 1590*4882a593Smuzhiyun pinctrl-0 = <&pwm7_pins>; 1591*4882a593Smuzhiyun 1592*4882a593Smuzhiyun ir_key1 { 1593*4882a593Smuzhiyun rockchip,usercode = <0x4040>; 1594*4882a593Smuzhiyun rockchip,key_table = 1595*4882a593Smuzhiyun <0xf2 KEY_REPLY>, 1596*4882a593Smuzhiyun <0xba KEY_BACK>, 1597*4882a593Smuzhiyun <0xf4 KEY_UP>, 1598*4882a593Smuzhiyun <0xf1 KEY_DOWN>, 1599*4882a593Smuzhiyun <0xef KEY_LEFT>, 1600*4882a593Smuzhiyun <0xee KEY_RIGHT>, 1601*4882a593Smuzhiyun <0xbd KEY_HOME>, 1602*4882a593Smuzhiyun <0xea KEY_VOLUMEUP>, 1603*4882a593Smuzhiyun <0xe3 KEY_VOLUMEDOWN>, 1604*4882a593Smuzhiyun <0xe2 KEY_SEARCH>, 1605*4882a593Smuzhiyun <0xb2 KEY_POWER>, 1606*4882a593Smuzhiyun <0xbc KEY_MUTE>, 1607*4882a593Smuzhiyun <0xec KEY_MENU>, 1608*4882a593Smuzhiyun <0xbf 0x190>, 1609*4882a593Smuzhiyun <0xe0 0x191>, 1610*4882a593Smuzhiyun <0xe1 0x192>, 1611*4882a593Smuzhiyun <0xe9 183>, 1612*4882a593Smuzhiyun <0xe6 248>, 1613*4882a593Smuzhiyun <0xe8 185>, 1614*4882a593Smuzhiyun <0xe7 186>, 1615*4882a593Smuzhiyun <0xf0 388>, 1616*4882a593Smuzhiyun <0xbe 0x175>; 1617*4882a593Smuzhiyun }; 1618*4882a593Smuzhiyun 1619*4882a593Smuzhiyun ir_key2 { 1620*4882a593Smuzhiyun rockchip,usercode = <0xff00>; 1621*4882a593Smuzhiyun rockchip,key_table = 1622*4882a593Smuzhiyun <0xf9 KEY_HOME>, 1623*4882a593Smuzhiyun <0xbf KEY_BACK>, 1624*4882a593Smuzhiyun <0xfb KEY_MENU>, 1625*4882a593Smuzhiyun <0xaa KEY_REPLY>, 1626*4882a593Smuzhiyun <0xb9 KEY_UP>, 1627*4882a593Smuzhiyun <0xe9 KEY_DOWN>, 1628*4882a593Smuzhiyun <0xb8 KEY_LEFT>, 1629*4882a593Smuzhiyun <0xea KEY_RIGHT>, 1630*4882a593Smuzhiyun <0xeb KEY_VOLUMEDOWN>, 1631*4882a593Smuzhiyun <0xef KEY_VOLUMEUP>, 1632*4882a593Smuzhiyun <0xf7 KEY_MUTE>, 1633*4882a593Smuzhiyun <0xe7 KEY_POWER>, 1634*4882a593Smuzhiyun <0xfc KEY_POWER>, 1635*4882a593Smuzhiyun <0xa9 KEY_VOLUMEDOWN>, 1636*4882a593Smuzhiyun <0xa8 KEY_VOLUMEDOWN>, 1637*4882a593Smuzhiyun <0xe0 KEY_VOLUMEDOWN>, 1638*4882a593Smuzhiyun <0xa5 KEY_VOLUMEDOWN>, 1639*4882a593Smuzhiyun <0xab 183>, 1640*4882a593Smuzhiyun <0xb7 388>, 1641*4882a593Smuzhiyun <0xe8 388>, 1642*4882a593Smuzhiyun <0xf8 184>, 1643*4882a593Smuzhiyun <0xaf 185>, 1644*4882a593Smuzhiyun <0xed KEY_VOLUMEDOWN>, 1645*4882a593Smuzhiyun <0xee 186>, 1646*4882a593Smuzhiyun <0xb3 KEY_VOLUMEDOWN>, 1647*4882a593Smuzhiyun <0xf1 KEY_VOLUMEDOWN>, 1648*4882a593Smuzhiyun <0xf2 KEY_VOLUMEDOWN>, 1649*4882a593Smuzhiyun <0xf3 KEY_SEARCH>, 1650*4882a593Smuzhiyun <0xb4 KEY_VOLUMEDOWN>, 1651*4882a593Smuzhiyun <0xbe KEY_SEARCH>; 1652*4882a593Smuzhiyun }; 1653*4882a593Smuzhiyun 1654*4882a593Smuzhiyun ir_key3 { 1655*4882a593Smuzhiyun rockchip,usercode = <0x1dcc>; 1656*4882a593Smuzhiyun rockchip,key_table = 1657*4882a593Smuzhiyun <0xee KEY_REPLY>, 1658*4882a593Smuzhiyun <0xf0 KEY_BACK>, 1659*4882a593Smuzhiyun <0xf8 KEY_UP>, 1660*4882a593Smuzhiyun <0xbb KEY_DOWN>, 1661*4882a593Smuzhiyun <0xef KEY_LEFT>, 1662*4882a593Smuzhiyun <0xed KEY_RIGHT>, 1663*4882a593Smuzhiyun <0xfc KEY_HOME>, 1664*4882a593Smuzhiyun <0xf1 KEY_VOLUMEUP>, 1665*4882a593Smuzhiyun <0xfd KEY_VOLUMEDOWN>, 1666*4882a593Smuzhiyun <0xb7 KEY_SEARCH>, 1667*4882a593Smuzhiyun <0xff KEY_POWER>, 1668*4882a593Smuzhiyun <0xf3 KEY_MUTE>, 1669*4882a593Smuzhiyun <0xbf KEY_MENU>, 1670*4882a593Smuzhiyun <0xf9 0x191>, 1671*4882a593Smuzhiyun <0xf5 0x192>, 1672*4882a593Smuzhiyun <0xb3 388>, 1673*4882a593Smuzhiyun <0xbe KEY_1>, 1674*4882a593Smuzhiyun <0xba KEY_2>, 1675*4882a593Smuzhiyun <0xb2 KEY_3>, 1676*4882a593Smuzhiyun <0xbd KEY_4>, 1677*4882a593Smuzhiyun <0xf9 KEY_5>, 1678*4882a593Smuzhiyun <0xb1 KEY_6>, 1679*4882a593Smuzhiyun <0xfc KEY_7>, 1680*4882a593Smuzhiyun <0xf8 KEY_8>, 1681*4882a593Smuzhiyun <0xb0 KEY_9>, 1682*4882a593Smuzhiyun <0xb6 KEY_0>, 1683*4882a593Smuzhiyun <0xb5 KEY_BACKSPACE>; 1684*4882a593Smuzhiyun }; 1685*4882a593Smuzhiyun}; 1686*4882a593Smuzhiyun 1687*4882a593Smuzhiyun&rk_rga { 1688*4882a593Smuzhiyun status = "okay"; 1689*4882a593Smuzhiyun}; 1690*4882a593Smuzhiyun 1691*4882a593Smuzhiyun&rkvdec { 1692*4882a593Smuzhiyun status = "okay"; 1693*4882a593Smuzhiyun}; 1694*4882a593Smuzhiyun 1695*4882a593Smuzhiyun&rkvdec_mmu { 1696*4882a593Smuzhiyun status = "okay"; 1697*4882a593Smuzhiyun}; 1698*4882a593Smuzhiyun 1699*4882a593Smuzhiyun&rkvenc { 1700*4882a593Smuzhiyun venc-supply = <&vdd_logic>; 1701*4882a593Smuzhiyun status = "okay"; 1702*4882a593Smuzhiyun}; 1703*4882a593Smuzhiyun 1704*4882a593Smuzhiyun&rkvenc_mmu { 1705*4882a593Smuzhiyun status = "okay"; 1706*4882a593Smuzhiyun}; 1707*4882a593Smuzhiyun 1708*4882a593Smuzhiyun&rknpu { 1709*4882a593Smuzhiyun rknpu-supply = <&vdd_npu>; 1710*4882a593Smuzhiyun status = "okay"; 1711*4882a593Smuzhiyun}; 1712*4882a593Smuzhiyun 1713*4882a593Smuzhiyun&rknpu_mmu { 1714*4882a593Smuzhiyun status = "okay"; 1715*4882a593Smuzhiyun}; 1716*4882a593Smuzhiyun 1717*4882a593Smuzhiyun&route_hdmi { 1718*4882a593Smuzhiyun status = "okay"; 1719*4882a593Smuzhiyun connect = <&vp0_out_hdmi>; 1720*4882a593Smuzhiyun}; 1721*4882a593Smuzhiyun 1722*4882a593Smuzhiyun&saradc { 1723*4882a593Smuzhiyun status = "okay"; 1724*4882a593Smuzhiyun vref-supply = <&vcca_1v8>; 1725*4882a593Smuzhiyun}; 1726*4882a593Smuzhiyun 1727*4882a593Smuzhiyun&sdhci { 1728*4882a593Smuzhiyun bus-width = <8>; 1729*4882a593Smuzhiyun no-sdio; 1730*4882a593Smuzhiyun no-sd; 1731*4882a593Smuzhiyun non-removable; 1732*4882a593Smuzhiyun max-frequency = <200000000>; 1733*4882a593Smuzhiyun full-pwr-cycle-in-suspend; 1734*4882a593Smuzhiyun status = "okay"; 1735*4882a593Smuzhiyun}; 1736*4882a593Smuzhiyun 1737*4882a593Smuzhiyun&sdmmc0 { 1738*4882a593Smuzhiyun max-frequency = <150000000>; 1739*4882a593Smuzhiyun no-sdio; 1740*4882a593Smuzhiyun no-mmc; 1741*4882a593Smuzhiyun bus-width = <4>; 1742*4882a593Smuzhiyun cap-mmc-highspeed; 1743*4882a593Smuzhiyun cap-sd-highspeed; 1744*4882a593Smuzhiyun disable-wp; 1745*4882a593Smuzhiyun sd-uhs-sdr104; 1746*4882a593Smuzhiyun vmmc-supply = <&vcc3v3_sd>; 1747*4882a593Smuzhiyun vqmmc-supply = <&vccio_sd>; 1748*4882a593Smuzhiyun pinctrl-names = "default"; 1749*4882a593Smuzhiyun pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; 1750*4882a593Smuzhiyun status = "okay"; 1751*4882a593Smuzhiyun}; 1752*4882a593Smuzhiyun 1753*4882a593Smuzhiyun&sfc { 1754*4882a593Smuzhiyun status = "okay"; 1755*4882a593Smuzhiyun 1756*4882a593Smuzhiyun flash@0 { 1757*4882a593Smuzhiyun compatible = "spi-nand"; 1758*4882a593Smuzhiyun reg = <0>; 1759*4882a593Smuzhiyun spi-max-frequency = <75000000>; 1760*4882a593Smuzhiyun spi-rx-bus-width = <4>; 1761*4882a593Smuzhiyun spi-tx-bus-width = <1>; 1762*4882a593Smuzhiyun }; 1763*4882a593Smuzhiyun}; 1764*4882a593Smuzhiyun 1765*4882a593Smuzhiyun&spdif_8ch { 1766*4882a593Smuzhiyun status = "okay"; 1767*4882a593Smuzhiyun}; 1768*4882a593Smuzhiyun 1769*4882a593Smuzhiyun&tsadc { 1770*4882a593Smuzhiyun status = "okay"; 1771*4882a593Smuzhiyun}; 1772*4882a593Smuzhiyun 1773*4882a593Smuzhiyun&u2phy0_host { 1774*4882a593Smuzhiyun phy-supply = <&vcc5v0_host>; 1775*4882a593Smuzhiyun status = "okay"; 1776*4882a593Smuzhiyun}; 1777*4882a593Smuzhiyun 1778*4882a593Smuzhiyun&u2phy0_otg { 1779*4882a593Smuzhiyun vbus-supply = <&vcc5v0_otg>; 1780*4882a593Smuzhiyun status = "okay"; 1781*4882a593Smuzhiyun}; 1782*4882a593Smuzhiyun 1783*4882a593Smuzhiyun&u2phy1_host { 1784*4882a593Smuzhiyun phy-supply = <&vcc5v0_host>; 1785*4882a593Smuzhiyun status = "okay"; 1786*4882a593Smuzhiyun}; 1787*4882a593Smuzhiyun 1788*4882a593Smuzhiyun&u2phy1_otg { 1789*4882a593Smuzhiyun phy-supply = <&vcc5v0_host>; 1790*4882a593Smuzhiyun status = "okay"; 1791*4882a593Smuzhiyun}; 1792*4882a593Smuzhiyun 1793*4882a593Smuzhiyun&usb2phy0 { 1794*4882a593Smuzhiyun status = "okay"; 1795*4882a593Smuzhiyun}; 1796*4882a593Smuzhiyun 1797*4882a593Smuzhiyun&usb2phy1 { 1798*4882a593Smuzhiyun status = "okay"; 1799*4882a593Smuzhiyun}; 1800*4882a593Smuzhiyun 1801*4882a593Smuzhiyun&usb_host0_ehci { 1802*4882a593Smuzhiyun status = "okay"; 1803*4882a593Smuzhiyun}; 1804*4882a593Smuzhiyun 1805*4882a593Smuzhiyun&usb_host0_ohci { 1806*4882a593Smuzhiyun status = "okay"; 1807*4882a593Smuzhiyun}; 1808*4882a593Smuzhiyun 1809*4882a593Smuzhiyun&usb_host1_ehci { 1810*4882a593Smuzhiyun status = "okay"; 1811*4882a593Smuzhiyun}; 1812*4882a593Smuzhiyun 1813*4882a593Smuzhiyun&usb_host1_ohci { 1814*4882a593Smuzhiyun status = "okay"; 1815*4882a593Smuzhiyun}; 1816*4882a593Smuzhiyun 1817*4882a593Smuzhiyun&usbdrd_dwc3 { 1818*4882a593Smuzhiyun dr_mode = "otg"; 1819*4882a593Smuzhiyun extcon = <&usb2phy0>; 1820*4882a593Smuzhiyun status = "okay"; 1821*4882a593Smuzhiyun}; 1822*4882a593Smuzhiyun 1823*4882a593Smuzhiyun&usbdrd30 { 1824*4882a593Smuzhiyun status = "okay"; 1825*4882a593Smuzhiyun}; 1826*4882a593Smuzhiyun 1827*4882a593Smuzhiyun&usbhost_dwc3 { 1828*4882a593Smuzhiyun status = "okay"; 1829*4882a593Smuzhiyun}; 1830*4882a593Smuzhiyun 1831*4882a593Smuzhiyun&usbhost30 { 1832*4882a593Smuzhiyun status = "okay"; 1833*4882a593Smuzhiyun}; 1834*4882a593Smuzhiyun 1835*4882a593Smuzhiyun&vad { 1836*4882a593Smuzhiyun rockchip,audio-src = <&i2s1_8ch>; 1837*4882a593Smuzhiyun rockchip,buffer-time-ms = <128>; 1838*4882a593Smuzhiyun rockchip,det-channel = <0>; 1839*4882a593Smuzhiyun rockchip,mode = <0>; 1840*4882a593Smuzhiyun}; 1841*4882a593Smuzhiyun 1842*4882a593Smuzhiyun&vdpu { 1843*4882a593Smuzhiyun status = "okay"; 1844*4882a593Smuzhiyun}; 1845*4882a593Smuzhiyun 1846*4882a593Smuzhiyun&vdpu_mmu { 1847*4882a593Smuzhiyun status = "okay"; 1848*4882a593Smuzhiyun}; 1849*4882a593Smuzhiyun 1850*4882a593Smuzhiyun&vepu { 1851*4882a593Smuzhiyun status = "okay"; 1852*4882a593Smuzhiyun}; 1853*4882a593Smuzhiyun 1854*4882a593Smuzhiyun&vepu_mmu { 1855*4882a593Smuzhiyun status = "okay"; 1856*4882a593Smuzhiyun}; 1857*4882a593Smuzhiyun 1858*4882a593Smuzhiyun&vop { 1859*4882a593Smuzhiyun status = "okay"; 1860*4882a593Smuzhiyun assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; 1861*4882a593Smuzhiyun assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; 1862*4882a593Smuzhiyun}; 1863*4882a593Smuzhiyun 1864*4882a593Smuzhiyun&vop_mmu { 1865*4882a593Smuzhiyun status = "okay"; 1866*4882a593Smuzhiyun}; 1867