xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm64/rockchip/rk3566-rk817-tablet-v10.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun/dts-v1/;
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
10*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h>
11*4882a593Smuzhiyun#include <dt-bindings/input/rk-input.h>
12*4882a593Smuzhiyun#include <dt-bindings/sensor-dev.h>
13*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h>
14*4882a593Smuzhiyun#include "rk3566.dtsi"
15*4882a593Smuzhiyun#include "rk3568-android.dtsi"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun/ {
18*4882a593Smuzhiyun	model = "Rockchip RK3566 RK817 TABLET LP4X Board";
19*4882a593Smuzhiyun	compatible = "rockchip,rk3566-rk817-tablet", "rockchip,rk3566";
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun	adc_keys: adc-keys {
22*4882a593Smuzhiyun		compatible = "adc-keys";
23*4882a593Smuzhiyun		io-channels = <&saradc 0>;
24*4882a593Smuzhiyun		io-channel-names = "buttons";
25*4882a593Smuzhiyun		keyup-threshold-microvolt = <1800000>;
26*4882a593Smuzhiyun		poll-interval = <100>;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun		vol-up-key {
29*4882a593Smuzhiyun			label = "volume up";
30*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
31*4882a593Smuzhiyun			press-threshold-microvolt = <1750>;
32*4882a593Smuzhiyun		};
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun		vol-down-key {
35*4882a593Smuzhiyun			label = "volume down";
36*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEDOWN>;
37*4882a593Smuzhiyun			press-threshold-microvolt = <297500>;
38*4882a593Smuzhiyun		};
39*4882a593Smuzhiyun	};
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun	backlight: backlight {
42*4882a593Smuzhiyun		compatible = "pwm-backlight";
43*4882a593Smuzhiyun		pwms = <&pwm4 0 25000 0>;
44*4882a593Smuzhiyun		brightness-levels = <
45*4882a593Smuzhiyun			  0  20  20  21  21  22  22  23
46*4882a593Smuzhiyun			 23  24  24  25  25  26  26  27
47*4882a593Smuzhiyun			 27  28  28  29  29  30  30  31
48*4882a593Smuzhiyun			 31  32  32  33  33  34  34  35
49*4882a593Smuzhiyun			 35  36  36  37  37  38  38  39
50*4882a593Smuzhiyun			 40  41  42  43  44  45  46  47
51*4882a593Smuzhiyun			 48  49  50  50  51  52  53  54
52*4882a593Smuzhiyun			 55  55  56  57  58  59  60  61
53*4882a593Smuzhiyun			 62  63  64  64  65  65  66  67
54*4882a593Smuzhiyun			 68  69  70  71  71  72  73  74
55*4882a593Smuzhiyun			 75  76  77  78  79  79  80  81
56*4882a593Smuzhiyun			 82  83  84  85  86  86  87  88
57*4882a593Smuzhiyun			 89  90  91  92  93  94  94  95
58*4882a593Smuzhiyun			 96  97  98  99 100 101 101 102
59*4882a593Smuzhiyun			103 104 105 106 107 107 108 109
60*4882a593Smuzhiyun			110 111 112 113 114 115 115 116
61*4882a593Smuzhiyun			117 118 119 120 121 122 123 123
62*4882a593Smuzhiyun			124 125 126 127 128 129 130 130
63*4882a593Smuzhiyun			131 132 133 134 135 136 136 137
64*4882a593Smuzhiyun			138 139 140 141 142 143 143 144
65*4882a593Smuzhiyun			145 146 147 147 148 149 150 151
66*4882a593Smuzhiyun			152 153 154 155 156 156 157 158
67*4882a593Smuzhiyun			159 157 158 159 160 161 162 162
68*4882a593Smuzhiyun			163 164 165 166 167 168 169 169
69*4882a593Smuzhiyun			170 171 172 173 174 175 175 176
70*4882a593Smuzhiyun			177 178 179 180 181 182 182 183
71*4882a593Smuzhiyun			184 185 186 187 188 189 190 190
72*4882a593Smuzhiyun			191 192 193 194 195 196 197 197
73*4882a593Smuzhiyun			198 199 200 201 202 203 204 204
74*4882a593Smuzhiyun			205 206 207 208 209 209 210 211
75*4882a593Smuzhiyun			212 213 213 214 214 215 215 216
76*4882a593Smuzhiyun			216 217 217 218 218 219 219 220
77*4882a593Smuzhiyun		>;
78*4882a593Smuzhiyun		default-brightness-level = <200>;
79*4882a593Smuzhiyun	};
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun	charge-animation {
82*4882a593Smuzhiyun		compatible = "rockchip,uboot-charge";
83*4882a593Smuzhiyun		rockchip,uboot-charge-on = <1>;
84*4882a593Smuzhiyun		rockchip,android-charge-on = <0>;
85*4882a593Smuzhiyun		rockchip,uboot-low-power-voltage = <3350>;
86*4882a593Smuzhiyun		rockchip,screen-on-voltage = <3400>;
87*4882a593Smuzhiyun		status = "okay";
88*4882a593Smuzhiyun	};
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun	flash_rgb13h: flash-rgb13h {
91*4882a593Smuzhiyun		status = "okay";
92*4882a593Smuzhiyun		compatible = "led,rgb13h";
93*4882a593Smuzhiyun		label = "gpio-flash";
94*4882a593Smuzhiyun		pinctrl-names = "default";
95*4882a593Smuzhiyun		pinctrl-0 = <&flash_led_gpios>;
96*4882a593Smuzhiyun		led-max-microamp = <20000>;
97*4882a593Smuzhiyun		flash-max-microamp = <20000>;
98*4882a593Smuzhiyun		flash-max-timeout-us = <1000000>;
99*4882a593Smuzhiyun		enable-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>;
100*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
101*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
102*4882a593Smuzhiyun	};
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun	hdmi_sound: hdmi-sound {
105*4882a593Smuzhiyun		compatible = "simple-audio-card";
106*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
107*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <128>;
108*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,hdmi";
109*4882a593Smuzhiyun		status = "okay";
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun		simple-audio-card,cpu {
112*4882a593Smuzhiyun				sound-dai = <&i2s0_8ch>;
113*4882a593Smuzhiyun		};
114*4882a593Smuzhiyun		simple-audio-card,codec {
115*4882a593Smuzhiyun				sound-dai = <&hdmi>;
116*4882a593Smuzhiyun		};
117*4882a593Smuzhiyun	};
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun	vccsys: vccsys {
120*4882a593Smuzhiyun		compatible = "regulator-fixed";
121*4882a593Smuzhiyun		regulator-name = "vcc3v8_sys";
122*4882a593Smuzhiyun		regulator-always-on;
123*4882a593Smuzhiyun		regulator-boot-on;
124*4882a593Smuzhiyun		regulator-min-microvolt = <3800000>;
125*4882a593Smuzhiyun		regulator-max-microvolt = <3800000>;
126*4882a593Smuzhiyun	};
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun	vcc_camera: vcc-camera-regulator {
129*4882a593Smuzhiyun		compatible = "regulator-fixed";
130*4882a593Smuzhiyun		gpio = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>;
131*4882a593Smuzhiyun		pinctrl-names = "default";
132*4882a593Smuzhiyun		pinctrl-0 = <&camera_rst>;
133*4882a593Smuzhiyun		regulator-name = "vcc_camera";
134*4882a593Smuzhiyun		enable-active-high;
135*4882a593Smuzhiyun		regulator-always-on;
136*4882a593Smuzhiyun		regulator-boot-on;
137*4882a593Smuzhiyun	};
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun	rk817-sound {
140*4882a593Smuzhiyun		compatible = "rockchip,multicodecs-card";
141*4882a593Smuzhiyun		rockchip,card-name = "rockchip-rk817";
142*4882a593Smuzhiyun		hp-det-gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>;
143*4882a593Smuzhiyun		io-channels = <&saradc 2>;
144*4882a593Smuzhiyun		io-channel-names = "adc-detect";
145*4882a593Smuzhiyun		keyup-threshold-microvolt = <1800000>;
146*4882a593Smuzhiyun		poll-interval = <100>;
147*4882a593Smuzhiyun		rockchip,format = "i2s";
148*4882a593Smuzhiyun		rockchip,mclk-fs = <256>;
149*4882a593Smuzhiyun		rockchip,cpu = <&i2s1_8ch>;
150*4882a593Smuzhiyun		rockchip,codec = <&rk817_codec>;
151*4882a593Smuzhiyun		pinctrl-names = "default";
152*4882a593Smuzhiyun		pinctrl-0 = <&hp_det>;
153*4882a593Smuzhiyun		play-pause-key {
154*4882a593Smuzhiyun			label = "playpause";
155*4882a593Smuzhiyun			linux,code = <KEY_PLAYPAUSE>;
156*4882a593Smuzhiyun			press-threshold-microvolt = <2000>;
157*4882a593Smuzhiyun		};
158*4882a593Smuzhiyun	};
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun	sdio_pwrseq: sdio-pwrseq {
161*4882a593Smuzhiyun		compatible = "mmc-pwrseq-simple";
162*4882a593Smuzhiyun		clocks = <&rk817 1>;
163*4882a593Smuzhiyun		clock-names = "ext_clock";
164*4882a593Smuzhiyun		pinctrl-names = "default";
165*4882a593Smuzhiyun		pinctrl-0 = <&wifi_enable_h>;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun		/*
168*4882a593Smuzhiyun		 * On the module itself this is one of these (depending
169*4882a593Smuzhiyun		 * on the actual card populated):
170*4882a593Smuzhiyun		 * - SDIO_RESET_L_WL_REG_ON
171*4882a593Smuzhiyun		 * - PDN (power down when low)
172*4882a593Smuzhiyun		 */
173*4882a593Smuzhiyun		post-power-on-delay-ms = <200>;
174*4882a593Smuzhiyun		reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
175*4882a593Smuzhiyun	};
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun	vcc_sd: vcc-sd {
178*4882a593Smuzhiyun		compatible = "regulator-gpio";
179*4882a593Smuzhiyun		enable-active-low;
180*4882a593Smuzhiyun		enable-gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
181*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
182*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
183*4882a593Smuzhiyun		pinctrl-names = "default";
184*4882a593Smuzhiyun		pinctrl-0 = <&vcc_sd_h>;
185*4882a593Smuzhiyun		regulator-name = "vcc_sd";
186*4882a593Smuzhiyun		states = <3300000 0x0
187*4882a593Smuzhiyun			3300000 0x1>;
188*4882a593Smuzhiyun	};
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun	wireless-wlan {
191*4882a593Smuzhiyun		compatible = "wlan-platdata";
192*4882a593Smuzhiyun		rockchip,grf = <&grf>;
193*4882a593Smuzhiyun		wifi_chip_type = "ap6255";
194*4882a593Smuzhiyun		pinctrl-names = "default";
195*4882a593Smuzhiyun		pinctrl-0 = <&wifi_host_wake_irq>;
196*4882a593Smuzhiyun		WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>;
197*4882a593Smuzhiyun		WIFI,poweren_gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
198*4882a593Smuzhiyun		status = "okay";
199*4882a593Smuzhiyun	};
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun	wireless-bluetooth {
202*4882a593Smuzhiyun		compatible = "bluetooth-platdata";
203*4882a593Smuzhiyun		clocks = <&rk817 1>;
204*4882a593Smuzhiyun		clock-names = "ext_clock";
205*4882a593Smuzhiyun		//wifi-bt-power-toggle;
206*4882a593Smuzhiyun		uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
207*4882a593Smuzhiyun		pinctrl-names = "default", "rts_gpio";
208*4882a593Smuzhiyun		pinctrl-0 = <&uart1m0_rtsn>;
209*4882a593Smuzhiyun		pinctrl-1 = <&uart1_gpios>;
210*4882a593Smuzhiyun		BT,reset_gpio    = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
211*4882a593Smuzhiyun		BT,wake_gpio     = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
212*4882a593Smuzhiyun		BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
213*4882a593Smuzhiyun		status = "okay";
214*4882a593Smuzhiyun	};
215*4882a593Smuzhiyun};
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun&cpu0 {
218*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu>;
219*4882a593Smuzhiyun};
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun&csi2_dphy_hw {
222*4882a593Smuzhiyun	status = "okay";
223*4882a593Smuzhiyun};
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun&csi2_dphy0 {
226*4882a593Smuzhiyun	status = "okay";
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun	ports {
229*4882a593Smuzhiyun		#address-cells = <1>;
230*4882a593Smuzhiyun		#size-cells = <0>;
231*4882a593Smuzhiyun		port@0 {
232*4882a593Smuzhiyun			reg = <0>;
233*4882a593Smuzhiyun			#address-cells = <1>;
234*4882a593Smuzhiyun			#size-cells = <0>;
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun			mipi_in_ucam0: endpoint@0 {
237*4882a593Smuzhiyun				reg = <0>;
238*4882a593Smuzhiyun				remote-endpoint = <&gc2385_out>;
239*4882a593Smuzhiyun				data-lanes = <1>;
240*4882a593Smuzhiyun			};
241*4882a593Smuzhiyun			mipi_in_ucam1: endpoint@1 {
242*4882a593Smuzhiyun				reg = <1>;
243*4882a593Smuzhiyun				remote-endpoint = <&ov8858_out>;
244*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
245*4882a593Smuzhiyun			};
246*4882a593Smuzhiyun		};
247*4882a593Smuzhiyun		port@1 {
248*4882a593Smuzhiyun			reg = <1>;
249*4882a593Smuzhiyun			#address-cells = <1>;
250*4882a593Smuzhiyun			#size-cells = <0>;
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun			csidphy0_out: endpoint@0 {
253*4882a593Smuzhiyun				reg = <0>;
254*4882a593Smuzhiyun				remote-endpoint = <&isp0_in>;
255*4882a593Smuzhiyun			};
256*4882a593Smuzhiyun		};
257*4882a593Smuzhiyun	};
258*4882a593Smuzhiyun};
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun&dfi {
261*4882a593Smuzhiyun	status = "okay";
262*4882a593Smuzhiyun};
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun&dmc {
265*4882a593Smuzhiyun	center-supply = <&vdd_logic>;
266*4882a593Smuzhiyun	status = "okay";
267*4882a593Smuzhiyun};
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun&dsi0 {
270*4882a593Smuzhiyun	status = "okay";
271*4882a593Smuzhiyun	rockchip,lane-rate = <1000>;
272*4882a593Smuzhiyun	panel@0 {
273*4882a593Smuzhiyun		compatible = "aoly,sl008pa21y1285-b00", "simple-panel-dsi";
274*4882a593Smuzhiyun		reg = <0>;
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun		backlight = <&backlight>;
277*4882a593Smuzhiyun		//power-supply=<&vcc_3v3>;
278*4882a593Smuzhiyun		enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
279*4882a593Smuzhiyun		stbyb-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
280*4882a593Smuzhiyun		reset-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun		pinctrl-names = "default";
283*4882a593Smuzhiyun		pinctrl-0 = <&lcd_enable_gpio>, <&lcd_rst_gpio>, <&lcd_stanby_gpio>;
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun		prepare-delay-ms = <120>;
286*4882a593Smuzhiyun		reset-delay-ms = <120>;
287*4882a593Smuzhiyun		init-delay-ms = <120>;
288*4882a593Smuzhiyun		stbyb-delay-ms = <120>;
289*4882a593Smuzhiyun		enable-delay-ms = <120>;
290*4882a593Smuzhiyun		disable-delay-ms = <120>;
291*4882a593Smuzhiyun		unprepare-delay-ms = <120>;
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun		width-mm = <229>;
294*4882a593Smuzhiyun		height-mm = <143>;
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun		dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
297*4882a593Smuzhiyun			      MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
298*4882a593Smuzhiyun		dsi,format = <MIPI_DSI_FMT_RGB888>;
299*4882a593Smuzhiyun		dsi,lanes = <4>;
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun		panel-init-sequence = [
302*4882a593Smuzhiyun			23 00 02 B0 01
303*4882a593Smuzhiyun			23 00 02 C3 0F
304*4882a593Smuzhiyun			23 00 02 C4 00
305*4882a593Smuzhiyun			23 00 02 C5 00
306*4882a593Smuzhiyun			23 00 02 C6 00
307*4882a593Smuzhiyun			23 00 02 C7 00
308*4882a593Smuzhiyun			23 00 02 C8 0D
309*4882a593Smuzhiyun			23 00 02 C9 12
310*4882a593Smuzhiyun			23 00 02 CA 11
311*4882a593Smuzhiyun			23 00 02 CD 1D
312*4882a593Smuzhiyun			23 00 02 CE 1B
313*4882a593Smuzhiyun			23 00 02 CF 0B
314*4882a593Smuzhiyun			23 00 02 D0 09
315*4882a593Smuzhiyun			23 00 02 D1 07
316*4882a593Smuzhiyun			23 00 02 D2 05
317*4882a593Smuzhiyun			23 00 02 D3 01
318*4882a593Smuzhiyun			23 00 02 D7 10
319*4882a593Smuzhiyun			23 00 02 D8 00
320*4882a593Smuzhiyun			23 00 02 D9 00
321*4882a593Smuzhiyun			23 00 02 DA 00
322*4882a593Smuzhiyun			23 00 02 DB 00
323*4882a593Smuzhiyun			23 00 02 DC 0E
324*4882a593Smuzhiyun			23 00 02 DD 12
325*4882a593Smuzhiyun			23 00 02 DE 11
326*4882a593Smuzhiyun			23 00 02 E1 1E
327*4882a593Smuzhiyun			23 00 02 E2 1C
328*4882a593Smuzhiyun			23 00 02 E3 0C
329*4882a593Smuzhiyun			23 00 02 E4 0A
330*4882a593Smuzhiyun			23 00 02 E5 08
331*4882a593Smuzhiyun			23 00 02 E6 06
332*4882a593Smuzhiyun			23 00 02 E7 02
333*4882a593Smuzhiyun			23 00 02 B0 03
334*4882a593Smuzhiyun			23 00 02 BE 03
335*4882a593Smuzhiyun			23 00 02 CC 44
336*4882a593Smuzhiyun			23 00 02 C8 07
337*4882a593Smuzhiyun			23 00 02 C9 05
338*4882a593Smuzhiyun			23 00 02 CA 42
339*4882a593Smuzhiyun			23 00 02 CD 3E
340*4882a593Smuzhiyun			23 00 02 CF 60
341*4882a593Smuzhiyun			23 00 02 D2 04
342*4882a593Smuzhiyun			23 00 02 D3 04
343*4882a593Smuzhiyun			23 00 02 D4 01
344*4882a593Smuzhiyun			23 00 02 D5 00
345*4882a593Smuzhiyun			23 00 02 D6 03
346*4882a593Smuzhiyun			23 00 02 D7 04
347*4882a593Smuzhiyun			23 00 02 D9 01
348*4882a593Smuzhiyun			23 00 02 DB 01
349*4882a593Smuzhiyun			23 00 02 E4 F0
350*4882a593Smuzhiyun			23 00 02 E5 0A
351*4882a593Smuzhiyun			23 00 02 B0 00
352*4882a593Smuzhiyun			23 00 02 BA 8F// NEW ADD
353*4882a593Smuzhiyun			23 00 02 BD 63
354*4882a593Smuzhiyun			23 00 02 C2 08
355*4882a593Smuzhiyun			23 00 02 C4 10
356*4882a593Smuzhiyun			23 00 02 B0 02
357*4882a593Smuzhiyun			23 00 02 C0 00
358*4882a593Smuzhiyun			23 00 02 C1 0A
359*4882a593Smuzhiyun			23 00 02 C2 20
360*4882a593Smuzhiyun			23 00 02 C3 24
361*4882a593Smuzhiyun			23 00 02 C4 23
362*4882a593Smuzhiyun			23 00 02 C5 29
363*4882a593Smuzhiyun			23 00 02 C6 23
364*4882a593Smuzhiyun			23 00 02 C7 1C
365*4882a593Smuzhiyun			23 00 02 C8 19
366*4882a593Smuzhiyun			23 00 02 C9 17
367*4882a593Smuzhiyun			23 00 02 CA 17
368*4882a593Smuzhiyun			23 00 02 CB 18
369*4882a593Smuzhiyun			23 00 02 CC 1A
370*4882a593Smuzhiyun			23 00 02 CD 1E
371*4882a593Smuzhiyun			23 00 02 CE 20
372*4882a593Smuzhiyun			23 00 02 CF 23
373*4882a593Smuzhiyun			23 00 02 D0 07
374*4882a593Smuzhiyun			23 00 02 D1 00
375*4882a593Smuzhiyun			23 00 02 D2 00
376*4882a593Smuzhiyun			23 00 02 D3 0A
377*4882a593Smuzhiyun			23 00 02 D4 13
378*4882a593Smuzhiyun			23 00 02 D5 1C
379*4882a593Smuzhiyun			23 00 02 D6 1A
380*4882a593Smuzhiyun			23 00 02 D7 13
381*4882a593Smuzhiyun			23 00 02 D8 17
382*4882a593Smuzhiyun			23 00 02 D9 1C
383*4882a593Smuzhiyun			23 00 02 DA 19
384*4882a593Smuzhiyun			23 00 02 DB 17
385*4882a593Smuzhiyun			23 00 02 DC 17
386*4882a593Smuzhiyun			23 00 02 DD 18
387*4882a593Smuzhiyun			23 00 02 DE 1A
388*4882a593Smuzhiyun			23 00 02 DF 1E
389*4882a593Smuzhiyun			23 00 02 E0 20
390*4882a593Smuzhiyun			23 00 02 E1 23
391*4882a593Smuzhiyun			23 00 02 E2 07
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun			05 78 01 11
394*4882a593Smuzhiyun			05 32 01 29
395*4882a593Smuzhiyun		];
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun		panel-exit-sequence = [
398*4882a593Smuzhiyun			05 dc 01 28
399*4882a593Smuzhiyun			05 78 01 10
400*4882a593Smuzhiyun		];
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun		display-timings {
403*4882a593Smuzhiyun			native-mode = <&timing0>;
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun			timing0: timing0 {
406*4882a593Smuzhiyun				clock-frequency = <160000000>;
407*4882a593Smuzhiyun				hactive = <1200>;
408*4882a593Smuzhiyun				vactive = <1920>;
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun				hsync-len = <1>;//19
411*4882a593Smuzhiyun				hback-porch = <60>;//40
412*4882a593Smuzhiyun				hfront-porch = <80>;//123
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun				vsync-len = <1>;
415*4882a593Smuzhiyun				vback-porch = <25>;
416*4882a593Smuzhiyun				vfront-porch = <35>;
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun				hsync-active = <0>;
419*4882a593Smuzhiyun				vsync-active = <0>;
420*4882a593Smuzhiyun				de-active = <0>;
421*4882a593Smuzhiyun				pixelclk-active = <1>;
422*4882a593Smuzhiyun			};
423*4882a593Smuzhiyun		};
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun		ports {
426*4882a593Smuzhiyun			#address-cells = <1>;
427*4882a593Smuzhiyun			#size-cells = <0>;
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun			port@0 {
430*4882a593Smuzhiyun				reg = <0>;
431*4882a593Smuzhiyun				panel_in_dsi: endpoint {
432*4882a593Smuzhiyun					remote-endpoint = <&dsi_out_panel>;
433*4882a593Smuzhiyun				};
434*4882a593Smuzhiyun			};
435*4882a593Smuzhiyun		};
436*4882a593Smuzhiyun	};
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun	ports {
439*4882a593Smuzhiyun		#address-cells = <1>;
440*4882a593Smuzhiyun		#size-cells = <0>;
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun		port@1 {
443*4882a593Smuzhiyun			reg = <1>;
444*4882a593Smuzhiyun			dsi_out_panel: endpoint {
445*4882a593Smuzhiyun				remote-endpoint = <&panel_in_dsi>;
446*4882a593Smuzhiyun			};
447*4882a593Smuzhiyun		};
448*4882a593Smuzhiyun	};
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun};
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun&dsi0_in_vp0 {
453*4882a593Smuzhiyun	status = "okay";
454*4882a593Smuzhiyun};
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun&dsi0_in_vp1 {
457*4882a593Smuzhiyun	status = "disabled";
458*4882a593Smuzhiyun};
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun&gpu {
461*4882a593Smuzhiyun	mali-supply = <&vdd_gpu>;
462*4882a593Smuzhiyun	status = "okay";
463*4882a593Smuzhiyun};
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun&hdmi {
466*4882a593Smuzhiyun	status = "okay";
467*4882a593Smuzhiyun};
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun&hdmi_in_vp0 {
470*4882a593Smuzhiyun	status = "okay";
471*4882a593Smuzhiyun};
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun&hdmi_in_vp1 {
474*4882a593Smuzhiyun	status = "disabled";
475*4882a593Smuzhiyun};
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun&hdmi_sound {
478*4882a593Smuzhiyun	status = "okay";
479*4882a593Smuzhiyun};
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun&i2c0 {
482*4882a593Smuzhiyun	status = "okay";
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun	vdd_cpu: tcs4525@1c {
485*4882a593Smuzhiyun		compatible = "tcs,tcs4525";
486*4882a593Smuzhiyun		reg = <0x1c>;
487*4882a593Smuzhiyun		vin-supply = <&vccsys>;
488*4882a593Smuzhiyun		regulator-compatible = "fan53555-reg";
489*4882a593Smuzhiyun		regulator-name = "vdd_cpu";
490*4882a593Smuzhiyun		regulator-min-microvolt = <712500>;
491*4882a593Smuzhiyun		regulator-max-microvolt = <1390000>;
492*4882a593Smuzhiyun		regulator-init-microvolt = <900000>;
493*4882a593Smuzhiyun		regulator-ramp-delay = <2300>;
494*4882a593Smuzhiyun		fcs,suspend-voltage-selector = <1>;
495*4882a593Smuzhiyun		regulator-boot-on;
496*4882a593Smuzhiyun		regulator-always-on;
497*4882a593Smuzhiyun		regulator-state-mem {
498*4882a593Smuzhiyun			regulator-off-in-suspend;
499*4882a593Smuzhiyun		};
500*4882a593Smuzhiyun	};
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun	rk817: pmic@20 {
503*4882a593Smuzhiyun		compatible = "rockchip,rk817";
504*4882a593Smuzhiyun		reg = <0x20>;
505*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
506*4882a593Smuzhiyun		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
507*4882a593Smuzhiyun
508*4882a593Smuzhiyun		pinctrl-names = "default", "pmic-sleep",
509*4882a593Smuzhiyun				"pmic-power-off", "pmic-reset";
510*4882a593Smuzhiyun		pinctrl-0 = <&pmic_int>;
511*4882a593Smuzhiyun		pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
512*4882a593Smuzhiyun		pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
513*4882a593Smuzhiyun		pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>;
514*4882a593Smuzhiyun		rockchip,system-power-controller;
515*4882a593Smuzhiyun		wakeup-source;
516*4882a593Smuzhiyun		#clock-cells = <1>;
517*4882a593Smuzhiyun		clock-output-names = "rk808-clkout1", "rk808-clkout2";
518*4882a593Smuzhiyun		//fb-inner-reg-idxs = <2>;
519*4882a593Smuzhiyun		/* 1: rst regs (default in codes), 0: rst the pmic */
520*4882a593Smuzhiyun		pmic-reset-func = <0>;
521*4882a593Smuzhiyun		/* not save the PMIC_POWER_EN register in uboot */
522*4882a593Smuzhiyun		not-save-power-en = <1>;
523*4882a593Smuzhiyun
524*4882a593Smuzhiyun		vcc1-supply = <&vccsys>;
525*4882a593Smuzhiyun		vcc2-supply = <&vccsys>;
526*4882a593Smuzhiyun		vcc3-supply = <&vccsys>;
527*4882a593Smuzhiyun		vcc4-supply = <&vccsys>;
528*4882a593Smuzhiyun		vcc5-supply = <&vccsys>;
529*4882a593Smuzhiyun		vcc6-supply = <&vccsys>;
530*4882a593Smuzhiyun		vcc7-supply = <&vccsys>;
531*4882a593Smuzhiyun		vcc8-supply = <&vccsys>;
532*4882a593Smuzhiyun		vcc9-supply = <&dcdc_boost>;
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun		pwrkey {
535*4882a593Smuzhiyun			status = "okay";
536*4882a593Smuzhiyun		};
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun		pinctrl_rk8xx: pinctrl_rk8xx {
539*4882a593Smuzhiyun			gpio-controller;
540*4882a593Smuzhiyun			#gpio-cells = <2>;
541*4882a593Smuzhiyun
542*4882a593Smuzhiyun			rk817_slppin_null: rk817_slppin_null {
543*4882a593Smuzhiyun				pins = "gpio_slp";
544*4882a593Smuzhiyun				function = "pin_fun0";
545*4882a593Smuzhiyun			};
546*4882a593Smuzhiyun
547*4882a593Smuzhiyun			rk817_slppin_slp: rk817_slppin_slp {
548*4882a593Smuzhiyun				pins = "gpio_slp";
549*4882a593Smuzhiyun				function = "pin_fun1";
550*4882a593Smuzhiyun			};
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun			rk817_slppin_pwrdn: rk817_slppin_pwrdn {
553*4882a593Smuzhiyun				pins = "gpio_slp";
554*4882a593Smuzhiyun				function = "pin_fun2";
555*4882a593Smuzhiyun			};
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun			rk817_slppin_rst: rk817_slppin_rst {
558*4882a593Smuzhiyun				pins = "gpio_slp";
559*4882a593Smuzhiyun				function = "pin_fun3";
560*4882a593Smuzhiyun			};
561*4882a593Smuzhiyun		};
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun		regulators {
564*4882a593Smuzhiyun			vdd_logic: DCDC_REG1 {
565*4882a593Smuzhiyun				regulator-always-on;
566*4882a593Smuzhiyun				regulator-boot-on;
567*4882a593Smuzhiyun				regulator-min-microvolt = <500000>;
568*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
569*4882a593Smuzhiyun				regulator-init-microvolt = <900000>;
570*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
571*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
572*4882a593Smuzhiyun				regulator-name = "vdd_logic";
573*4882a593Smuzhiyun				regulator-state-mem {
574*4882a593Smuzhiyun					regulator-off-in-suspend;
575*4882a593Smuzhiyun					regulator-suspend-microvolt = <900000>;
576*4882a593Smuzhiyun				};
577*4882a593Smuzhiyun			};
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun			vdd_gpu: DCDC_REG2 {
580*4882a593Smuzhiyun				regulator-always-on;
581*4882a593Smuzhiyun				regulator-boot-on;
582*4882a593Smuzhiyun				regulator-min-microvolt = <500000>;
583*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
584*4882a593Smuzhiyun				regulator-init-microvolt = <900000>;
585*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
586*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
587*4882a593Smuzhiyun				regulator-name = "vdd_gpu";
588*4882a593Smuzhiyun				regulator-state-mem {
589*4882a593Smuzhiyun					regulator-off-in-suspend;
590*4882a593Smuzhiyun				};
591*4882a593Smuzhiyun			};
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun			vcc_ddr: DCDC_REG3 {
594*4882a593Smuzhiyun				regulator-always-on;
595*4882a593Smuzhiyun				regulator-boot-on;
596*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
597*4882a593Smuzhiyun				regulator-name = "vcc_ddr";
598*4882a593Smuzhiyun				regulator-state-mem {
599*4882a593Smuzhiyun					regulator-on-in-suspend;
600*4882a593Smuzhiyun				};
601*4882a593Smuzhiyun			};
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun			vcc_3v3: DCDC_REG4 {
604*4882a593Smuzhiyun				regulator-always-on;
605*4882a593Smuzhiyun				regulator-boot-on;
606*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
607*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
608*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
609*4882a593Smuzhiyun				regulator-name = "vcc_3v3";
610*4882a593Smuzhiyun				regulator-state-mem {
611*4882a593Smuzhiyun					regulator-off-in-suspend;
612*4882a593Smuzhiyun				};
613*4882a593Smuzhiyun			};
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun			vcca1v8_pmu: LDO_REG1 {
616*4882a593Smuzhiyun				regulator-always-on;
617*4882a593Smuzhiyun				regulator-boot-on;
618*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
619*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
620*4882a593Smuzhiyun				regulator-name = "vcca1v8_pmu";
621*4882a593Smuzhiyun				regulator-state-mem {
622*4882a593Smuzhiyun					regulator-on-in-suspend;
623*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
624*4882a593Smuzhiyun				};
625*4882a593Smuzhiyun			};
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun			vdda_0v9: LDO_REG2 {
628*4882a593Smuzhiyun				regulator-always-on;
629*4882a593Smuzhiyun				regulator-boot-on;
630*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
631*4882a593Smuzhiyun				regulator-max-microvolt = <900000>;
632*4882a593Smuzhiyun				regulator-name = "vdda_0v9";
633*4882a593Smuzhiyun				regulator-state-mem {
634*4882a593Smuzhiyun					regulator-off-in-suspend;
635*4882a593Smuzhiyun				};
636*4882a593Smuzhiyun			};
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun			vdda0v9_pmu: LDO_REG3 {
639*4882a593Smuzhiyun				regulator-always-on;
640*4882a593Smuzhiyun				regulator-boot-on;
641*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
642*4882a593Smuzhiyun				regulator-max-microvolt = <900000>;
643*4882a593Smuzhiyun				regulator-name = "vdda0v9_pmu";
644*4882a593Smuzhiyun				regulator-state-mem {
645*4882a593Smuzhiyun					regulator-on-in-suspend;
646*4882a593Smuzhiyun					regulator-suspend-microvolt = <900000>;
647*4882a593Smuzhiyun				};
648*4882a593Smuzhiyun			};
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun			vccio_acodec: LDO_REG4 {
651*4882a593Smuzhiyun				regulator-always-on;
652*4882a593Smuzhiyun				regulator-boot-on;
653*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
654*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
655*4882a593Smuzhiyun				regulator-name = "vccio_acodec";
656*4882a593Smuzhiyun				regulator-state-mem {
657*4882a593Smuzhiyun					regulator-off-in-suspend;
658*4882a593Smuzhiyun				};
659*4882a593Smuzhiyun			};
660*4882a593Smuzhiyun
661*4882a593Smuzhiyun			vccio_sd: LDO_REG5 {
662*4882a593Smuzhiyun				regulator-always-on;
663*4882a593Smuzhiyun				regulator-boot-on;
664*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
665*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
666*4882a593Smuzhiyun				regulator-name = "vccio_sd";
667*4882a593Smuzhiyun				regulator-state-mem {
668*4882a593Smuzhiyun					regulator-off-in-suspend;
669*4882a593Smuzhiyun				};
670*4882a593Smuzhiyun			};
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun			vcc3v3_pmu: LDO_REG6 {
673*4882a593Smuzhiyun				regulator-always-on;
674*4882a593Smuzhiyun				regulator-boot-on;
675*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
676*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
677*4882a593Smuzhiyun				regulator-name = "vcc3v3_pmu";
678*4882a593Smuzhiyun				regulator-state-mem {
679*4882a593Smuzhiyun					regulator-on-in-suspend;
680*4882a593Smuzhiyun					regulator-suspend-microvolt = <3000000>;
681*4882a593Smuzhiyun				};
682*4882a593Smuzhiyun			};
683*4882a593Smuzhiyun
684*4882a593Smuzhiyun			vcc_1v8: LDO_REG7 {
685*4882a593Smuzhiyun				regulator-always-on;
686*4882a593Smuzhiyun				regulator-boot-on;
687*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
688*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
689*4882a593Smuzhiyun				regulator-name = "vcc_1v8";
690*4882a593Smuzhiyun				regulator-state-mem {
691*4882a593Smuzhiyun					regulator-off-in-suspend;
692*4882a593Smuzhiyun				};
693*4882a593Smuzhiyun			};
694*4882a593Smuzhiyun
695*4882a593Smuzhiyun			vcc1v8_dvp: LDO_REG8 {
696*4882a593Smuzhiyun				regulator-always-on;
697*4882a593Smuzhiyun				regulator-boot-on;
698*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
699*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
700*4882a593Smuzhiyun				regulator-name = "vcc1v8_dvp";
701*4882a593Smuzhiyun				regulator-state-mem {
702*4882a593Smuzhiyun					regulator-off-in-suspend;
703*4882a593Smuzhiyun				};
704*4882a593Smuzhiyun			};
705*4882a593Smuzhiyun
706*4882a593Smuzhiyun			vcc2v8_dvp: LDO_REG9 {
707*4882a593Smuzhiyun				regulator-always-on;
708*4882a593Smuzhiyun				regulator-boot-on;
709*4882a593Smuzhiyun				regulator-min-microvolt = <2800000>;
710*4882a593Smuzhiyun				regulator-max-microvolt = <2800000>;
711*4882a593Smuzhiyun				regulator-name = "vcc2v8_dvp";
712*4882a593Smuzhiyun				regulator-state-mem {
713*4882a593Smuzhiyun					regulator-off-in-suspend;
714*4882a593Smuzhiyun				};
715*4882a593Smuzhiyun			};
716*4882a593Smuzhiyun
717*4882a593Smuzhiyun			dcdc_boost: BOOST {
718*4882a593Smuzhiyun				regulator-always-on;
719*4882a593Smuzhiyun				regulator-boot-on;
720*4882a593Smuzhiyun				regulator-min-microvolt = <4700000>;
721*4882a593Smuzhiyun				regulator-max-microvolt = <5400000>;
722*4882a593Smuzhiyun				regulator-name = "boost";
723*4882a593Smuzhiyun				regulator-state-mem {
724*4882a593Smuzhiyun					regulator-off-in-suspend;
725*4882a593Smuzhiyun				};
726*4882a593Smuzhiyun			};
727*4882a593Smuzhiyun
728*4882a593Smuzhiyun			otg_switch: OTG_SWITCH {
729*4882a593Smuzhiyun				regulator-name = "otg_switch";
730*4882a593Smuzhiyun				regulator-state-mem {
731*4882a593Smuzhiyun					regulator-off-in-suspend;
732*4882a593Smuzhiyun				};
733*4882a593Smuzhiyun			};
734*4882a593Smuzhiyun		};
735*4882a593Smuzhiyun
736*4882a593Smuzhiyun		battery {
737*4882a593Smuzhiyun			compatible = "rk817,battery";
738*4882a593Smuzhiyun			ocv_table = <3400 3513 3578 3687 3734 3752 3763
739*4882a593Smuzhiyun				     3766 3771 3784 3804 3836 3885 3925
740*4882a593Smuzhiyun				     3962 4005 4063 4114 4169 4227 4303>;
741*4882a593Smuzhiyun			design_capacity = <5000>;
742*4882a593Smuzhiyun			design_qmax = <5500>;
743*4882a593Smuzhiyun			bat_res = <100>;
744*4882a593Smuzhiyun			sleep_enter_current = <150>;
745*4882a593Smuzhiyun			sleep_exit_current = <180>;
746*4882a593Smuzhiyun			sleep_filter_current = <100>;
747*4882a593Smuzhiyun			power_off_thresd = <3350>;
748*4882a593Smuzhiyun			zero_algorithm_vol = <3850>;
749*4882a593Smuzhiyun			max_soc_offset = <60>;
750*4882a593Smuzhiyun			monitor_sec = <5>;
751*4882a593Smuzhiyun			sample_res = <10>;
752*4882a593Smuzhiyun			virtual_power = <0>;
753*4882a593Smuzhiyun		};
754*4882a593Smuzhiyun
755*4882a593Smuzhiyun		charger {
756*4882a593Smuzhiyun			compatible = "rk817,charger";
757*4882a593Smuzhiyun			min_input_voltage = <4500>;
758*4882a593Smuzhiyun			max_input_current = <1500>;
759*4882a593Smuzhiyun			max_chrg_current = <2000>;
760*4882a593Smuzhiyun			max_chrg_voltage = <4300>;
761*4882a593Smuzhiyun			chrg_term_mode = <0>;
762*4882a593Smuzhiyun			chrg_finish_cur = <300>;
763*4882a593Smuzhiyun			virtual_power = <0>;
764*4882a593Smuzhiyun			dc_det_adc = <0>;
765*4882a593Smuzhiyun			extcon = <&usb2phy0>;
766*4882a593Smuzhiyun			gate_function_disable = <1>;
767*4882a593Smuzhiyun		};
768*4882a593Smuzhiyun
769*4882a593Smuzhiyun		rk817_codec: codec {
770*4882a593Smuzhiyun			#sound-dai-cells = <0>;
771*4882a593Smuzhiyun			compatible = "rockchip,rk817-codec";
772*4882a593Smuzhiyun			clocks = <&cru I2S1_MCLKOUT>;
773*4882a593Smuzhiyun			clock-names = "mclk";
774*4882a593Smuzhiyun			assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>;
775*4882a593Smuzhiyun			assigned-clock-rates = <12288000>;
776*4882a593Smuzhiyun			assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>;
777*4882a593Smuzhiyun			pinctrl-names = "default";
778*4882a593Smuzhiyun			pinctrl-0 = <&i2s1m0_mclk>;
779*4882a593Smuzhiyun			hp-volume = <20>;
780*4882a593Smuzhiyun			spk-volume = <3>;
781*4882a593Smuzhiyun			out-l2spk-r2hp;
782*4882a593Smuzhiyun			spk-ctl-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
783*4882a593Smuzhiyun			status = "okay";
784*4882a593Smuzhiyun		};
785*4882a593Smuzhiyun	};
786*4882a593Smuzhiyun};
787*4882a593Smuzhiyun
788*4882a593Smuzhiyun&i2c2 {
789*4882a593Smuzhiyun	status = "okay";
790*4882a593Smuzhiyun	pinctrl-0 = <&i2c2m1_xfer>;
791*4882a593Smuzhiyun
792*4882a593Smuzhiyun	dw9714: dw9714@c {
793*4882a593Smuzhiyun		compatible = "dongwoon,dw9714";
794*4882a593Smuzhiyun		status = "okay";
795*4882a593Smuzhiyun		reg = <0x0c>;
796*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
797*4882a593Smuzhiyun		rockchip,vcm-start-current = <10>;
798*4882a593Smuzhiyun		rockchip,vcm-rated-current = <85>;
799*4882a593Smuzhiyun		rockchip,vcm-step-mode = <5>;
800*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
801*4882a593Smuzhiyun	};
802*4882a593Smuzhiyun
803*4882a593Smuzhiyun	gc2385: gc2385@37 {
804*4882a593Smuzhiyun		compatible = "galaxycore,gc2385";
805*4882a593Smuzhiyun		status = "okay";
806*4882a593Smuzhiyun		reg = <0x37>;
807*4882a593Smuzhiyun		clocks = <&cru CLK_CIF_OUT>;
808*4882a593Smuzhiyun		clock-names = "xvclk";
809*4882a593Smuzhiyun		power-domains = <&power RK3568_PD_VI>;
810*4882a593Smuzhiyun		pinctrl-names = "rockchip,camera_default";
811*4882a593Smuzhiyun		pinctrl-0 = <&cif_clk>;
812*4882a593Smuzhiyun
813*4882a593Smuzhiyun		//reset pin control by hardware,used this pin switch to mipi input
814*4882a593Smuzhiyun		//1->2LANE(LANE 0&1) FRONT camera, 0->4LANE REAR camera
815*4882a593Smuzhiyun		reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
816*4882a593Smuzhiyun		pwdn-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
817*4882a593Smuzhiyun		rockchip,camera-module-index = <1>;
818*4882a593Smuzhiyun		rockchip,camera-module-facing = "front";
819*4882a593Smuzhiyun		rockchip,camera-module-name = "HS5885-BNSM1018-V01";
820*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "default";
821*4882a593Smuzhiyun		port {
822*4882a593Smuzhiyun			gc2385_out: endpoint {
823*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ucam0>;
824*4882a593Smuzhiyun				data-lanes = <1>;
825*4882a593Smuzhiyun			};
826*4882a593Smuzhiyun		};
827*4882a593Smuzhiyun	};
828*4882a593Smuzhiyun
829*4882a593Smuzhiyun	ov8858: ov8858@36 {
830*4882a593Smuzhiyun		status = "okay";
831*4882a593Smuzhiyun		compatible = "ovti,ov8858";
832*4882a593Smuzhiyun		reg = <0x36>;
833*4882a593Smuzhiyun		clocks = <&cru CLK_CAM0_OUT>;
834*4882a593Smuzhiyun		clock-names = "xvclk";
835*4882a593Smuzhiyun		power-domains = <&power RK3568_PD_VI>;
836*4882a593Smuzhiyun		pinctrl-names = "rockchip,camera_default", "rockchip,camera_sleep";
837*4882a593Smuzhiyun		pinctrl-0 = <&cam_clkout0>;
838*4882a593Smuzhiyun		pinctrl-1 = <&cam_sleep>;
839*4882a593Smuzhiyun		//reset pin control by hardware,used this pin switch to mipi input
840*4882a593Smuzhiyun		//1->2LANE(LANE 0&1) FRONT camera, 0->4LANE REAR camera
841*4882a593Smuzhiyun		reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
842*4882a593Smuzhiyun		pwdn-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
843*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
844*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
845*4882a593Smuzhiyun		rockchip,camera-module-name = "HS5885-BNSM1018-V01";
846*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "default";
847*4882a593Smuzhiyun		flash-leds = <&flash_rgb13h>;
848*4882a593Smuzhiyun		lens-focus = <&dw9714>;
849*4882a593Smuzhiyun		port {
850*4882a593Smuzhiyun			ov8858_out: endpoint {
851*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ucam1>;
852*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
853*4882a593Smuzhiyun			};
854*4882a593Smuzhiyun		};
855*4882a593Smuzhiyun	};
856*4882a593Smuzhiyun};
857*4882a593Smuzhiyun
858*4882a593Smuzhiyun&i2c3 {
859*4882a593Smuzhiyun	status = "okay";
860*4882a593Smuzhiyun	pinctrl-names = "default";
861*4882a593Smuzhiyun	pinctrl-0 = <&i2c3m1_xfer>;
862*4882a593Smuzhiyun	clock-frequency = <400000>;
863*4882a593Smuzhiyun	i2c-scl-rising-time-ns = <138>;
864*4882a593Smuzhiyun	i2c-scl-falling-time-ns = <4>;
865*4882a593Smuzhiyun
866*4882a593Smuzhiyun	ts@40 {
867*4882a593Smuzhiyun		compatible = "gslX680-pad";
868*4882a593Smuzhiyun		reg = <0x40>;
869*4882a593Smuzhiyun		touch-gpio = <&gpio3 RK_PB0 IRQ_TYPE_LEVEL_HIGH>;
870*4882a593Smuzhiyun		reset-gpio = <&gpio3 RK_PB1 IRQ_TYPE_LEVEL_HIGH>;
871*4882a593Smuzhiyun		pinctrl-names = "default";
872*4882a593Smuzhiyun		pinctrl-0 = <&tp_gpio>;
873*4882a593Smuzhiyun		screen_max_x = <1200>;
874*4882a593Smuzhiyun		screen_max_y = <1920>;
875*4882a593Smuzhiyun		revert_x = <0>;
876*4882a593Smuzhiyun		revert_y = <1>;
877*4882a593Smuzhiyun		revert_xy = <0>;
878*4882a593Smuzhiyun		chip_id = <1>;
879*4882a593Smuzhiyun		status = "okay";
880*4882a593Smuzhiyun	};
881*4882a593Smuzhiyun};
882*4882a593Smuzhiyun
883*4882a593Smuzhiyun&i2c5 {
884*4882a593Smuzhiyun	status = "okay";
885*4882a593Smuzhiyun	clock-frequency = <400000>;
886*4882a593Smuzhiyun	i2c-scl-rising-time-ns = <144>;
887*4882a593Smuzhiyun	i2c-scl-falling-time-ns = <4>;
888*4882a593Smuzhiyun
889*4882a593Smuzhiyun	sensor@18 {
890*4882a593Smuzhiyun		compatible = "gs_sc7a20";
891*4882a593Smuzhiyun		reg = <0x18>;
892*4882a593Smuzhiyun		type = <SENSOR_TYPE_ACCEL>;
893*4882a593Smuzhiyun		irq_enable = <0>;
894*4882a593Smuzhiyun		pinctrl-names = "default";
895*4882a593Smuzhiyun		pinctrl-0 = <&sensor_gpio>;
896*4882a593Smuzhiyun		irq-gpio = <&gpio3 RK_PA2 IRQ_TYPE_EDGE_RISING>;
897*4882a593Smuzhiyun		poll_delay_ms = <10>;
898*4882a593Smuzhiyun		layout = <1>;
899*4882a593Smuzhiyun	};
900*4882a593Smuzhiyun};
901*4882a593Smuzhiyun
902*4882a593Smuzhiyun&i2s0_8ch {
903*4882a593Smuzhiyun	status = "okay";
904*4882a593Smuzhiyun};
905*4882a593Smuzhiyun
906*4882a593Smuzhiyun&i2s1_8ch {
907*4882a593Smuzhiyun	status = "okay";
908*4882a593Smuzhiyun	rockchip,clk-trcm = <1>;
909*4882a593Smuzhiyun	pinctrl-names = "default";
910*4882a593Smuzhiyun	pinctrl-0 = <&i2s1m0_sclktx
911*4882a593Smuzhiyun		     &i2s1m0_lrcktx
912*4882a593Smuzhiyun		     &i2s1m0_sdi0
913*4882a593Smuzhiyun		     &i2s1m0_sdo0>;
914*4882a593Smuzhiyun};
915*4882a593Smuzhiyun
916*4882a593Smuzhiyun&jpegd {
917*4882a593Smuzhiyun	status = "okay";
918*4882a593Smuzhiyun};
919*4882a593Smuzhiyun
920*4882a593Smuzhiyun&jpegd_mmu {
921*4882a593Smuzhiyun	status = "okay";
922*4882a593Smuzhiyun};
923*4882a593Smuzhiyun
924*4882a593Smuzhiyun&video_phy0 {
925*4882a593Smuzhiyun	status = "okay";
926*4882a593Smuzhiyun};
927*4882a593Smuzhiyun
928*4882a593Smuzhiyun&mpp_srv {
929*4882a593Smuzhiyun	status = "okay";
930*4882a593Smuzhiyun};
931*4882a593Smuzhiyun
932*4882a593Smuzhiyun&nandc0 {
933*4882a593Smuzhiyun	status = "okay";
934*4882a593Smuzhiyun};
935*4882a593Smuzhiyun
936*4882a593Smuzhiyun&pinctrl {
937*4882a593Smuzhiyun	cam {
938*4882a593Smuzhiyun		cam_clkout0: cam-clkout0 {
939*4882a593Smuzhiyun			rockchip,pins =
940*4882a593Smuzhiyun				/* cam_clkout0 */
941*4882a593Smuzhiyun				<4 RK_PA7 1 &pcfg_pull_none>;
942*4882a593Smuzhiyun		};
943*4882a593Smuzhiyun
944*4882a593Smuzhiyun		cam_sleep: cam-sleep {
945*4882a593Smuzhiyun			rockchip,pins =
946*4882a593Smuzhiyun				/* cam_sleep */
947*4882a593Smuzhiyun				<4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
948*4882a593Smuzhiyun		};
949*4882a593Smuzhiyun
950*4882a593Smuzhiyun		camera_rst: camera-rst {
951*4882a593Smuzhiyun			rockchip,pins =
952*4882a593Smuzhiyun				/* front camera reset */
953*4882a593Smuzhiyun				<4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>,
954*4882a593Smuzhiyun				/* back camra reset */
955*4882a593Smuzhiyun				<4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
956*4882a593Smuzhiyun		};
957*4882a593Smuzhiyun
958*4882a593Smuzhiyun		flash_led_gpios: flash-led {
959*4882a593Smuzhiyun			rockchip,pins =
960*4882a593Smuzhiyun				/* flash led enable */
961*4882a593Smuzhiyun				<4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
962*4882a593Smuzhiyun		};
963*4882a593Smuzhiyun	};
964*4882a593Smuzhiyun
965*4882a593Smuzhiyun	tp {
966*4882a593Smuzhiyun		tp_gpio: tp-gpio {
967*4882a593Smuzhiyun			rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>,
968*4882a593Smuzhiyun					<3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
969*4882a593Smuzhiyun		};
970*4882a593Smuzhiyun	};
971*4882a593Smuzhiyun
972*4882a593Smuzhiyun	headphone {
973*4882a593Smuzhiyun		hp_det: hp-det {
974*4882a593Smuzhiyun			rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
975*4882a593Smuzhiyun		};
976*4882a593Smuzhiyun	};
977*4882a593Smuzhiyun
978*4882a593Smuzhiyun	lcd {
979*4882a593Smuzhiyun		lcd_rst_gpio: lcd-rst-gpio {
980*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
981*4882a593Smuzhiyun		};
982*4882a593Smuzhiyun
983*4882a593Smuzhiyun		lcd_enable_gpio: lcd-enable-gpio {
984*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
985*4882a593Smuzhiyun		};
986*4882a593Smuzhiyun
987*4882a593Smuzhiyun		lcd_stanby_gpio: lcd-stanby-gpio {
988*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>;
989*4882a593Smuzhiyun		};
990*4882a593Smuzhiyun	};
991*4882a593Smuzhiyun
992*4882a593Smuzhiyun	pmic {
993*4882a593Smuzhiyun		pmic_int: pmic_int {
994*4882a593Smuzhiyun			rockchip,pins =
995*4882a593Smuzhiyun				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
996*4882a593Smuzhiyun		};
997*4882a593Smuzhiyun
998*4882a593Smuzhiyun		soc_slppin_gpio: soc_slppin_gpio {
999*4882a593Smuzhiyun			rockchip,pins =
1000*4882a593Smuzhiyun				<0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>;
1001*4882a593Smuzhiyun		};
1002*4882a593Smuzhiyun
1003*4882a593Smuzhiyun		soc_slppin_slp: soc_slppin_slp {
1004*4882a593Smuzhiyun			rockchip,pins =
1005*4882a593Smuzhiyun				<0 RK_PA2 1 &pcfg_pull_none>;
1006*4882a593Smuzhiyun		};
1007*4882a593Smuzhiyun
1008*4882a593Smuzhiyun		soc_slppin_rst: soc_slppin_rst {
1009*4882a593Smuzhiyun			rockchip,pins =
1010*4882a593Smuzhiyun				<0 RK_PA2 2 &pcfg_pull_none>;
1011*4882a593Smuzhiyun		};
1012*4882a593Smuzhiyun	};
1013*4882a593Smuzhiyun
1014*4882a593Smuzhiyun	sensor {
1015*4882a593Smuzhiyun		sensor_gpio: sensor-gpio {
1016*4882a593Smuzhiyun			rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
1017*4882a593Smuzhiyun		};
1018*4882a593Smuzhiyun	};
1019*4882a593Smuzhiyun
1020*4882a593Smuzhiyun	sdio-pwrseq {
1021*4882a593Smuzhiyun		wifi_enable_h: wifi-enable-h {
1022*4882a593Smuzhiyun			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
1023*4882a593Smuzhiyun		};
1024*4882a593Smuzhiyun	};
1025*4882a593Smuzhiyun
1026*4882a593Smuzhiyun	vcc_sd {
1027*4882a593Smuzhiyun		vcc_sd_h: vcc-sd-h {
1028*4882a593Smuzhiyun			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1029*4882a593Smuzhiyun		};
1030*4882a593Smuzhiyun	};
1031*4882a593Smuzhiyun
1032*4882a593Smuzhiyun	wireless-wlan {
1033*4882a593Smuzhiyun		wifi_host_wake_irq: wifi-host-wake-irq {
1034*4882a593Smuzhiyun			rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>;
1035*4882a593Smuzhiyun		};
1036*4882a593Smuzhiyun	};
1037*4882a593Smuzhiyun
1038*4882a593Smuzhiyun	wireless-bluetooth {
1039*4882a593Smuzhiyun		uart1_gpios: uart1-gpios {
1040*4882a593Smuzhiyun			rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1041*4882a593Smuzhiyun		};
1042*4882a593Smuzhiyun	};
1043*4882a593Smuzhiyun};
1044*4882a593Smuzhiyun
1045*4882a593Smuzhiyun&pmu_io_domains {
1046*4882a593Smuzhiyun	status = "okay";
1047*4882a593Smuzhiyun	pmuio1-supply = <&vcc3v3_pmu>;
1048*4882a593Smuzhiyun	pmuio2-supply = <&vcc3v3_pmu>;
1049*4882a593Smuzhiyun	vccio1-supply = <&vccio_acodec>;
1050*4882a593Smuzhiyun	vccio3-supply = <&vccio_sd>;
1051*4882a593Smuzhiyun	vccio4-supply = <&vcca1v8_pmu>;
1052*4882a593Smuzhiyun	vccio5-supply = <&vcc_1v8>;
1053*4882a593Smuzhiyun	vccio6-supply = <&vcc1v8_dvp>;
1054*4882a593Smuzhiyun	vccio7-supply = <&vcc_3v3>;
1055*4882a593Smuzhiyun};
1056*4882a593Smuzhiyun
1057*4882a593Smuzhiyun&pwm4 {
1058*4882a593Smuzhiyun	status = "okay";
1059*4882a593Smuzhiyun};
1060*4882a593Smuzhiyun
1061*4882a593Smuzhiyun&rk_rga {
1062*4882a593Smuzhiyun	status = "okay";
1063*4882a593Smuzhiyun};
1064*4882a593Smuzhiyun
1065*4882a593Smuzhiyun&rkisp {
1066*4882a593Smuzhiyun	status = "okay";
1067*4882a593Smuzhiyun};
1068*4882a593Smuzhiyun
1069*4882a593Smuzhiyun&rkisp_mmu {
1070*4882a593Smuzhiyun	status = "okay";
1071*4882a593Smuzhiyun};
1072*4882a593Smuzhiyun
1073*4882a593Smuzhiyun&rkisp_vir0 {
1074*4882a593Smuzhiyun	status = "okay";
1075*4882a593Smuzhiyun
1076*4882a593Smuzhiyun	port {
1077*4882a593Smuzhiyun		#address-cells = <1>;
1078*4882a593Smuzhiyun		#size-cells = <0>;
1079*4882a593Smuzhiyun
1080*4882a593Smuzhiyun		isp0_in: endpoint@0 {
1081*4882a593Smuzhiyun			reg = <0>;
1082*4882a593Smuzhiyun			remote-endpoint = <&csidphy0_out>;
1083*4882a593Smuzhiyun		};
1084*4882a593Smuzhiyun	};
1085*4882a593Smuzhiyun};
1086*4882a593Smuzhiyun
1087*4882a593Smuzhiyun&rkvdec {
1088*4882a593Smuzhiyun	status = "okay";
1089*4882a593Smuzhiyun};
1090*4882a593Smuzhiyun
1091*4882a593Smuzhiyun&rkvdec_mmu {
1092*4882a593Smuzhiyun	status = "okay";
1093*4882a593Smuzhiyun};
1094*4882a593Smuzhiyun
1095*4882a593Smuzhiyun&rkvenc {
1096*4882a593Smuzhiyun	status = "okay";
1097*4882a593Smuzhiyun};
1098*4882a593Smuzhiyun
1099*4882a593Smuzhiyun&rkvenc_mmu {
1100*4882a593Smuzhiyun	status = "okay";
1101*4882a593Smuzhiyun};
1102*4882a593Smuzhiyun
1103*4882a593Smuzhiyun&route_dsi0 {
1104*4882a593Smuzhiyun	status = "okay";
1105*4882a593Smuzhiyun};
1106*4882a593Smuzhiyun
1107*4882a593Smuzhiyun&route_hdmi {
1108*4882a593Smuzhiyun	status = "okay";
1109*4882a593Smuzhiyun	connect = <&vp0_out_hdmi>;
1110*4882a593Smuzhiyun};
1111*4882a593Smuzhiyun
1112*4882a593Smuzhiyun&saradc {
1113*4882a593Smuzhiyun	status = "okay";
1114*4882a593Smuzhiyun	vref-supply = <&vcc_1v8>;
1115*4882a593Smuzhiyun};
1116*4882a593Smuzhiyun
1117*4882a593Smuzhiyun&sdhci {
1118*4882a593Smuzhiyun	bus-width = <8>;
1119*4882a593Smuzhiyun	no-sdio;
1120*4882a593Smuzhiyun	no-sd;
1121*4882a593Smuzhiyun	non-removable;
1122*4882a593Smuzhiyun	max-frequency = <200000000>;
1123*4882a593Smuzhiyun	status = "okay";
1124*4882a593Smuzhiyun};
1125*4882a593Smuzhiyun
1126*4882a593Smuzhiyun&sdmmc0 {
1127*4882a593Smuzhiyun	max-frequency = <150000000>;
1128*4882a593Smuzhiyun	no-sdio;
1129*4882a593Smuzhiyun	no-mmc;
1130*4882a593Smuzhiyun	bus-width = <4>;
1131*4882a593Smuzhiyun	cap-mmc-highspeed;
1132*4882a593Smuzhiyun	cap-sd-highspeed;
1133*4882a593Smuzhiyun	disable-wp;
1134*4882a593Smuzhiyun	sd-uhs-sdr104;
1135*4882a593Smuzhiyun	vmmc-supply = <&vcc_sd>;
1136*4882a593Smuzhiyun	vqmmc-supply = <&vccio_sd>;
1137*4882a593Smuzhiyun	pinctrl-names = "default";
1138*4882a593Smuzhiyun	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
1139*4882a593Smuzhiyun	status = "okay";
1140*4882a593Smuzhiyun};
1141*4882a593Smuzhiyun
1142*4882a593Smuzhiyun&sdmmc1 {
1143*4882a593Smuzhiyun	max-frequency = <150000000>;
1144*4882a593Smuzhiyun	no-sd;
1145*4882a593Smuzhiyun	no-mmc;
1146*4882a593Smuzhiyun	bus-width = <4>;
1147*4882a593Smuzhiyun	disable-wp;
1148*4882a593Smuzhiyun	cap-sd-highspeed;
1149*4882a593Smuzhiyun	cap-sdio-irq;
1150*4882a593Smuzhiyun	keep-power-in-suspend;
1151*4882a593Smuzhiyun	mmc-pwrseq = <&sdio_pwrseq>;
1152*4882a593Smuzhiyun	non-removable;
1153*4882a593Smuzhiyun	pinctrl-names = "default";
1154*4882a593Smuzhiyun	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
1155*4882a593Smuzhiyun	sd-uhs-sdr104;
1156*4882a593Smuzhiyun	rockchip,default-sample-phase = <90>;
1157*4882a593Smuzhiyun	status = "okay";
1158*4882a593Smuzhiyun};
1159*4882a593Smuzhiyun
1160*4882a593Smuzhiyun&tsadc {
1161*4882a593Smuzhiyun	status = "okay";
1162*4882a593Smuzhiyun};
1163*4882a593Smuzhiyun
1164*4882a593Smuzhiyun&uart1 {
1165*4882a593Smuzhiyun	status = "okay";
1166*4882a593Smuzhiyun	pinctrl-names = "default";
1167*4882a593Smuzhiyun	pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
1168*4882a593Smuzhiyun};
1169*4882a593Smuzhiyun
1170*4882a593Smuzhiyun&u2phy0_otg {
1171*4882a593Smuzhiyun	status = "okay";
1172*4882a593Smuzhiyun};
1173*4882a593Smuzhiyun
1174*4882a593Smuzhiyun&usb2phy0 {
1175*4882a593Smuzhiyun	status = "okay";
1176*4882a593Smuzhiyun};
1177*4882a593Smuzhiyun
1178*4882a593Smuzhiyun&usbdrd_dwc3 {
1179*4882a593Smuzhiyun	status = "okay";
1180*4882a593Smuzhiyun};
1181*4882a593Smuzhiyun
1182*4882a593Smuzhiyun&usbdrd30 {
1183*4882a593Smuzhiyun	status = "okay";
1184*4882a593Smuzhiyun};
1185*4882a593Smuzhiyun
1186*4882a593Smuzhiyun&vdpu {
1187*4882a593Smuzhiyun	status = "okay";
1188*4882a593Smuzhiyun};
1189*4882a593Smuzhiyun
1190*4882a593Smuzhiyun&vdpu_mmu {
1191*4882a593Smuzhiyun	status = "okay";
1192*4882a593Smuzhiyun};
1193*4882a593Smuzhiyun
1194*4882a593Smuzhiyun&vepu {
1195*4882a593Smuzhiyun	status = "okay";
1196*4882a593Smuzhiyun};
1197*4882a593Smuzhiyun
1198*4882a593Smuzhiyun&vepu_mmu {
1199*4882a593Smuzhiyun	status = "okay";
1200*4882a593Smuzhiyun};
1201*4882a593Smuzhiyun
1202*4882a593Smuzhiyun&vop {
1203*4882a593Smuzhiyun	status = "okay";
1204*4882a593Smuzhiyun};
1205*4882a593Smuzhiyun
1206*4882a593Smuzhiyun&vop_mmu {
1207*4882a593Smuzhiyun	status = "okay";
1208*4882a593Smuzhiyun};
1209