1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 10*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h> 11*4882a593Smuzhiyun#include <dt-bindings/input/rk-input.h> 12*4882a593Smuzhiyun#include <dt-bindings/sensor-dev.h> 13*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h> 14*4882a593Smuzhiyun#include "rk3566.dtsi" 15*4882a593Smuzhiyun#include "rk3568-android.dtsi" 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun/ { 18*4882a593Smuzhiyun model = "Rockchip RK3566 RK817 TABLET K108 LP4X Board"; 19*4882a593Smuzhiyun compatible = "rockchip,rk3566-rk817-tablet-k108", "rockchip,rk3566"; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun adc_keys: adc-keys { 22*4882a593Smuzhiyun compatible = "adc-keys"; 23*4882a593Smuzhiyun io-channels = <&saradc 0>; 24*4882a593Smuzhiyun io-channel-names = "buttons"; 25*4882a593Smuzhiyun keyup-threshold-microvolt = <1800000>; 26*4882a593Smuzhiyun poll-interval = <100>; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun vol-up-key { 29*4882a593Smuzhiyun label = "volume up"; 30*4882a593Smuzhiyun linux,code = <KEY_VOLUMEUP>; 31*4882a593Smuzhiyun press-threshold-microvolt = <1750>; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun vol-down-key { 35*4882a593Smuzhiyun label = "volume down"; 36*4882a593Smuzhiyun linux,code = <KEY_VOLUMEDOWN>; 37*4882a593Smuzhiyun press-threshold-microvolt = <297500>; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun backlight: backlight { 42*4882a593Smuzhiyun compatible = "pwm-backlight"; 43*4882a593Smuzhiyun pwms = <&pwm4 0 25000 0>; 44*4882a593Smuzhiyun brightness-levels = < 45*4882a593Smuzhiyun 0 20 20 21 21 22 22 23 46*4882a593Smuzhiyun 23 24 24 25 25 26 26 27 47*4882a593Smuzhiyun 27 28 28 29 29 30 30 31 48*4882a593Smuzhiyun 31 32 32 33 33 34 34 35 49*4882a593Smuzhiyun 35 36 36 37 37 38 38 39 50*4882a593Smuzhiyun 40 41 42 43 44 45 46 47 51*4882a593Smuzhiyun 48 49 50 51 52 53 54 55 52*4882a593Smuzhiyun 56 57 58 59 60 61 62 63 53*4882a593Smuzhiyun 64 65 66 67 68 69 70 71 54*4882a593Smuzhiyun 72 73 74 75 76 77 78 79 55*4882a593Smuzhiyun 80 81 82 83 84 85 86 87 56*4882a593Smuzhiyun 88 89 90 91 92 93 94 95 57*4882a593Smuzhiyun 96 97 98 99 100 101 102 103 58*4882a593Smuzhiyun 104 105 106 107 108 109 110 111 59*4882a593Smuzhiyun 112 113 114 115 116 117 118 119 60*4882a593Smuzhiyun 120 121 122 123 124 125 126 127 61*4882a593Smuzhiyun 128 129 130 131 132 133 134 135 62*4882a593Smuzhiyun 136 137 138 139 140 141 142 143 63*4882a593Smuzhiyun 144 145 146 147 148 149 150 151 64*4882a593Smuzhiyun 152 153 154 155 156 157 158 159 65*4882a593Smuzhiyun 160 161 162 163 164 165 166 167 66*4882a593Smuzhiyun 168 169 170 171 172 173 174 175 67*4882a593Smuzhiyun 176 177 178 179 180 181 182 183 68*4882a593Smuzhiyun 184 185 186 187 188 189 190 191 69*4882a593Smuzhiyun 192 193 194 195 196 197 198 199 70*4882a593Smuzhiyun 200 201 202 203 204 205 206 207 71*4882a593Smuzhiyun 208 209 210 211 212 213 214 215 72*4882a593Smuzhiyun 216 217 218 219 220 221 222 223 73*4882a593Smuzhiyun 224 225 226 227 228 229 230 231 74*4882a593Smuzhiyun 232 233 234 235 236 237 238 239 75*4882a593Smuzhiyun 240 241 242 243 244 245 246 247 76*4882a593Smuzhiyun 248 249 250 251 252 253 254 255 77*4882a593Smuzhiyun >; 78*4882a593Smuzhiyun default-brightness-level = <200>; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun charge-animation { 82*4882a593Smuzhiyun compatible = "rockchip,uboot-charge"; 83*4882a593Smuzhiyun rockchip,uboot-charge-on = <1>; 84*4882a593Smuzhiyun rockchip,android-charge-on = <0>; 85*4882a593Smuzhiyun rockchip,uboot-low-power-voltage = <3350>; 86*4882a593Smuzhiyun rockchip,screen-on-voltage = <3400>; 87*4882a593Smuzhiyun status = "okay"; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun flash_rgb13h: flash-rgb13h { 91*4882a593Smuzhiyun status = "okay"; 92*4882a593Smuzhiyun compatible = "led,rgb13h"; 93*4882a593Smuzhiyun label = "gpio-flash"; 94*4882a593Smuzhiyun pinctrl-names = "default"; 95*4882a593Smuzhiyun pinctrl-0 = <&flash_led_gpios>; 96*4882a593Smuzhiyun led-max-microamp = <20000>; 97*4882a593Smuzhiyun flash-max-microamp = <20000>; 98*4882a593Smuzhiyun flash-max-timeout-us = <1000000>; 99*4882a593Smuzhiyun enable-gpio = <&gpio4 RK_PB7 GPIO_ACTIVE_HIGH>; 100*4882a593Smuzhiyun rockchip,camera-module-index = <0>; 101*4882a593Smuzhiyun rockchip,camera-module-facing = "back"; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun hall_sensor: hall-mh248 { 105*4882a593Smuzhiyun compatible = "hall-mh248"; 106*4882a593Smuzhiyun irq-gpio = <&gpio3 RK_PA6 IRQ_TYPE_EDGE_BOTH>; 107*4882a593Smuzhiyun hall-active = <1>; 108*4882a593Smuzhiyun status = "okay"; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun hdmi_sound: hdmi-sound { 112*4882a593Smuzhiyun compatible = "simple-audio-card"; 113*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 114*4882a593Smuzhiyun simple-audio-card,mclk-fs = <128>; 115*4882a593Smuzhiyun simple-audio-card,name = "rockchip,hdmi"; 116*4882a593Smuzhiyun status = "okay"; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun simple-audio-card,cpu { 119*4882a593Smuzhiyun sound-dai = <&i2s0_8ch>; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun simple-audio-card,codec { 122*4882a593Smuzhiyun sound-dai = <&hdmi>; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun vccsys: vccsys { 127*4882a593Smuzhiyun compatible = "regulator-fixed"; 128*4882a593Smuzhiyun regulator-name = "vcc3v8_sys"; 129*4882a593Smuzhiyun regulator-always-on; 130*4882a593Smuzhiyun regulator-boot-on; 131*4882a593Smuzhiyun regulator-min-microvolt = <3800000>; 132*4882a593Smuzhiyun regulator-max-microvolt = <3800000>; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun vcc_camera: vcc-camera-regulator { 136*4882a593Smuzhiyun compatible = "regulator-fixed"; 137*4882a593Smuzhiyun gpio = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; 138*4882a593Smuzhiyun pinctrl-names = "default"; 139*4882a593Smuzhiyun pinctrl-0 = <&camera_rst>; 140*4882a593Smuzhiyun regulator-name = "vcc_camera"; 141*4882a593Smuzhiyun enable-active-high; 142*4882a593Smuzhiyun regulator-always-on; 143*4882a593Smuzhiyun regulator-boot-on; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun rk817-sound { 147*4882a593Smuzhiyun compatible = "simple-audio-card"; 148*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 149*4882a593Smuzhiyun simple-audio-card,name = "rockchip,rk817-codec"; 150*4882a593Smuzhiyun simple-audio-card,mclk-fs = <256>; 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun simple-audio-card,cpu { 153*4882a593Smuzhiyun sound-dai = <&i2s1_8ch>; 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun simple-audio-card,codec { 156*4882a593Smuzhiyun sound-dai = <&rk817_codec>; 157*4882a593Smuzhiyun }; 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun rk_headset: rk-headset { 161*4882a593Smuzhiyun compatible = "rockchip_headset"; 162*4882a593Smuzhiyun headset_gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; 163*4882a593Smuzhiyun pinctrl-names = "default"; 164*4882a593Smuzhiyun pinctrl-0 = <&hp_det>; 165*4882a593Smuzhiyun io-channels = <&saradc 2>; 166*4882a593Smuzhiyun }; 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun sdio_pwrseq: sdio-pwrseq { 169*4882a593Smuzhiyun compatible = "mmc-pwrseq-simple"; 170*4882a593Smuzhiyun clocks = <&rk817 1>; 171*4882a593Smuzhiyun clock-names = "ext_clock"; 172*4882a593Smuzhiyun pinctrl-names = "default"; 173*4882a593Smuzhiyun pinctrl-0 = <&wifi_enable_h>; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun /* 176*4882a593Smuzhiyun * On the module itself this is one of these (depending 177*4882a593Smuzhiyun * on the actual card populated): 178*4882a593Smuzhiyun * - SDIO_RESET_L_WL_REG_ON 179*4882a593Smuzhiyun * - PDN (power down when low) 180*4882a593Smuzhiyun */ 181*4882a593Smuzhiyun post-power-on-delay-ms = <200>; 182*4882a593Smuzhiyun reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun vcc_sd: vcc-sd { 186*4882a593Smuzhiyun compatible = "regulator-gpio"; 187*4882a593Smuzhiyun enable-active-low; 188*4882a593Smuzhiyun enable-gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; 189*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 190*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 191*4882a593Smuzhiyun pinctrl-names = "default"; 192*4882a593Smuzhiyun pinctrl-0 = <&vcc_sd_h>; 193*4882a593Smuzhiyun regulator-name = "vcc_sd"; 194*4882a593Smuzhiyun states = <3300000 0x0 195*4882a593Smuzhiyun 3300000 0x1>; 196*4882a593Smuzhiyun }; 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun vcc5v0_host: vcc5v0-host-regulator { 199*4882a593Smuzhiyun compatible = "regulator-fixed"; 200*4882a593Smuzhiyun enable-active-high; 201*4882a593Smuzhiyun gpio = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; 202*4882a593Smuzhiyun pinctrl-names = "default"; 203*4882a593Smuzhiyun pinctrl-0 = <&vcc5v0_host_en>; 204*4882a593Smuzhiyun regulator-name = "vcc5v0_host"; 205*4882a593Smuzhiyun regulator-always-on; 206*4882a593Smuzhiyun }; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun wireless-wlan { 209*4882a593Smuzhiyun compatible = "wlan-platdata"; 210*4882a593Smuzhiyun rockchip,grf = <&grf>; 211*4882a593Smuzhiyun wifi_chip_type = "rtl8723cs"; 212*4882a593Smuzhiyun pinctrl-names = "default"; 213*4882a593Smuzhiyun pinctrl-0 = <&wifi_host_wake_irq>; 214*4882a593Smuzhiyun WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; 215*4882a593Smuzhiyun WIFI,vbat_gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_LOW>; 216*4882a593Smuzhiyun WIFI,poweren_gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; 217*4882a593Smuzhiyun status = "okay"; 218*4882a593Smuzhiyun }; 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun wireless-bluetooth { 221*4882a593Smuzhiyun compatible = "bluetooth-platdata"; 222*4882a593Smuzhiyun clocks = <&rk817 1>; 223*4882a593Smuzhiyun clock-names = "ext_clock"; 224*4882a593Smuzhiyun //wifi-bt-power-toggle; 225*4882a593Smuzhiyun uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; 226*4882a593Smuzhiyun pinctrl-names = "default", "rts_gpio"; 227*4882a593Smuzhiyun pinctrl-0 = <&uart1m0_rtsn>; 228*4882a593Smuzhiyun pinctrl-1 = <&uart1_gpios>; 229*4882a593Smuzhiyun BT,reset_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; 230*4882a593Smuzhiyun BT,wake_gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; 231*4882a593Smuzhiyun BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; 232*4882a593Smuzhiyun status = "okay"; 233*4882a593Smuzhiyun }; 234*4882a593Smuzhiyun}; 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun&combphy1_usq { 237*4882a593Smuzhiyun rockchip,dis-u3otg1-port; 238*4882a593Smuzhiyun status = "okay"; 239*4882a593Smuzhiyun}; 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun&cpu0 { 242*4882a593Smuzhiyun cpu-supply = <&vdd_cpu>; 243*4882a593Smuzhiyun}; 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun&csi2_dphy_hw { 246*4882a593Smuzhiyun status = "okay"; 247*4882a593Smuzhiyun}; 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun&csi2_dphy0 { 250*4882a593Smuzhiyun status = "okay"; 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun ports { 253*4882a593Smuzhiyun #address-cells = <1>; 254*4882a593Smuzhiyun #size-cells = <0>; 255*4882a593Smuzhiyun port@0 { 256*4882a593Smuzhiyun reg = <0>; 257*4882a593Smuzhiyun #address-cells = <1>; 258*4882a593Smuzhiyun #size-cells = <0>; 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun mipi_in_ucam0: endpoint@0 { 261*4882a593Smuzhiyun reg = <0>; 262*4882a593Smuzhiyun remote-endpoint = <&gc2385_out>; 263*4882a593Smuzhiyun data-lanes = <1>; 264*4882a593Smuzhiyun }; 265*4882a593Smuzhiyun mipi_in_ucam1: endpoint@1 { 266*4882a593Smuzhiyun reg = <1>; 267*4882a593Smuzhiyun remote-endpoint = <&ov8858_out>; 268*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 269*4882a593Smuzhiyun }; 270*4882a593Smuzhiyun }; 271*4882a593Smuzhiyun port@1 { 272*4882a593Smuzhiyun reg = <1>; 273*4882a593Smuzhiyun #address-cells = <1>; 274*4882a593Smuzhiyun #size-cells = <0>; 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun csidphy0_out: endpoint@0 { 277*4882a593Smuzhiyun reg = <0>; 278*4882a593Smuzhiyun remote-endpoint = <&isp0_in>; 279*4882a593Smuzhiyun }; 280*4882a593Smuzhiyun }; 281*4882a593Smuzhiyun }; 282*4882a593Smuzhiyun}; 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun&dsi0 { 285*4882a593Smuzhiyun status = "okay"; 286*4882a593Smuzhiyun rockchip,lane-rate = <1000>; 287*4882a593Smuzhiyun panel@0 { 288*4882a593Smuzhiyun compatible = "aoly,sl008pa21y1285-b00", "simple-panel-dsi"; 289*4882a593Smuzhiyun reg = <0>; 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun backlight = <&backlight>; 292*4882a593Smuzhiyun power-supply=<&vcc_3v3>; 293*4882a593Smuzhiyun enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; 294*4882a593Smuzhiyun stbyb-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; 295*4882a593Smuzhiyun reset-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun pinctrl-names = "default"; 298*4882a593Smuzhiyun pinctrl-0 = <&lcd_enable_gpio>, <&lcd_rst_gpio>, <&lcd_stanby_gpio>; 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun prepare-delay-ms = <120>; 301*4882a593Smuzhiyun reset-delay-ms = <120>; 302*4882a593Smuzhiyun init-delay-ms = <120>; 303*4882a593Smuzhiyun stbyb-delay-ms = <120>; 304*4882a593Smuzhiyun enable-delay-ms = <120>; 305*4882a593Smuzhiyun disable-delay-ms = <120>; 306*4882a593Smuzhiyun unprepare-delay-ms = <120>; 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun width-mm = <229>; 309*4882a593Smuzhiyun height-mm = <143>; 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 312*4882a593Smuzhiyun MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; 313*4882a593Smuzhiyun dsi,format = <MIPI_DSI_FMT_RGB888>; 314*4882a593Smuzhiyun dsi,lanes = <4>; 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun panel-init-sequence = [ 317*4882a593Smuzhiyun 29 00 04 FF 98 81 03 318*4882a593Smuzhiyun 23 00 02 01 00 319*4882a593Smuzhiyun 23 00 02 02 00 320*4882a593Smuzhiyun 23 00 02 03 73 321*4882a593Smuzhiyun 23 00 02 04 00 322*4882a593Smuzhiyun 23 00 02 05 00 323*4882a593Smuzhiyun 23 00 02 06 08 324*4882a593Smuzhiyun 23 00 02 07 00 325*4882a593Smuzhiyun 23 00 02 08 00 326*4882a593Smuzhiyun 23 00 02 09 00 327*4882a593Smuzhiyun 23 00 02 0A 01 328*4882a593Smuzhiyun 23 00 02 0B 01 329*4882a593Smuzhiyun 23 00 02 0C 00 330*4882a593Smuzhiyun 23 00 02 0D 01 331*4882a593Smuzhiyun 23 00 02 0E 01 332*4882a593Smuzhiyun 23 00 02 0F 00 333*4882a593Smuzhiyun 23 00 02 10 00 334*4882a593Smuzhiyun 23 00 02 11 00 335*4882a593Smuzhiyun 23 00 02 12 00 336*4882a593Smuzhiyun 23 00 02 13 1F 337*4882a593Smuzhiyun 23 00 02 14 1F 338*4882a593Smuzhiyun 23 00 02 15 00 339*4882a593Smuzhiyun 23 00 02 16 00 340*4882a593Smuzhiyun 23 00 02 17 00 341*4882a593Smuzhiyun 23 00 02 18 00 342*4882a593Smuzhiyun 23 00 02 19 00 343*4882a593Smuzhiyun 23 00 02 1A 00 344*4882a593Smuzhiyun 23 00 02 1B 00 345*4882a593Smuzhiyun 23 00 02 1C 00 346*4882a593Smuzhiyun 23 00 02 1D 00 347*4882a593Smuzhiyun 23 00 02 1E 40 348*4882a593Smuzhiyun 23 00 02 1F C0 349*4882a593Smuzhiyun 23 00 02 20 06 350*4882a593Smuzhiyun 23 00 02 21 01 351*4882a593Smuzhiyun 23 00 02 22 06 352*4882a593Smuzhiyun 23 00 02 23 01 353*4882a593Smuzhiyun 23 00 02 24 88 354*4882a593Smuzhiyun 23 00 02 25 88 355*4882a593Smuzhiyun 23 00 02 26 00 356*4882a593Smuzhiyun 23 00 02 27 00 357*4882a593Smuzhiyun 23 00 02 28 3B 358*4882a593Smuzhiyun 23 00 02 29 03 359*4882a593Smuzhiyun 23 00 02 2A 00 360*4882a593Smuzhiyun 23 00 02 2B 00 361*4882a593Smuzhiyun 23 00 02 2C 00 362*4882a593Smuzhiyun 23 00 02 2D 00 363*4882a593Smuzhiyun 23 00 02 2E 00 364*4882a593Smuzhiyun 23 00 02 2F 00 365*4882a593Smuzhiyun 23 00 02 30 00 366*4882a593Smuzhiyun 23 00 02 31 00 367*4882a593Smuzhiyun 23 00 02 32 00 368*4882a593Smuzhiyun 23 00 02 33 00 369*4882a593Smuzhiyun 23 00 02 34 00 370*4882a593Smuzhiyun 23 00 02 35 00 371*4882a593Smuzhiyun 23 00 02 36 00 372*4882a593Smuzhiyun 23 00 02 37 00 373*4882a593Smuzhiyun 23 00 02 38 00 374*4882a593Smuzhiyun 23 00 02 39 00 375*4882a593Smuzhiyun 23 00 02 3A 00 376*4882a593Smuzhiyun 23 00 02 3B 00 377*4882a593Smuzhiyun 23 00 02 3C 00 378*4882a593Smuzhiyun 23 00 02 3D 00 379*4882a593Smuzhiyun 23 00 02 3E 00 380*4882a593Smuzhiyun 23 00 02 3F 00 381*4882a593Smuzhiyun 23 00 02 40 00 382*4882a593Smuzhiyun 23 00 02 41 00 383*4882a593Smuzhiyun 23 00 02 42 00 384*4882a593Smuzhiyun 23 00 02 43 00 385*4882a593Smuzhiyun 23 00 02 44 00 386*4882a593Smuzhiyun 23 00 02 50 01 387*4882a593Smuzhiyun 23 00 02 51 23 388*4882a593Smuzhiyun 23 00 02 52 45 389*4882a593Smuzhiyun 23 00 02 53 67 390*4882a593Smuzhiyun 23 00 02 54 89 391*4882a593Smuzhiyun 23 00 02 55 AB 392*4882a593Smuzhiyun 23 00 02 56 01 393*4882a593Smuzhiyun 23 00 02 57 23 394*4882a593Smuzhiyun 23 00 02 58 45 395*4882a593Smuzhiyun 23 00 02 59 67 396*4882a593Smuzhiyun 23 00 02 5A 89 397*4882a593Smuzhiyun 23 00 02 5B AB 398*4882a593Smuzhiyun 23 00 02 5C CD 399*4882a593Smuzhiyun 23 00 02 5D EF 400*4882a593Smuzhiyun 23 00 02 5E 00 401*4882a593Smuzhiyun 23 00 02 5F 01 402*4882a593Smuzhiyun 23 00 02 60 01 403*4882a593Smuzhiyun 23 00 02 61 06 404*4882a593Smuzhiyun 23 00 02 62 06 405*4882a593Smuzhiyun 23 00 02 63 07 406*4882a593Smuzhiyun 23 00 02 64 07 407*4882a593Smuzhiyun 23 00 02 65 00 408*4882a593Smuzhiyun 23 00 02 66 00 409*4882a593Smuzhiyun 23 00 02 67 02 410*4882a593Smuzhiyun 23 00 02 68 02 411*4882a593Smuzhiyun 23 00 02 69 05 412*4882a593Smuzhiyun 23 00 02 6A 05 413*4882a593Smuzhiyun 23 00 02 6B 02 414*4882a593Smuzhiyun 23 00 02 6C 0D 415*4882a593Smuzhiyun 23 00 02 6D 0D 416*4882a593Smuzhiyun 23 00 02 6E 0C 417*4882a593Smuzhiyun 23 00 02 6F 0C 418*4882a593Smuzhiyun 23 00 02 70 0F 419*4882a593Smuzhiyun 23 00 02 71 0F 420*4882a593Smuzhiyun 23 00 02 72 0E 421*4882a593Smuzhiyun 23 00 02 73 0E 422*4882a593Smuzhiyun 23 00 02 74 02 423*4882a593Smuzhiyun 23 00 02 75 01 424*4882a593Smuzhiyun 23 00 02 76 01 425*4882a593Smuzhiyun 23 00 02 77 06 426*4882a593Smuzhiyun 23 00 02 78 06 427*4882a593Smuzhiyun 23 00 02 79 07 428*4882a593Smuzhiyun 23 00 02 7A 07 429*4882a593Smuzhiyun 23 00 02 7B 00 430*4882a593Smuzhiyun 23 00 02 7C 00 431*4882a593Smuzhiyun 23 00 02 7D 02 432*4882a593Smuzhiyun 23 00 02 7E 02 433*4882a593Smuzhiyun 23 00 02 7F 05 434*4882a593Smuzhiyun 23 00 02 80 05 435*4882a593Smuzhiyun 23 00 02 81 02 436*4882a593Smuzhiyun 23 00 02 82 0D 437*4882a593Smuzhiyun 23 00 02 83 0D 438*4882a593Smuzhiyun 23 00 02 84 0C 439*4882a593Smuzhiyun 23 00 02 85 0C 440*4882a593Smuzhiyun 23 00 02 86 0F 441*4882a593Smuzhiyun 23 00 02 87 0F 442*4882a593Smuzhiyun 23 00 02 88 0E 443*4882a593Smuzhiyun 23 00 02 89 0E 444*4882a593Smuzhiyun 23 00 02 8A 02 445*4882a593Smuzhiyun 29 00 04 FF 98 81 04 446*4882a593Smuzhiyun 23 00 02 6C 15 447*4882a593Smuzhiyun 23 00 02 6E 2A 448*4882a593Smuzhiyun 23 00 02 6F 33 449*4882a593Smuzhiyun 23 00 02 8D 1B 450*4882a593Smuzhiyun 23 00 02 87 BA 451*4882a593Smuzhiyun 23 00 02 3A 24 452*4882a593Smuzhiyun 23 00 02 26 76 453*4882a593Smuzhiyun 23 00 02 B2 D1 454*4882a593Smuzhiyun 29 00 04 FF 98 81 01 455*4882a593Smuzhiyun 23 00 02 22 0A 456*4882a593Smuzhiyun 23 00 02 31 00 457*4882a593Smuzhiyun 23 00 02 43 66 458*4882a593Smuzhiyun 23 00 02 53 40 459*4882a593Smuzhiyun 23 00 02 50 87 460*4882a593Smuzhiyun 23 00 02 51 82 461*4882a593Smuzhiyun 23 00 02 60 15 462*4882a593Smuzhiyun 23 00 02 61 01 463*4882a593Smuzhiyun 23 00 02 62 0C 464*4882a593Smuzhiyun 23 00 02 63 00 465*4882a593Smuzhiyun 29 00 04 FF 98 81 00 466*4882a593Smuzhiyun 23 00 02 35 00 467*4882a593Smuzhiyun 468*4882a593Smuzhiyun 05 78 01 11 469*4882a593Smuzhiyun 05 dc 01 29 470*4882a593Smuzhiyun //05 00 01 35 471*4882a593Smuzhiyun ]; 472*4882a593Smuzhiyun 473*4882a593Smuzhiyun panel-exit-sequence = [ 474*4882a593Smuzhiyun 05 dc 01 28 475*4882a593Smuzhiyun 05 78 01 10 476*4882a593Smuzhiyun ]; 477*4882a593Smuzhiyun 478*4882a593Smuzhiyun display-timings { 479*4882a593Smuzhiyun native-mode = <&timing0>; 480*4882a593Smuzhiyun 481*4882a593Smuzhiyun timing0: timing0 { 482*4882a593Smuzhiyun clock-frequency = <160000000>; 483*4882a593Smuzhiyun hactive = <1200>; 484*4882a593Smuzhiyun vactive = <1920>; 485*4882a593Smuzhiyun 486*4882a593Smuzhiyun hsync-len = <1>;//19 487*4882a593Smuzhiyun hback-porch = <60>;//40 488*4882a593Smuzhiyun hfront-porch = <80>;//123 489*4882a593Smuzhiyun 490*4882a593Smuzhiyun vsync-len = <1>; 491*4882a593Smuzhiyun vback-porch = <25>; 492*4882a593Smuzhiyun vfront-porch = <35>; 493*4882a593Smuzhiyun 494*4882a593Smuzhiyun hsync-active = <0>; 495*4882a593Smuzhiyun vsync-active = <0>; 496*4882a593Smuzhiyun de-active = <0>; 497*4882a593Smuzhiyun pixelclk-active = <1>; 498*4882a593Smuzhiyun }; 499*4882a593Smuzhiyun }; 500*4882a593Smuzhiyun 501*4882a593Smuzhiyun ports { 502*4882a593Smuzhiyun #address-cells = <1>; 503*4882a593Smuzhiyun #size-cells = <0>; 504*4882a593Smuzhiyun 505*4882a593Smuzhiyun port@0 { 506*4882a593Smuzhiyun reg = <0>; 507*4882a593Smuzhiyun panel_in_dsi: endpoint { 508*4882a593Smuzhiyun remote-endpoint = <&dsi_out_panel>; 509*4882a593Smuzhiyun }; 510*4882a593Smuzhiyun }; 511*4882a593Smuzhiyun }; 512*4882a593Smuzhiyun }; 513*4882a593Smuzhiyun 514*4882a593Smuzhiyun ports { 515*4882a593Smuzhiyun #address-cells = <1>; 516*4882a593Smuzhiyun #size-cells = <0>; 517*4882a593Smuzhiyun 518*4882a593Smuzhiyun port@1 { 519*4882a593Smuzhiyun reg = <1>; 520*4882a593Smuzhiyun dsi_out_panel: endpoint { 521*4882a593Smuzhiyun remote-endpoint = <&panel_in_dsi>; 522*4882a593Smuzhiyun }; 523*4882a593Smuzhiyun }; 524*4882a593Smuzhiyun }; 525*4882a593Smuzhiyun 526*4882a593Smuzhiyun}; 527*4882a593Smuzhiyun 528*4882a593Smuzhiyun&dsi0_in_vp0 { 529*4882a593Smuzhiyun status = "okay"; 530*4882a593Smuzhiyun}; 531*4882a593Smuzhiyun 532*4882a593Smuzhiyun&dsi0_in_vp1 { 533*4882a593Smuzhiyun status = "disabled"; 534*4882a593Smuzhiyun}; 535*4882a593Smuzhiyun 536*4882a593Smuzhiyun&gpu { 537*4882a593Smuzhiyun mali-supply = <&vdd_gpu>; 538*4882a593Smuzhiyun status = "okay"; 539*4882a593Smuzhiyun}; 540*4882a593Smuzhiyun 541*4882a593Smuzhiyun&hdmi { 542*4882a593Smuzhiyun status = "okay"; 543*4882a593Smuzhiyun}; 544*4882a593Smuzhiyun 545*4882a593Smuzhiyun&hdmi_in_vp0 { 546*4882a593Smuzhiyun status = "okay"; 547*4882a593Smuzhiyun}; 548*4882a593Smuzhiyun 549*4882a593Smuzhiyun&hdmi_in_vp1 { 550*4882a593Smuzhiyun status = "disabled"; 551*4882a593Smuzhiyun}; 552*4882a593Smuzhiyun 553*4882a593Smuzhiyun&hdmi_sound { 554*4882a593Smuzhiyun status = "okay"; 555*4882a593Smuzhiyun}; 556*4882a593Smuzhiyun 557*4882a593Smuzhiyun&i2c0 { 558*4882a593Smuzhiyun status = "okay"; 559*4882a593Smuzhiyun 560*4882a593Smuzhiyun vdd_cpu: tcs4525@1c { 561*4882a593Smuzhiyun compatible = "tcs,tcs4525"; 562*4882a593Smuzhiyun reg = <0x1c>; 563*4882a593Smuzhiyun vin-supply = <&vccsys>; 564*4882a593Smuzhiyun regulator-compatible = "fan53555-reg"; 565*4882a593Smuzhiyun regulator-name = "vdd_cpu"; 566*4882a593Smuzhiyun regulator-min-microvolt = <712500>; 567*4882a593Smuzhiyun regulator-max-microvolt = <1390000>; 568*4882a593Smuzhiyun regulator-init-microvolt = <900000>; 569*4882a593Smuzhiyun regulator-ramp-delay = <2300>; 570*4882a593Smuzhiyun fcs,suspend-voltage-selector = <1>; 571*4882a593Smuzhiyun regulator-boot-on; 572*4882a593Smuzhiyun regulator-always-on; 573*4882a593Smuzhiyun regulator-state-mem { 574*4882a593Smuzhiyun regulator-off-in-suspend; 575*4882a593Smuzhiyun }; 576*4882a593Smuzhiyun }; 577*4882a593Smuzhiyun 578*4882a593Smuzhiyun rk817: pmic@20 { 579*4882a593Smuzhiyun compatible = "rockchip,rk817"; 580*4882a593Smuzhiyun reg = <0x20>; 581*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 582*4882a593Smuzhiyun interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 583*4882a593Smuzhiyun 584*4882a593Smuzhiyun pinctrl-names = "default", "pmic-sleep", 585*4882a593Smuzhiyun "pmic-power-off", "pmic-reset"; 586*4882a593Smuzhiyun pinctrl-0 = <&pmic_int>; 587*4882a593Smuzhiyun pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; 588*4882a593Smuzhiyun pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; 589*4882a593Smuzhiyun pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; 590*4882a593Smuzhiyun rockchip,system-power-controller; 591*4882a593Smuzhiyun wakeup-source; 592*4882a593Smuzhiyun #clock-cells = <1>; 593*4882a593Smuzhiyun clock-output-names = "rk808-clkout1", "rk808-clkout2"; 594*4882a593Smuzhiyun //fb-inner-reg-idxs = <2>; 595*4882a593Smuzhiyun /* 1: rst regs (default in codes), 0: rst the pmic */ 596*4882a593Smuzhiyun pmic-reset-func = <0>; 597*4882a593Smuzhiyun 598*4882a593Smuzhiyun vcc1-supply = <&vccsys>; 599*4882a593Smuzhiyun vcc2-supply = <&vccsys>; 600*4882a593Smuzhiyun vcc3-supply = <&vccsys>; 601*4882a593Smuzhiyun vcc4-supply = <&vccsys>; 602*4882a593Smuzhiyun vcc5-supply = <&vccsys>; 603*4882a593Smuzhiyun vcc6-supply = <&vccsys>; 604*4882a593Smuzhiyun vcc7-supply = <&vccsys>; 605*4882a593Smuzhiyun vcc8-supply = <&vccsys>; 606*4882a593Smuzhiyun vcc9-supply = <&dcdc_boost>; 607*4882a593Smuzhiyun 608*4882a593Smuzhiyun pwrkey { 609*4882a593Smuzhiyun status = "okay"; 610*4882a593Smuzhiyun }; 611*4882a593Smuzhiyun 612*4882a593Smuzhiyun pinctrl_rk8xx: pinctrl_rk8xx { 613*4882a593Smuzhiyun gpio-controller; 614*4882a593Smuzhiyun #gpio-cells = <2>; 615*4882a593Smuzhiyun 616*4882a593Smuzhiyun rk817_slppin_null: rk817_slppin_null { 617*4882a593Smuzhiyun pins = "gpio_slp"; 618*4882a593Smuzhiyun function = "pin_fun0"; 619*4882a593Smuzhiyun }; 620*4882a593Smuzhiyun 621*4882a593Smuzhiyun rk817_slppin_slp: rk817_slppin_slp { 622*4882a593Smuzhiyun pins = "gpio_slp"; 623*4882a593Smuzhiyun function = "pin_fun1"; 624*4882a593Smuzhiyun }; 625*4882a593Smuzhiyun 626*4882a593Smuzhiyun rk817_slppin_pwrdn: rk817_slppin_pwrdn { 627*4882a593Smuzhiyun pins = "gpio_slp"; 628*4882a593Smuzhiyun function = "pin_fun2"; 629*4882a593Smuzhiyun }; 630*4882a593Smuzhiyun 631*4882a593Smuzhiyun rk817_slppin_rst: rk817_slppin_rst { 632*4882a593Smuzhiyun pins = "gpio_slp"; 633*4882a593Smuzhiyun function = "pin_fun3"; 634*4882a593Smuzhiyun }; 635*4882a593Smuzhiyun }; 636*4882a593Smuzhiyun 637*4882a593Smuzhiyun regulators { 638*4882a593Smuzhiyun vdd_logic: DCDC_REG1 { 639*4882a593Smuzhiyun regulator-always-on; 640*4882a593Smuzhiyun regulator-boot-on; 641*4882a593Smuzhiyun regulator-min-microvolt = <500000>; 642*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 643*4882a593Smuzhiyun regulator-init-microvolt = <900000>; 644*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 645*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 646*4882a593Smuzhiyun regulator-name = "vdd_logic"; 647*4882a593Smuzhiyun regulator-state-mem { 648*4882a593Smuzhiyun regulator-off-in-suspend; 649*4882a593Smuzhiyun regulator-suspend-microvolt = <900000>; 650*4882a593Smuzhiyun }; 651*4882a593Smuzhiyun }; 652*4882a593Smuzhiyun 653*4882a593Smuzhiyun vdd_gpu: DCDC_REG2 { 654*4882a593Smuzhiyun regulator-always-on; 655*4882a593Smuzhiyun regulator-boot-on; 656*4882a593Smuzhiyun regulator-min-microvolt = <500000>; 657*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 658*4882a593Smuzhiyun regulator-init-microvolt = <900000>; 659*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 660*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 661*4882a593Smuzhiyun regulator-name = "vdd_gpu"; 662*4882a593Smuzhiyun regulator-state-mem { 663*4882a593Smuzhiyun regulator-off-in-suspend; 664*4882a593Smuzhiyun }; 665*4882a593Smuzhiyun }; 666*4882a593Smuzhiyun 667*4882a593Smuzhiyun vcc_ddr: DCDC_REG3 { 668*4882a593Smuzhiyun regulator-always-on; 669*4882a593Smuzhiyun regulator-boot-on; 670*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 671*4882a593Smuzhiyun regulator-name = "vcc_ddr"; 672*4882a593Smuzhiyun regulator-state-mem { 673*4882a593Smuzhiyun regulator-on-in-suspend; 674*4882a593Smuzhiyun }; 675*4882a593Smuzhiyun }; 676*4882a593Smuzhiyun 677*4882a593Smuzhiyun vcc_3v3: DCDC_REG4 { 678*4882a593Smuzhiyun regulator-always-on; 679*4882a593Smuzhiyun regulator-boot-on; 680*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 681*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 682*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 683*4882a593Smuzhiyun regulator-name = "vcc_3v3"; 684*4882a593Smuzhiyun regulator-state-mem { 685*4882a593Smuzhiyun regulator-off-in-suspend; 686*4882a593Smuzhiyun }; 687*4882a593Smuzhiyun }; 688*4882a593Smuzhiyun 689*4882a593Smuzhiyun vcca1v8_pmu: LDO_REG1 { 690*4882a593Smuzhiyun regulator-always-on; 691*4882a593Smuzhiyun regulator-boot-on; 692*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 693*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 694*4882a593Smuzhiyun regulator-name = "vcca1v8_pmu"; 695*4882a593Smuzhiyun regulator-state-mem { 696*4882a593Smuzhiyun regulator-on-in-suspend; 697*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 698*4882a593Smuzhiyun }; 699*4882a593Smuzhiyun }; 700*4882a593Smuzhiyun 701*4882a593Smuzhiyun vdda_0v9: LDO_REG2 { 702*4882a593Smuzhiyun regulator-always-on; 703*4882a593Smuzhiyun regulator-boot-on; 704*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 705*4882a593Smuzhiyun regulator-max-microvolt = <900000>; 706*4882a593Smuzhiyun regulator-name = "vdda_0v9"; 707*4882a593Smuzhiyun regulator-state-mem { 708*4882a593Smuzhiyun regulator-off-in-suspend; 709*4882a593Smuzhiyun }; 710*4882a593Smuzhiyun }; 711*4882a593Smuzhiyun 712*4882a593Smuzhiyun vdda0v9_pmu: LDO_REG3 { 713*4882a593Smuzhiyun regulator-always-on; 714*4882a593Smuzhiyun regulator-boot-on; 715*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 716*4882a593Smuzhiyun regulator-max-microvolt = <900000>; 717*4882a593Smuzhiyun regulator-name = "vdda0v9_pmu"; 718*4882a593Smuzhiyun regulator-state-mem { 719*4882a593Smuzhiyun regulator-on-in-suspend; 720*4882a593Smuzhiyun regulator-suspend-microvolt = <900000>; 721*4882a593Smuzhiyun }; 722*4882a593Smuzhiyun }; 723*4882a593Smuzhiyun 724*4882a593Smuzhiyun vccio_acodec: LDO_REG4 { 725*4882a593Smuzhiyun regulator-always-on; 726*4882a593Smuzhiyun regulator-boot-on; 727*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 728*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 729*4882a593Smuzhiyun regulator-name = "vccio_acodec"; 730*4882a593Smuzhiyun regulator-state-mem { 731*4882a593Smuzhiyun regulator-off-in-suspend; 732*4882a593Smuzhiyun }; 733*4882a593Smuzhiyun }; 734*4882a593Smuzhiyun 735*4882a593Smuzhiyun vccio_sd: LDO_REG5 { 736*4882a593Smuzhiyun regulator-always-on; 737*4882a593Smuzhiyun regulator-boot-on; 738*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 739*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 740*4882a593Smuzhiyun regulator-name = "vccio_sd"; 741*4882a593Smuzhiyun regulator-state-mem { 742*4882a593Smuzhiyun regulator-off-in-suspend; 743*4882a593Smuzhiyun }; 744*4882a593Smuzhiyun }; 745*4882a593Smuzhiyun 746*4882a593Smuzhiyun vcc3v3_pmu: LDO_REG6 { 747*4882a593Smuzhiyun regulator-always-on; 748*4882a593Smuzhiyun regulator-boot-on; 749*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 750*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 751*4882a593Smuzhiyun regulator-name = "vcc3v3_pmu"; 752*4882a593Smuzhiyun regulator-state-mem { 753*4882a593Smuzhiyun regulator-on-in-suspend; 754*4882a593Smuzhiyun regulator-suspend-microvolt = <3000000>; 755*4882a593Smuzhiyun }; 756*4882a593Smuzhiyun }; 757*4882a593Smuzhiyun 758*4882a593Smuzhiyun vcc_1v8: LDO_REG7 { 759*4882a593Smuzhiyun regulator-always-on; 760*4882a593Smuzhiyun regulator-boot-on; 761*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 762*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 763*4882a593Smuzhiyun regulator-name = "vcc_1v8"; 764*4882a593Smuzhiyun regulator-state-mem { 765*4882a593Smuzhiyun regulator-off-in-suspend; 766*4882a593Smuzhiyun }; 767*4882a593Smuzhiyun }; 768*4882a593Smuzhiyun 769*4882a593Smuzhiyun vcc1v8_dvp: LDO_REG8 { 770*4882a593Smuzhiyun regulator-always-on; 771*4882a593Smuzhiyun regulator-boot-on; 772*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 773*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 774*4882a593Smuzhiyun regulator-name = "vcc1v8_dvp"; 775*4882a593Smuzhiyun regulator-state-mem { 776*4882a593Smuzhiyun regulator-off-in-suspend; 777*4882a593Smuzhiyun }; 778*4882a593Smuzhiyun }; 779*4882a593Smuzhiyun 780*4882a593Smuzhiyun vcc2v8_dvp: LDO_REG9 { 781*4882a593Smuzhiyun regulator-always-on; 782*4882a593Smuzhiyun regulator-boot-on; 783*4882a593Smuzhiyun regulator-min-microvolt = <2800000>; 784*4882a593Smuzhiyun regulator-max-microvolt = <2800000>; 785*4882a593Smuzhiyun regulator-name = "vcc2v8_dvp"; 786*4882a593Smuzhiyun regulator-state-mem { 787*4882a593Smuzhiyun regulator-off-in-suspend; 788*4882a593Smuzhiyun }; 789*4882a593Smuzhiyun }; 790*4882a593Smuzhiyun 791*4882a593Smuzhiyun dcdc_boost: BOOST { 792*4882a593Smuzhiyun regulator-always-on; 793*4882a593Smuzhiyun regulator-boot-on; 794*4882a593Smuzhiyun regulator-min-microvolt = <4700000>; 795*4882a593Smuzhiyun regulator-max-microvolt = <5400000>; 796*4882a593Smuzhiyun regulator-name = "boost"; 797*4882a593Smuzhiyun regulator-state-mem { 798*4882a593Smuzhiyun regulator-off-in-suspend; 799*4882a593Smuzhiyun }; 800*4882a593Smuzhiyun }; 801*4882a593Smuzhiyun 802*4882a593Smuzhiyun otg_switch: OTG_SWITCH { 803*4882a593Smuzhiyun regulator-name = "otg_switch"; 804*4882a593Smuzhiyun regulator-state-mem { 805*4882a593Smuzhiyun regulator-off-in-suspend; 806*4882a593Smuzhiyun }; 807*4882a593Smuzhiyun }; 808*4882a593Smuzhiyun }; 809*4882a593Smuzhiyun 810*4882a593Smuzhiyun battery { 811*4882a593Smuzhiyun compatible = "rk817,battery"; 812*4882a593Smuzhiyun ocv_table = <3400 3513 3578 3687 3734 3752 3763 813*4882a593Smuzhiyun 3766 3771 3784 3804 3836 3885 3925 814*4882a593Smuzhiyun 3962 4005 4063 4114 4169 4227 4303>; 815*4882a593Smuzhiyun design_capacity = <5000>; 816*4882a593Smuzhiyun design_qmax = <5500>; 817*4882a593Smuzhiyun bat_res = <100>; 818*4882a593Smuzhiyun sleep_enter_current = <150>; 819*4882a593Smuzhiyun sleep_exit_current = <180>; 820*4882a593Smuzhiyun sleep_filter_current = <100>; 821*4882a593Smuzhiyun power_off_thresd = <3450>; 822*4882a593Smuzhiyun zero_algorithm_vol = <3850>; 823*4882a593Smuzhiyun max_soc_offset = <60>; 824*4882a593Smuzhiyun monitor_sec = <5>; 825*4882a593Smuzhiyun sample_res = <10>; 826*4882a593Smuzhiyun virtual_power = <0>; 827*4882a593Smuzhiyun }; 828*4882a593Smuzhiyun 829*4882a593Smuzhiyun charger { 830*4882a593Smuzhiyun compatible = "rk817,charger"; 831*4882a593Smuzhiyun min_input_voltage = <4500>; 832*4882a593Smuzhiyun max_input_current = <1500>; 833*4882a593Smuzhiyun max_chrg_current = <2000>; 834*4882a593Smuzhiyun max_chrg_voltage = <4300>; 835*4882a593Smuzhiyun chrg_term_mode = <0>; 836*4882a593Smuzhiyun chrg_finish_cur = <300>; 837*4882a593Smuzhiyun virtual_power = <0>; 838*4882a593Smuzhiyun dc_det_adc = <0>; 839*4882a593Smuzhiyun extcon = <&usb2phy0>; 840*4882a593Smuzhiyun }; 841*4882a593Smuzhiyun 842*4882a593Smuzhiyun rk817_codec: codec { 843*4882a593Smuzhiyun #sound-dai-cells = <0>; 844*4882a593Smuzhiyun compatible = "rockchip,rk817-codec"; 845*4882a593Smuzhiyun clocks = <&cru I2S1_MCLKOUT>; 846*4882a593Smuzhiyun clock-names = "mclk"; 847*4882a593Smuzhiyun assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; 848*4882a593Smuzhiyun assigned-clock-rates = <12288000>; 849*4882a593Smuzhiyun assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; 850*4882a593Smuzhiyun pinctrl-names = "default"; 851*4882a593Smuzhiyun pinctrl-0 = <&i2s1m0_mclk>; 852*4882a593Smuzhiyun hp-volume = <20>; 853*4882a593Smuzhiyun spk-volume = <3>; 854*4882a593Smuzhiyun out-l2spk-r2hp; 855*4882a593Smuzhiyun spk-ctl-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; 856*4882a593Smuzhiyun status = "okay"; 857*4882a593Smuzhiyun }; 858*4882a593Smuzhiyun }; 859*4882a593Smuzhiyun}; 860*4882a593Smuzhiyun 861*4882a593Smuzhiyun&i2c2 { 862*4882a593Smuzhiyun status = "okay"; 863*4882a593Smuzhiyun pinctrl-0 = <&i2c2m1_xfer>; 864*4882a593Smuzhiyun 865*4882a593Smuzhiyun dw9714: dw9714@c { 866*4882a593Smuzhiyun compatible = "dongwoon,dw9714"; 867*4882a593Smuzhiyun status = "okay"; 868*4882a593Smuzhiyun reg = <0x0c>; 869*4882a593Smuzhiyun rockchip,camera-module-index = <0>; 870*4882a593Smuzhiyun rockchip,vcm-start-current = <10>; 871*4882a593Smuzhiyun rockchip,vcm-rated-current = <85>; 872*4882a593Smuzhiyun rockchip,vcm-step-mode = <5>; 873*4882a593Smuzhiyun rockchip,camera-module-facing = "back"; 874*4882a593Smuzhiyun }; 875*4882a593Smuzhiyun 876*4882a593Smuzhiyun gc2385: gc2385@37 { 877*4882a593Smuzhiyun compatible = "galaxycore,gc2385"; 878*4882a593Smuzhiyun status = "okay"; 879*4882a593Smuzhiyun reg = <0x37>; 880*4882a593Smuzhiyun clocks = <&cru CLK_CIF_OUT>; 881*4882a593Smuzhiyun clock-names = "xvclk"; 882*4882a593Smuzhiyun power-domains = <&power RK3568_PD_VI>; 883*4882a593Smuzhiyun pinctrl-names = "rockchip,camera_default"; 884*4882a593Smuzhiyun pinctrl-0 = <&cif_clk>; 885*4882a593Smuzhiyun 886*4882a593Smuzhiyun //reset pin control by hardware,used this pin switch to mipi input 887*4882a593Smuzhiyun //1->2LANE(LANE 0&1) FRONT camera, 0->4LANE REAR camera 888*4882a593Smuzhiyun reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; 889*4882a593Smuzhiyun pwdn-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; 890*4882a593Smuzhiyun rockchip,camera-module-index = <1>; 891*4882a593Smuzhiyun rockchip,camera-module-facing = "front"; 892*4882a593Smuzhiyun rockchip,camera-module-name = "HS5885-BNSM1018-V01"; 893*4882a593Smuzhiyun rockchip,camera-module-lens-name = "default"; 894*4882a593Smuzhiyun port { 895*4882a593Smuzhiyun gc2385_out: endpoint { 896*4882a593Smuzhiyun remote-endpoint = <&mipi_in_ucam0>; 897*4882a593Smuzhiyun data-lanes = <1>; 898*4882a593Smuzhiyun }; 899*4882a593Smuzhiyun }; 900*4882a593Smuzhiyun }; 901*4882a593Smuzhiyun 902*4882a593Smuzhiyun ov8858: ov8858@36 { 903*4882a593Smuzhiyun status = "okay"; 904*4882a593Smuzhiyun compatible = "ovti,ov8858"; 905*4882a593Smuzhiyun reg = <0x36>; 906*4882a593Smuzhiyun clocks = <&cru CLK_CAM0_OUT>; 907*4882a593Smuzhiyun clock-names = "xvclk"; 908*4882a593Smuzhiyun power-domains = <&power RK3568_PD_VI>; 909*4882a593Smuzhiyun pinctrl-names = "rockchip,camera_default", "rockchip,camera_sleep"; 910*4882a593Smuzhiyun pinctrl-0 = <&cam_clkout0>; 911*4882a593Smuzhiyun pinctrl-1 = <&cam_sleep>; 912*4882a593Smuzhiyun //reset pin control by hardware,used this pin switch to mipi input 913*4882a593Smuzhiyun //1->2LANE(LANE 0&1) FRONT camera, 0->4LANE REAR camera 914*4882a593Smuzhiyun reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; 915*4882a593Smuzhiyun pwdn-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; 916*4882a593Smuzhiyun rockchip,camera-module-index = <0>; 917*4882a593Smuzhiyun rockchip,camera-module-facing = "back"; 918*4882a593Smuzhiyun rockchip,camera-module-name = "HS5885-BNSM1018-V01"; 919*4882a593Smuzhiyun rockchip,camera-module-lens-name = "default"; 920*4882a593Smuzhiyun flash-leds = <&flash_rgb13h>; 921*4882a593Smuzhiyun lens-focus = <&dw9714>; 922*4882a593Smuzhiyun port { 923*4882a593Smuzhiyun ov8858_out: endpoint { 924*4882a593Smuzhiyun remote-endpoint = <&mipi_in_ucam1>; 925*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 926*4882a593Smuzhiyun }; 927*4882a593Smuzhiyun }; 928*4882a593Smuzhiyun }; 929*4882a593Smuzhiyun}; 930*4882a593Smuzhiyun 931*4882a593Smuzhiyun&i2c3 { 932*4882a593Smuzhiyun status = "okay"; 933*4882a593Smuzhiyun pinctrl-names = "default"; 934*4882a593Smuzhiyun pinctrl-0 = <&i2c3m1_xfer>; 935*4882a593Smuzhiyun clock-frequency = <400000>; 936*4882a593Smuzhiyun i2c-scl-rising-time-ns = <138>; 937*4882a593Smuzhiyun i2c-scl-falling-time-ns = <4>; 938*4882a593Smuzhiyun 939*4882a593Smuzhiyun gt9xx: gt9xx@14 { 940*4882a593Smuzhiyun compatible = "goodix,gt9xx"; 941*4882a593Smuzhiyun reg = <0x14>; 942*4882a593Smuzhiyun pinctrl-names = "default"; 943*4882a593Smuzhiyun pinctrl-0 = <>9xx_gpio>; 944*4882a593Smuzhiyun touch-gpio = <&gpio3 RK_PB0 IRQ_TYPE_LEVEL_HIGH>; 945*4882a593Smuzhiyun reset-gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; 946*4882a593Smuzhiyun max-x = <1200>; 947*4882a593Smuzhiyun max-y = <1920>; 948*4882a593Smuzhiyun tp-size = <9110>; 949*4882a593Smuzhiyun tp-supply = <&vcc_3v3>; 950*4882a593Smuzhiyun }; 951*4882a593Smuzhiyun}; 952*4882a593Smuzhiyun 953*4882a593Smuzhiyun&i2c5 { 954*4882a593Smuzhiyun status = "okay"; 955*4882a593Smuzhiyun clock-frequency = <400000>; 956*4882a593Smuzhiyun i2c-scl-rising-time-ns = <144>; 957*4882a593Smuzhiyun i2c-scl-falling-time-ns = <4>; 958*4882a593Smuzhiyun 959*4882a593Smuzhiyun sensor@4c { 960*4882a593Smuzhiyun compatible = "gs_mc3230"; 961*4882a593Smuzhiyun reg = <0x4c>; 962*4882a593Smuzhiyun type = <SENSOR_TYPE_ACCEL>; 963*4882a593Smuzhiyun irq_enable = <0>; 964*4882a593Smuzhiyun poll_delay_ms = <30>; 965*4882a593Smuzhiyun layout = <9>; 966*4882a593Smuzhiyun reprobe_en = <1>; 967*4882a593Smuzhiyun pinctrl-names = "default"; 968*4882a593Smuzhiyun pinctrl-0 = <&sensor_gpio>; 969*4882a593Smuzhiyun irq-gpio = <&gpio3 RK_PA2 IRQ_TYPE_LEVEL_LOW>; 970*4882a593Smuzhiyun }; 971*4882a593Smuzhiyun}; 972*4882a593Smuzhiyun 973*4882a593Smuzhiyun&i2s0_8ch { 974*4882a593Smuzhiyun status = "okay"; 975*4882a593Smuzhiyun}; 976*4882a593Smuzhiyun 977*4882a593Smuzhiyun&i2s1_8ch { 978*4882a593Smuzhiyun status = "okay"; 979*4882a593Smuzhiyun rockchip,clk-trcm = <1>; 980*4882a593Smuzhiyun pinctrl-names = "default"; 981*4882a593Smuzhiyun pinctrl-0 = <&i2s1m0_sclktx 982*4882a593Smuzhiyun &i2s1m0_lrcktx 983*4882a593Smuzhiyun &i2s1m0_sdi0 984*4882a593Smuzhiyun &i2s1m0_sdo0>; 985*4882a593Smuzhiyun}; 986*4882a593Smuzhiyun 987*4882a593Smuzhiyun&jpegd { 988*4882a593Smuzhiyun status = "okay"; 989*4882a593Smuzhiyun}; 990*4882a593Smuzhiyun 991*4882a593Smuzhiyun&jpegd_mmu { 992*4882a593Smuzhiyun status = "okay"; 993*4882a593Smuzhiyun}; 994*4882a593Smuzhiyun 995*4882a593Smuzhiyun&video_phy0 { 996*4882a593Smuzhiyun status = "okay"; 997*4882a593Smuzhiyun}; 998*4882a593Smuzhiyun 999*4882a593Smuzhiyun&mpp_srv { 1000*4882a593Smuzhiyun status = "okay"; 1001*4882a593Smuzhiyun}; 1002*4882a593Smuzhiyun 1003*4882a593Smuzhiyun&nandc0 { 1004*4882a593Smuzhiyun status = "okay"; 1005*4882a593Smuzhiyun}; 1006*4882a593Smuzhiyun 1007*4882a593Smuzhiyun&pinctrl { 1008*4882a593Smuzhiyun cam { 1009*4882a593Smuzhiyun cam_clkout0: cam-clkout0 { 1010*4882a593Smuzhiyun rockchip,pins = 1011*4882a593Smuzhiyun /* cam_clkout0 */ 1012*4882a593Smuzhiyun <4 RK_PA7 1 &pcfg_pull_none>; 1013*4882a593Smuzhiyun }; 1014*4882a593Smuzhiyun 1015*4882a593Smuzhiyun cam_sleep: cam-sleep { 1016*4882a593Smuzhiyun rockchip,pins = 1017*4882a593Smuzhiyun /* cam_sleep */ 1018*4882a593Smuzhiyun <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; 1019*4882a593Smuzhiyun }; 1020*4882a593Smuzhiyun 1021*4882a593Smuzhiyun camera_rst: camera-rst { 1022*4882a593Smuzhiyun rockchip,pins = 1023*4882a593Smuzhiyun /* front camera reset */ 1024*4882a593Smuzhiyun <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>, 1025*4882a593Smuzhiyun /* back camra reset */ 1026*4882a593Smuzhiyun <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; 1027*4882a593Smuzhiyun }; 1028*4882a593Smuzhiyun 1029*4882a593Smuzhiyun flash_led_gpios: flash-led { 1030*4882a593Smuzhiyun rockchip,pins = 1031*4882a593Smuzhiyun /* flash led enable */ 1032*4882a593Smuzhiyun <4 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; 1033*4882a593Smuzhiyun }; 1034*4882a593Smuzhiyun }; 1035*4882a593Smuzhiyun 1036*4882a593Smuzhiyun gt9xx { 1037*4882a593Smuzhiyun gt9xx_gpio: gt9xx-gpio { 1038*4882a593Smuzhiyun rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>, 1039*4882a593Smuzhiyun <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; 1040*4882a593Smuzhiyun }; 1041*4882a593Smuzhiyun }; 1042*4882a593Smuzhiyun 1043*4882a593Smuzhiyun headphone { 1044*4882a593Smuzhiyun hp_det: hp-det { 1045*4882a593Smuzhiyun rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; 1046*4882a593Smuzhiyun }; 1047*4882a593Smuzhiyun }; 1048*4882a593Smuzhiyun 1049*4882a593Smuzhiyun lcd { 1050*4882a593Smuzhiyun lcd_rst_gpio: lcd-rst-gpio { 1051*4882a593Smuzhiyun rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; 1052*4882a593Smuzhiyun }; 1053*4882a593Smuzhiyun 1054*4882a593Smuzhiyun lcd_enable_gpio: lcd-enable-gpio { 1055*4882a593Smuzhiyun rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; 1056*4882a593Smuzhiyun }; 1057*4882a593Smuzhiyun 1058*4882a593Smuzhiyun lcd_stanby_gpio: lcd-stanby-gpio { 1059*4882a593Smuzhiyun rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; 1060*4882a593Smuzhiyun }; 1061*4882a593Smuzhiyun }; 1062*4882a593Smuzhiyun 1063*4882a593Smuzhiyun pmic { 1064*4882a593Smuzhiyun pmic_int: pmic_int { 1065*4882a593Smuzhiyun rockchip,pins = 1066*4882a593Smuzhiyun <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; 1067*4882a593Smuzhiyun }; 1068*4882a593Smuzhiyun 1069*4882a593Smuzhiyun soc_slppin_gpio: soc_slppin_gpio { 1070*4882a593Smuzhiyun rockchip,pins = 1071*4882a593Smuzhiyun <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>; 1072*4882a593Smuzhiyun }; 1073*4882a593Smuzhiyun 1074*4882a593Smuzhiyun soc_slppin_slp: soc_slppin_slp { 1075*4882a593Smuzhiyun rockchip,pins = 1076*4882a593Smuzhiyun <0 RK_PA2 1 &pcfg_pull_none>; 1077*4882a593Smuzhiyun }; 1078*4882a593Smuzhiyun 1079*4882a593Smuzhiyun soc_slppin_rst: soc_slppin_rst { 1080*4882a593Smuzhiyun rockchip,pins = 1081*4882a593Smuzhiyun <0 RK_PA2 2 &pcfg_pull_none>; 1082*4882a593Smuzhiyun }; 1083*4882a593Smuzhiyun }; 1084*4882a593Smuzhiyun 1085*4882a593Smuzhiyun sensor { 1086*4882a593Smuzhiyun sensor_gpio: sensor-gpio { 1087*4882a593Smuzhiyun rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; 1088*4882a593Smuzhiyun }; 1089*4882a593Smuzhiyun }; 1090*4882a593Smuzhiyun 1091*4882a593Smuzhiyun sdio-pwrseq { 1092*4882a593Smuzhiyun wifi_enable_h: wifi-enable-h { 1093*4882a593Smuzhiyun rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; 1094*4882a593Smuzhiyun }; 1095*4882a593Smuzhiyun }; 1096*4882a593Smuzhiyun 1097*4882a593Smuzhiyun vcc_sd { 1098*4882a593Smuzhiyun vcc_sd_h: vcc-sd-h { 1099*4882a593Smuzhiyun rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 1100*4882a593Smuzhiyun }; 1101*4882a593Smuzhiyun }; 1102*4882a593Smuzhiyun 1103*4882a593Smuzhiyun sdmmc0 { 1104*4882a593Smuzhiyun sdmmc0_det_gpio: sdmmc0-det-gpio { 1105*4882a593Smuzhiyun rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; 1106*4882a593Smuzhiyun }; 1107*4882a593Smuzhiyun }; 1108*4882a593Smuzhiyun 1109*4882a593Smuzhiyun usb { 1110*4882a593Smuzhiyun vcc5v0_host_en: vcc5v0-host-en { 1111*4882a593Smuzhiyun rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 1112*4882a593Smuzhiyun }; 1113*4882a593Smuzhiyun }; 1114*4882a593Smuzhiyun 1115*4882a593Smuzhiyun wireless-wlan { 1116*4882a593Smuzhiyun wifi_host_wake_irq: wifi-host-wake-irq { 1117*4882a593Smuzhiyun rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; 1118*4882a593Smuzhiyun }; 1119*4882a593Smuzhiyun }; 1120*4882a593Smuzhiyun 1121*4882a593Smuzhiyun wireless-bluetooth { 1122*4882a593Smuzhiyun uart1_gpios: uart1-gpios { 1123*4882a593Smuzhiyun rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1124*4882a593Smuzhiyun }; 1125*4882a593Smuzhiyun }; 1126*4882a593Smuzhiyun}; 1127*4882a593Smuzhiyun 1128*4882a593Smuzhiyun&pmu_io_domains { 1129*4882a593Smuzhiyun status = "okay"; 1130*4882a593Smuzhiyun pmuio1-supply = <&vcc3v3_pmu>; 1131*4882a593Smuzhiyun pmuio2-supply = <&vcc3v3_pmu>; 1132*4882a593Smuzhiyun vccio1-supply = <&vccio_acodec>; 1133*4882a593Smuzhiyun vccio3-supply = <&vccio_sd>; 1134*4882a593Smuzhiyun vccio4-supply = <&vcc3v3_pmu>; 1135*4882a593Smuzhiyun vccio5-supply = <&vcc_1v8>; 1136*4882a593Smuzhiyun vccio6-supply = <&vcc1v8_dvp>; 1137*4882a593Smuzhiyun vccio7-supply = <&vcc_3v3>; 1138*4882a593Smuzhiyun}; 1139*4882a593Smuzhiyun 1140*4882a593Smuzhiyun&pwm4 { 1141*4882a593Smuzhiyun status = "okay"; 1142*4882a593Smuzhiyun}; 1143*4882a593Smuzhiyun 1144*4882a593Smuzhiyun&rk_rga { 1145*4882a593Smuzhiyun status = "okay"; 1146*4882a593Smuzhiyun}; 1147*4882a593Smuzhiyun 1148*4882a593Smuzhiyun&rkisp { 1149*4882a593Smuzhiyun status = "okay"; 1150*4882a593Smuzhiyun}; 1151*4882a593Smuzhiyun 1152*4882a593Smuzhiyun&rkisp_mmu { 1153*4882a593Smuzhiyun status = "okay"; 1154*4882a593Smuzhiyun}; 1155*4882a593Smuzhiyun 1156*4882a593Smuzhiyun&rkisp_vir0 { 1157*4882a593Smuzhiyun status = "okay"; 1158*4882a593Smuzhiyun 1159*4882a593Smuzhiyun port { 1160*4882a593Smuzhiyun #address-cells = <1>; 1161*4882a593Smuzhiyun #size-cells = <0>; 1162*4882a593Smuzhiyun 1163*4882a593Smuzhiyun isp0_in: endpoint@0 { 1164*4882a593Smuzhiyun reg = <0>; 1165*4882a593Smuzhiyun remote-endpoint = <&csidphy0_out>; 1166*4882a593Smuzhiyun }; 1167*4882a593Smuzhiyun }; 1168*4882a593Smuzhiyun}; 1169*4882a593Smuzhiyun 1170*4882a593Smuzhiyun&rkvdec { 1171*4882a593Smuzhiyun status = "okay"; 1172*4882a593Smuzhiyun}; 1173*4882a593Smuzhiyun 1174*4882a593Smuzhiyun&rkvdec_mmu { 1175*4882a593Smuzhiyun status = "okay"; 1176*4882a593Smuzhiyun}; 1177*4882a593Smuzhiyun 1178*4882a593Smuzhiyun&rkvenc { 1179*4882a593Smuzhiyun status = "okay"; 1180*4882a593Smuzhiyun}; 1181*4882a593Smuzhiyun 1182*4882a593Smuzhiyun&rkvenc_mmu { 1183*4882a593Smuzhiyun status = "okay"; 1184*4882a593Smuzhiyun}; 1185*4882a593Smuzhiyun 1186*4882a593Smuzhiyun&route_dsi0 { 1187*4882a593Smuzhiyun status = "okay"; 1188*4882a593Smuzhiyun}; 1189*4882a593Smuzhiyun 1190*4882a593Smuzhiyun&route_hdmi { 1191*4882a593Smuzhiyun status = "okay"; 1192*4882a593Smuzhiyun connect = <&vp0_out_hdmi>; 1193*4882a593Smuzhiyun}; 1194*4882a593Smuzhiyun 1195*4882a593Smuzhiyun&saradc { 1196*4882a593Smuzhiyun status = "okay"; 1197*4882a593Smuzhiyun vref-supply = <&vcc_1v8>; 1198*4882a593Smuzhiyun}; 1199*4882a593Smuzhiyun 1200*4882a593Smuzhiyun&sdhci { 1201*4882a593Smuzhiyun bus-width = <8>; 1202*4882a593Smuzhiyun no-sdio; 1203*4882a593Smuzhiyun no-sd; 1204*4882a593Smuzhiyun non-removable; 1205*4882a593Smuzhiyun max-frequency = <200000000>; 1206*4882a593Smuzhiyun status = "okay"; 1207*4882a593Smuzhiyun}; 1208*4882a593Smuzhiyun 1209*4882a593Smuzhiyun&sdmmc0 { 1210*4882a593Smuzhiyun max-frequency = <150000000>; 1211*4882a593Smuzhiyun no-sdio; 1212*4882a593Smuzhiyun no-mmc; 1213*4882a593Smuzhiyun bus-width = <4>; 1214*4882a593Smuzhiyun cap-mmc-highspeed; 1215*4882a593Smuzhiyun cap-sd-highspeed; 1216*4882a593Smuzhiyun disable-wp; 1217*4882a593Smuzhiyun sd-uhs-sdr104; 1218*4882a593Smuzhiyun vmmc-supply = <&vcc_sd>; 1219*4882a593Smuzhiyun vqmmc-supply = <&vccio_sd>; 1220*4882a593Smuzhiyun cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; 1221*4882a593Smuzhiyun pinctrl-names = "default"; 1222*4882a593Smuzhiyun pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det_gpio>; 1223*4882a593Smuzhiyun status = "okay"; 1224*4882a593Smuzhiyun}; 1225*4882a593Smuzhiyun 1226*4882a593Smuzhiyun&sdmmc1 { 1227*4882a593Smuzhiyun max-frequency = <150000000>; 1228*4882a593Smuzhiyun no-sd; 1229*4882a593Smuzhiyun no-mmc; 1230*4882a593Smuzhiyun bus-width = <4>; 1231*4882a593Smuzhiyun disable-wp; 1232*4882a593Smuzhiyun cap-sd-highspeed; 1233*4882a593Smuzhiyun cap-sdio-irq; 1234*4882a593Smuzhiyun keep-power-in-suspend; 1235*4882a593Smuzhiyun mmc-pwrseq = <&sdio_pwrseq>; 1236*4882a593Smuzhiyun non-removable; 1237*4882a593Smuzhiyun pinctrl-names = "default"; 1238*4882a593Smuzhiyun pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; 1239*4882a593Smuzhiyun sd-uhs-sdr104; 1240*4882a593Smuzhiyun rockchip,default-sample-phase = <90>; 1241*4882a593Smuzhiyun status = "okay"; 1242*4882a593Smuzhiyun}; 1243*4882a593Smuzhiyun 1244*4882a593Smuzhiyun&tsadc { 1245*4882a593Smuzhiyun status = "okay"; 1246*4882a593Smuzhiyun}; 1247*4882a593Smuzhiyun 1248*4882a593Smuzhiyun&uart1 { 1249*4882a593Smuzhiyun status = "okay"; 1250*4882a593Smuzhiyun pinctrl-names = "default"; 1251*4882a593Smuzhiyun pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; 1252*4882a593Smuzhiyun}; 1253*4882a593Smuzhiyun 1254*4882a593Smuzhiyun&u2phy0_host { 1255*4882a593Smuzhiyun phy-supply = <&vcc5v0_host>; 1256*4882a593Smuzhiyun status = "okay"; 1257*4882a593Smuzhiyun}; 1258*4882a593Smuzhiyun 1259*4882a593Smuzhiyun&u2phy0_otg { 1260*4882a593Smuzhiyun status = "okay"; 1261*4882a593Smuzhiyun}; 1262*4882a593Smuzhiyun 1263*4882a593Smuzhiyun&usb2phy0 { 1264*4882a593Smuzhiyun status = "okay"; 1265*4882a593Smuzhiyun}; 1266*4882a593Smuzhiyun 1267*4882a593Smuzhiyun&usbdrd_dwc3 { 1268*4882a593Smuzhiyun status = "okay"; 1269*4882a593Smuzhiyun}; 1270*4882a593Smuzhiyun 1271*4882a593Smuzhiyun&usbdrd30 { 1272*4882a593Smuzhiyun status = "okay"; 1273*4882a593Smuzhiyun}; 1274*4882a593Smuzhiyun 1275*4882a593Smuzhiyun&usbhost30 { 1276*4882a593Smuzhiyun status = "okay"; 1277*4882a593Smuzhiyun}; 1278*4882a593Smuzhiyun 1279*4882a593Smuzhiyun&usbhost_dwc3 { 1280*4882a593Smuzhiyun phys = <&u2phy0_host>; 1281*4882a593Smuzhiyun phy-names = "usb2-phy"; 1282*4882a593Smuzhiyun maximum-speed = "high-speed"; 1283*4882a593Smuzhiyun status = "okay"; 1284*4882a593Smuzhiyun}; 1285*4882a593Smuzhiyun 1286*4882a593Smuzhiyun&vdpu { 1287*4882a593Smuzhiyun status = "okay"; 1288*4882a593Smuzhiyun}; 1289*4882a593Smuzhiyun 1290*4882a593Smuzhiyun&vdpu_mmu { 1291*4882a593Smuzhiyun status = "okay"; 1292*4882a593Smuzhiyun}; 1293*4882a593Smuzhiyun 1294*4882a593Smuzhiyun&vepu { 1295*4882a593Smuzhiyun status = "okay"; 1296*4882a593Smuzhiyun}; 1297*4882a593Smuzhiyun 1298*4882a593Smuzhiyun&vepu_mmu { 1299*4882a593Smuzhiyun status = "okay"; 1300*4882a593Smuzhiyun}; 1301*4882a593Smuzhiyun 1302*4882a593Smuzhiyun&vop { 1303*4882a593Smuzhiyun status = "okay"; 1304*4882a593Smuzhiyun}; 1305*4882a593Smuzhiyun 1306*4882a593Smuzhiyun&vop_mmu { 1307*4882a593Smuzhiyun status = "okay"; 1308*4882a593Smuzhiyun}; 1309