xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm64/rockchip/rk3566-evb3-ddr3-v10.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun/dts-v1/;
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
10*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h>
11*4882a593Smuzhiyun#include "rk3566.dtsi"
12*4882a593Smuzhiyun#include "rk3566-evb.dtsi"
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun/ {
15*4882a593Smuzhiyun	model = "Rockchip RK3566 EVB3 DDR3 V10 Board";
16*4882a593Smuzhiyun	compatible = "rockchip,rk3566-evb3-DDR3-v10", "rockchip,rk3566";
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun	rk_headset: rk-headset {
19*4882a593Smuzhiyun		compatible = "rockchip_headset";
20*4882a593Smuzhiyun		headset_gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
21*4882a593Smuzhiyun		pinctrl-names = "default";
22*4882a593Smuzhiyun		pinctrl-0 = <&hp_det>;
23*4882a593Smuzhiyun	};
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun	vcc3v3_vga: vcc3v3-vga {
26*4882a593Smuzhiyun		compatible = "regulator-fixed";
27*4882a593Smuzhiyun		regulator-name = "vcc3v3_vga";
28*4882a593Smuzhiyun		regulator-always-on;
29*4882a593Smuzhiyun		regulator-boot-on;
30*4882a593Smuzhiyun		gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
31*4882a593Smuzhiyun		enable-active-high;
32*4882a593Smuzhiyun		vin-supply = <&vcc3v3_sys>;
33*4882a593Smuzhiyun	};
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun	vcc_camera: vcc-camera-regulator {
36*4882a593Smuzhiyun		compatible = "regulator-fixed";
37*4882a593Smuzhiyun		gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
38*4882a593Smuzhiyun		pinctrl-names = "default";
39*4882a593Smuzhiyun		pinctrl-0 = <&camera_pwr>;
40*4882a593Smuzhiyun		regulator-name = "vcc_camera";
41*4882a593Smuzhiyun		enable-active-high;
42*4882a593Smuzhiyun		regulator-always-on;
43*4882a593Smuzhiyun		regulator-boot-on;
44*4882a593Smuzhiyun	};
45*4882a593Smuzhiyun};
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun&bt_sound {
48*4882a593Smuzhiyun	status = "disabled";
49*4882a593Smuzhiyun	simple-audio-card,cpu {
50*4882a593Smuzhiyun		sound-dai = <&i2s2_2ch>;
51*4882a593Smuzhiyun	};
52*4882a593Smuzhiyun};
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun&combphy1_usq {
55*4882a593Smuzhiyun	status = "okay";
56*4882a593Smuzhiyun};
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun&csi2_dphy_hw {
59*4882a593Smuzhiyun	status = "okay";
60*4882a593Smuzhiyun};
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun&csi2_dphy0 {
63*4882a593Smuzhiyun	status = "okay";
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun	ports {
66*4882a593Smuzhiyun		#address-cells = <1>;
67*4882a593Smuzhiyun		#size-cells = <0>;
68*4882a593Smuzhiyun		port@0 {
69*4882a593Smuzhiyun			reg = <0>;
70*4882a593Smuzhiyun			#address-cells = <1>;
71*4882a593Smuzhiyun			#size-cells = <0>;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun			mipi_in_ucam0: endpoint@1 {
74*4882a593Smuzhiyun				reg = <1>;
75*4882a593Smuzhiyun				remote-endpoint = <&ov5695_out>;
76*4882a593Smuzhiyun				data-lanes = <1 2>;
77*4882a593Smuzhiyun			};
78*4882a593Smuzhiyun			mipi_in_ucam1: endpoint@2 {
79*4882a593Smuzhiyun				reg = <2>;
80*4882a593Smuzhiyun				remote-endpoint = <&gc8034_out>;
81*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
82*4882a593Smuzhiyun			};
83*4882a593Smuzhiyun		};
84*4882a593Smuzhiyun		port@1 {
85*4882a593Smuzhiyun			reg = <1>;
86*4882a593Smuzhiyun			#address-cells = <1>;
87*4882a593Smuzhiyun			#size-cells = <0>;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun			csidphy_out: endpoint@0 {
90*4882a593Smuzhiyun				reg = <0>;
91*4882a593Smuzhiyun				remote-endpoint = <&isp0_in>;
92*4882a593Smuzhiyun			};
93*4882a593Smuzhiyun		};
94*4882a593Smuzhiyun	};
95*4882a593Smuzhiyun};
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun/*
98*4882a593Smuzhiyun * video_phy0 needs to be enabled
99*4882a593Smuzhiyun * when dsi0 is enabled
100*4882a593Smuzhiyun */
101*4882a593Smuzhiyun&dsi0 {
102*4882a593Smuzhiyun	status = "okay";
103*4882a593Smuzhiyun};
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun&dsi0_in_vp0 {
106*4882a593Smuzhiyun	status = "disabled";
107*4882a593Smuzhiyun};
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun&dsi0_in_vp1 {
110*4882a593Smuzhiyun	status = "okay";
111*4882a593Smuzhiyun};
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun&dsi0_panel {
114*4882a593Smuzhiyun	power-supply = <&vcc3v3_lcd0_n>;
115*4882a593Smuzhiyun	reset-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>;
116*4882a593Smuzhiyun	pinctrl-names = "default";
117*4882a593Smuzhiyun	pinctrl-0 = <&lcd0_rst_gpio>;
118*4882a593Smuzhiyun};
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun/*
121*4882a593Smuzhiyun * video_phy1 needs to be enabled
122*4882a593Smuzhiyun * when dsi1 is enabled
123*4882a593Smuzhiyun */
124*4882a593Smuzhiyun&dsi1 {
125*4882a593Smuzhiyun	status = "disabled";
126*4882a593Smuzhiyun};
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun&dsi1_in_vp0 {
129*4882a593Smuzhiyun	status = "disabled";
130*4882a593Smuzhiyun};
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun&dsi1_in_vp1 {
133*4882a593Smuzhiyun	status = "disabled";
134*4882a593Smuzhiyun};
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun&dsi1_panel {
137*4882a593Smuzhiyun	power-supply = <&vcc3v3_lcd1_n>;
138*4882a593Smuzhiyun	reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>;
139*4882a593Smuzhiyun	pinctrl-names = "default";
140*4882a593Smuzhiyun	pinctrl-0 = <&lcd1_rst_gpio>;
141*4882a593Smuzhiyun};
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun&edp {
144*4882a593Smuzhiyun	hpd-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
145*4882a593Smuzhiyun	status = "okay";
146*4882a593Smuzhiyun};
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun&edp_phy {
149*4882a593Smuzhiyun	status = "okay";
150*4882a593Smuzhiyun};
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun&edp_in_vp0 {
153*4882a593Smuzhiyun	status = "okay";
154*4882a593Smuzhiyun};
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun&edp_in_vp1 {
157*4882a593Smuzhiyun	status = "disabled";
158*4882a593Smuzhiyun};
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun&gmac1 {
161*4882a593Smuzhiyun	phy-mode = "rgmii";
162*4882a593Smuzhiyun	clock_in_out = "output";
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun	snps,reset-gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;
165*4882a593Smuzhiyun	snps,reset-active-low;
166*4882a593Smuzhiyun	/* Reset time is 20ms, 100ms for rtl8211f */
167*4882a593Smuzhiyun	snps,reset-delays-us = <0 20000 100000>;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
170*4882a593Smuzhiyun	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
171*4882a593Smuzhiyun	assigned-clock-rates = <0>, <125000000>;
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun	pinctrl-names = "default";
174*4882a593Smuzhiyun	pinctrl-0 = <&gmac1m0_miim
175*4882a593Smuzhiyun		     &gmac1m0_tx_bus2_level3
176*4882a593Smuzhiyun		     &gmac1m0_rx_bus2
177*4882a593Smuzhiyun		     &gmac1m0_rgmii_clk_level2
178*4882a593Smuzhiyun		     &gmac1m0_rgmii_bus_level3>;
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun	tx_delay = <0x41>;
181*4882a593Smuzhiyun	rx_delay = <0x2e>;
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun	phy-handle = <&rgmii_phy1>;
184*4882a593Smuzhiyun	status = "okay";
185*4882a593Smuzhiyun};
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun&gt1x {
188*4882a593Smuzhiyun	power-supply = <&vcc3v3_lcd0_n>;
189*4882a593Smuzhiyun};
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun&i2c2 {
192*4882a593Smuzhiyun	status = "okay";
193*4882a593Smuzhiyun	pinctrl-0 = <&i2c2m1_xfer>;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun	gc2145: gc2145@3c {
196*4882a593Smuzhiyun		status = "okay";
197*4882a593Smuzhiyun		compatible = "galaxycore,gc2145";
198*4882a593Smuzhiyun		reg = <0x3c>;
199*4882a593Smuzhiyun		clocks = <&cru CLK_CIF_OUT>;
200*4882a593Smuzhiyun		clock-names = "xvclk";
201*4882a593Smuzhiyun		power-domains = <&power RK3568_PD_VI>;
202*4882a593Smuzhiyun		pinctrl-names = "default";
203*4882a593Smuzhiyun		pinctrl-0 = <&cif_clk &cif_dvp_clk &cif_dvp_bus16>;
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun		/*avdd-supply = <&vcc2v8_dvp>;*/
206*4882a593Smuzhiyun		/*dovdd-supply = <&vcc1v8_dvp>;*/
207*4882a593Smuzhiyun		/*dvdd-supply = <&vcc1v8_dvp>;*/
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun		power-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>;
210*4882a593Smuzhiyun		/*reset-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_LOW>;*/
211*4882a593Smuzhiyun		pwdn-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>;
212*4882a593Smuzhiyun		rockchip,camera-module-index = <1>;
213*4882a593Smuzhiyun		rockchip,camera-module-facing = "front";
214*4882a593Smuzhiyun		rockchip,camera-module-name = "CameraKing";
215*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "Largan";
216*4882a593Smuzhiyun		port {
217*4882a593Smuzhiyun			gc2145_out: endpoint {
218*4882a593Smuzhiyun				remote-endpoint = <&dvp_in_bcam>;
219*4882a593Smuzhiyun			};
220*4882a593Smuzhiyun		};
221*4882a593Smuzhiyun	};
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun	ov5695: ov5695@36 {
224*4882a593Smuzhiyun		status = "okay";
225*4882a593Smuzhiyun		compatible = "ovti,ov5695";
226*4882a593Smuzhiyun		reg = <0x36>;
227*4882a593Smuzhiyun		clocks = <&cru CLK_CAM0_OUT>;
228*4882a593Smuzhiyun		clock-names = "xvclk";
229*4882a593Smuzhiyun		power-domains = <&power RK3568_PD_VI>;
230*4882a593Smuzhiyun		pinctrl-names = "default";
231*4882a593Smuzhiyun		pinctrl-0 = <&cam_clkout0>;
232*4882a593Smuzhiyun		reset-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>;
233*4882a593Smuzhiyun		pwdn-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
234*4882a593Smuzhiyun		/*power-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;*/
235*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
236*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
237*4882a593Smuzhiyun		rockchip,camera-module-name = "TongJu";
238*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "CHT842-MD";
239*4882a593Smuzhiyun		port {
240*4882a593Smuzhiyun			ov5695_out: endpoint {
241*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ucam0>;
242*4882a593Smuzhiyun				data-lanes = <1 2>;
243*4882a593Smuzhiyun			};
244*4882a593Smuzhiyun		};
245*4882a593Smuzhiyun	};
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun	gc8034: gc8034@37 {
248*4882a593Smuzhiyun		compatible = "galaxycore,gc8034";
249*4882a593Smuzhiyun		status = "okay";
250*4882a593Smuzhiyun		reg = <0x37>;
251*4882a593Smuzhiyun		clocks = <&cru CLK_CAM0_OUT>;
252*4882a593Smuzhiyun		clock-names = "xvclk";
253*4882a593Smuzhiyun		power-domains = <&power RK3568_PD_VI>;
254*4882a593Smuzhiyun		pinctrl-names = "default";
255*4882a593Smuzhiyun		pinctrl-0 = <&cam_clkout0>;
256*4882a593Smuzhiyun		reset-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_LOW>;
257*4882a593Smuzhiyun		pwdn-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>;
258*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
259*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
260*4882a593Smuzhiyun		rockchip,camera-module-name = "RK-CMK-8M-2-v1";
261*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "CK8401";
262*4882a593Smuzhiyun		port {
263*4882a593Smuzhiyun			gc8034_out: endpoint {
264*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ucam1>;
265*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
266*4882a593Smuzhiyun			};
267*4882a593Smuzhiyun		};
268*4882a593Smuzhiyun	};
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun};
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun&i2s1_8ch {
273*4882a593Smuzhiyun	status = "disabled";
274*4882a593Smuzhiyun};
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun&i2s2_2ch {
277*4882a593Smuzhiyun	pinctrl-0 = <&i2s2m0_sclktx &i2s2m0_lrcktx &i2s2m0_sdi &i2s2m0_sdo>;
278*4882a593Smuzhiyun	rockchip,bclk-fs = <32>;
279*4882a593Smuzhiyun	status = "disabled";
280*4882a593Smuzhiyun};
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun&i2s3_2ch {
283*4882a593Smuzhiyun	status = "okay";
284*4882a593Smuzhiyun	pinctrl-names = "default";
285*4882a593Smuzhiyun	rockchip,clk-trcm = <1>;
286*4882a593Smuzhiyun	pinctrl-0 = <&i2s3m1_sclk
287*4882a593Smuzhiyun		     &i2s3m1_lrck
288*4882a593Smuzhiyun		     &i2s3m1_sdi
289*4882a593Smuzhiyun		     &i2s3m1_sdo>;
290*4882a593Smuzhiyun};
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun&mdio1 {
293*4882a593Smuzhiyun	rgmii_phy1: phy@0 {
294*4882a593Smuzhiyun		compatible = "ethernet-phy-ieee802.3-c22";
295*4882a593Smuzhiyun		reg = <0x0>;
296*4882a593Smuzhiyun	};
297*4882a593Smuzhiyun};
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun&video_phy0 {
300*4882a593Smuzhiyun	status = "okay";
301*4882a593Smuzhiyun};
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun&video_phy1 {
304*4882a593Smuzhiyun	status = "disabled";
305*4882a593Smuzhiyun};
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun&pdm {
308*4882a593Smuzhiyun	status = "disabled";
309*4882a593Smuzhiyun	pinctrl-names = "default";
310*4882a593Smuzhiyun	pinctrl-0 = <&pdmm1_clk1
311*4882a593Smuzhiyun		     &pdmm1_sdi1
312*4882a593Smuzhiyun		     &pdmm1_sdi2
313*4882a593Smuzhiyun		     &pdmm1_sdi3>;
314*4882a593Smuzhiyun};
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun&pdmics {
317*4882a593Smuzhiyun	status = "disabled";
318*4882a593Smuzhiyun};
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun&pdm_mic_array {
321*4882a593Smuzhiyun	status = "disabled";
322*4882a593Smuzhiyun};
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun&pinctrl {
325*4882a593Smuzhiyun	cam {
326*4882a593Smuzhiyun		camera_pwr: camera-pwr {
327*4882a593Smuzhiyun			rockchip,pins =
328*4882a593Smuzhiyun				/* camera power en */
329*4882a593Smuzhiyun				<0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
330*4882a593Smuzhiyun		};
331*4882a593Smuzhiyun	};
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun	headphone {
334*4882a593Smuzhiyun		hp_det: hp-det {
335*4882a593Smuzhiyun			rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>;
336*4882a593Smuzhiyun		};
337*4882a593Smuzhiyun	};
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun	lcd0 {
340*4882a593Smuzhiyun		lcd0_rst_gpio: lcd-rst-gpio {
341*4882a593Smuzhiyun			rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
342*4882a593Smuzhiyun		};
343*4882a593Smuzhiyun	};
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun	lcd1 {
346*4882a593Smuzhiyun		lcd1_rst_gpio: lcd1-rst-gpio {
347*4882a593Smuzhiyun			rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
348*4882a593Smuzhiyun		};
349*4882a593Smuzhiyun	};
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun	sdio-pwrseq {
352*4882a593Smuzhiyun		wifi_enable_h: wifi-enable-h {
353*4882a593Smuzhiyun			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
354*4882a593Smuzhiyun		};
355*4882a593Smuzhiyun	};
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun	wireless-wlan {
358*4882a593Smuzhiyun		wifi_host_wake_irq: wifi-host-wake-irq {
359*4882a593Smuzhiyun			rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>;
360*4882a593Smuzhiyun		};
361*4882a593Smuzhiyun	};
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun	wireless-bluetooth {
364*4882a593Smuzhiyun		uart1_gpios: uart1-gpios {
365*4882a593Smuzhiyun			rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
366*4882a593Smuzhiyun		};
367*4882a593Smuzhiyun	};
368*4882a593Smuzhiyun};
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun&rkcif {
371*4882a593Smuzhiyun	status = "okay";
372*4882a593Smuzhiyun};
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun&rkcif_dvp {
375*4882a593Smuzhiyun	status = "okay";
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun	port {
378*4882a593Smuzhiyun		/* Parallel bus endpoint */
379*4882a593Smuzhiyun		dvp_in_bcam: endpoint {
380*4882a593Smuzhiyun			remote-endpoint = <&gc2145_out>;
381*4882a593Smuzhiyun			bus-width = <8>;
382*4882a593Smuzhiyun			vsync-active = <0>;
383*4882a593Smuzhiyun			hsync-active = <1>;
384*4882a593Smuzhiyun		};
385*4882a593Smuzhiyun	};
386*4882a593Smuzhiyun};
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun&rkisp {
389*4882a593Smuzhiyun	status = "okay";
390*4882a593Smuzhiyun};
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun&rkisp_mmu {
393*4882a593Smuzhiyun	status = "okay";
394*4882a593Smuzhiyun};
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun&rkisp_vir0 {
397*4882a593Smuzhiyun	status = "okay";
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun	port {
400*4882a593Smuzhiyun		#address-cells = <1>;
401*4882a593Smuzhiyun		#size-cells = <0>;
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun		isp0_in: endpoint@0 {
404*4882a593Smuzhiyun			reg = <0>;
405*4882a593Smuzhiyun			remote-endpoint = <&csidphy_out>;
406*4882a593Smuzhiyun		};
407*4882a593Smuzhiyun	};
408*4882a593Smuzhiyun};
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun&rk809_codec {
411*4882a593Smuzhiyun	compatible = "rockchip,rk809-codec", "rockchip,rk817-codec";
412*4882a593Smuzhiyun	clocks = <&cru I2S3_MCLKOUT>;
413*4882a593Smuzhiyun	clock-names = "mclk";
414*4882a593Smuzhiyun	assigned-clocks = <&cru I2S3_MCLKOUT>, <&cru I2S3_MCLK_IOE>;
415*4882a593Smuzhiyun	assigned-clock-rates = <12288000>;
416*4882a593Smuzhiyun	assigned-clock-parents = <&cru I2S3_MCLKOUT_TX>, <&cru I2S3_MCLKOUT>;
417*4882a593Smuzhiyun	pinctrl-names = "default";
418*4882a593Smuzhiyun	pinctrl-0 = <&i2s3m1_mclk>;
419*4882a593Smuzhiyun	hp-volume = <20>;
420*4882a593Smuzhiyun	spk-volume = <3>;
421*4882a593Smuzhiyun	mic-in-differential;
422*4882a593Smuzhiyun	status = "okay";
423*4882a593Smuzhiyun};
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun&rk809_sound {
426*4882a593Smuzhiyun	status = "okay";
427*4882a593Smuzhiyun	compatible = "simple-audio-card";
428*4882a593Smuzhiyun	simple-audio-card,format = "i2s";
429*4882a593Smuzhiyun	simple-audio-card,name = "rockchip,rk809-codec";
430*4882a593Smuzhiyun	simple-audio-card,mclk-fs = <256>;
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun	simple-audio-card,cpu {
433*4882a593Smuzhiyun		sound-dai = <&i2s3_2ch>;
434*4882a593Smuzhiyun	};
435*4882a593Smuzhiyun	simple-audio-card,codec {
436*4882a593Smuzhiyun		sound-dai = <&rk809_codec 0>;
437*4882a593Smuzhiyun	};
438*4882a593Smuzhiyun};
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun&route_dsi0 {
441*4882a593Smuzhiyun	status = "okay";
442*4882a593Smuzhiyun	connect = <&vp1_out_dsi0>;
443*4882a593Smuzhiyun};
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun&sata1 {
446*4882a593Smuzhiyun	status = "okay";
447*4882a593Smuzhiyun};
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun&sdio_pwrseq {
450*4882a593Smuzhiyun	reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
451*4882a593Smuzhiyun};
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun&sdmmc1 {
454*4882a593Smuzhiyun	max-frequency = <150000000>;
455*4882a593Smuzhiyun	no-sd;
456*4882a593Smuzhiyun	no-mmc;
457*4882a593Smuzhiyun	bus-width = <4>;
458*4882a593Smuzhiyun	disable-wp;
459*4882a593Smuzhiyun	cap-sd-highspeed;
460*4882a593Smuzhiyun	cap-sdio-irq;
461*4882a593Smuzhiyun	keep-power-in-suspend;
462*4882a593Smuzhiyun	mmc-pwrseq = <&sdio_pwrseq>;
463*4882a593Smuzhiyun	non-removable;
464*4882a593Smuzhiyun	pinctrl-names = "default";
465*4882a593Smuzhiyun	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
466*4882a593Smuzhiyun	sd-uhs-sdr104;
467*4882a593Smuzhiyun	status = "okay";
468*4882a593Smuzhiyun};
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun&sdmmc2 {
471*4882a593Smuzhiyun	status = "disabled";
472*4882a593Smuzhiyun};
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun&spdif_8ch {
475*4882a593Smuzhiyun	status = "disabled";
476*4882a593Smuzhiyun};
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun&uart1 {
479*4882a593Smuzhiyun	status = "okay";
480*4882a593Smuzhiyun	pinctrl-names = "default";
481*4882a593Smuzhiyun	pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
482*4882a593Smuzhiyun};
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun&vcc3v3_lcd0_n {
485*4882a593Smuzhiyun	gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
486*4882a593Smuzhiyun	enable-active-high;
487*4882a593Smuzhiyun};
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun&wireless_bluetooth {
490*4882a593Smuzhiyun	compatible = "bluetooth-platdata";
491*4882a593Smuzhiyun	clocks = <&rk809 1>;
492*4882a593Smuzhiyun	clock-names = "ext_clock";
493*4882a593Smuzhiyun	//wifi-bt-power-toggle;
494*4882a593Smuzhiyun	uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
495*4882a593Smuzhiyun	pinctrl-names = "default", "rts_gpio";
496*4882a593Smuzhiyun	pinctrl-0 = <&uart1m0_rtsn>;
497*4882a593Smuzhiyun	pinctrl-1 = <&uart1_gpios>;
498*4882a593Smuzhiyun	BT,reset_gpio    = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
499*4882a593Smuzhiyun	BT,wake_gpio     = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
500*4882a593Smuzhiyun	BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
501*4882a593Smuzhiyun	status = "okay";
502*4882a593Smuzhiyun};
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun&wireless_wlan {
505*4882a593Smuzhiyun	pinctrl-names = "default";
506*4882a593Smuzhiyun	pinctrl-0 = <&wifi_host_wake_irq>;
507*4882a593Smuzhiyun	WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>;
508*4882a593Smuzhiyun	WIFI,poweren_gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
509*4882a593Smuzhiyun};
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun&work_led {
512*4882a593Smuzhiyun	gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
513*4882a593Smuzhiyun};
514