xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm64/rockchip/rk3566-evb1-ddr4-v10-lvds.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun#include <dt-bindings/display/media-bus-format.h>
7*4882a593Smuzhiyun#include "rk3566-evb1-ddr4-v10.dtsi"
8*4882a593Smuzhiyun#include "rk3568-android.dtsi"
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun/ {
11*4882a593Smuzhiyun	panel {
12*4882a593Smuzhiyun		compatible = "simple-panel";
13*4882a593Smuzhiyun		backlight = <&backlight>;
14*4882a593Smuzhiyun		power-supply = <&vcc3v3_lcd1_n>;
15*4882a593Smuzhiyun		enable-delay-ms = <20>;
16*4882a593Smuzhiyun		prepare-delay-ms = <20>;
17*4882a593Smuzhiyun		unprepare-delay-ms = <20>;
18*4882a593Smuzhiyun		disable-delay-ms = <20>;
19*4882a593Smuzhiyun		bus-format = <MEDIA_BUS_FMT_RGB666_1X7X3_SPWG>;
20*4882a593Smuzhiyun		width-mm = <217>;
21*4882a593Smuzhiyun		height-mm = <136>;
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun		display-timings {
24*4882a593Smuzhiyun			native-mode = <&timing0>;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun			timing0: timing0 {
27*4882a593Smuzhiyun				clock-frequency = <68000000>;
28*4882a593Smuzhiyun				hactive = <800>;
29*4882a593Smuzhiyun				vactive = <1280>;
30*4882a593Smuzhiyun				hback-porch = <30>;
31*4882a593Smuzhiyun				hfront-porch = <30>;
32*4882a593Smuzhiyun				vback-porch = <4>;
33*4882a593Smuzhiyun				vfront-porch = <2>;
34*4882a593Smuzhiyun				hsync-len = <4>;
35*4882a593Smuzhiyun				vsync-len = <2>;
36*4882a593Smuzhiyun				hsync-active = <0>;
37*4882a593Smuzhiyun				vsync-active = <0>;
38*4882a593Smuzhiyun				de-active = <0>;
39*4882a593Smuzhiyun				pixelclk-active = <0>;
40*4882a593Smuzhiyun			};
41*4882a593Smuzhiyun		};
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun		ports {
44*4882a593Smuzhiyun			#address-cells = <1>;
45*4882a593Smuzhiyun			#size-cells = <0>;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun			port@0 {
48*4882a593Smuzhiyun				reg = <0>;
49*4882a593Smuzhiyun				dual-lvds-even-pixels;
50*4882a593Smuzhiyun				panel_in_lvds: endpoint {
51*4882a593Smuzhiyun					remote-endpoint = <&lvds_out_panel>;
52*4882a593Smuzhiyun				};
53*4882a593Smuzhiyun			};
54*4882a593Smuzhiyun		};
55*4882a593Smuzhiyun	};
56*4882a593Smuzhiyun};
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun&dsi0 {
59*4882a593Smuzhiyun	status = "disabled";
60*4882a593Smuzhiyun};
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun&dsi0_in_vp0 {
63*4882a593Smuzhiyun	status = "disabled";
64*4882a593Smuzhiyun};
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun&dsi0_in_vp1 {
67*4882a593Smuzhiyun	status = "disabled";
68*4882a593Smuzhiyun};
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun&video_phy0 {
71*4882a593Smuzhiyun	status = "okay";
72*4882a593Smuzhiyun};
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun&lvds {
75*4882a593Smuzhiyun	status = "okay";
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun	ports {
78*4882a593Smuzhiyun		port@1 {
79*4882a593Smuzhiyun			reg = <1>;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun			lvds_out_panel: endpoint {
82*4882a593Smuzhiyun				remote-endpoint = <&panel_in_lvds>;
83*4882a593Smuzhiyun			};
84*4882a593Smuzhiyun		};
85*4882a593Smuzhiyun	};
86*4882a593Smuzhiyun};
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun&lvds_in_vp1 {
89*4882a593Smuzhiyun	status = "okay";
90*4882a593Smuzhiyun};
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun&lvds_in_vp2 {
93*4882a593Smuzhiyun	status = "disabled";
94*4882a593Smuzhiyun};
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun&route_lvds {
97*4882a593Smuzhiyun	status = "okay";
98*4882a593Smuzhiyun	connect = <&vp1_out_lvds>;
99*4882a593Smuzhiyun};
100