xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm64/rockchip/rk3562-test2-ddr4-v10.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun/dts-v1/;
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun#include "rk3562.dtsi"
10*4882a593Smuzhiyun#include "rk3562-evb.dtsi"
11*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
12*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun/ {
15*4882a593Smuzhiyun	model = "Rockchip RK3562 TEST2 DDR4 V10 Board";
16*4882a593Smuzhiyun	compatible = "rockchip,rk3562-test2-ddr4-v10", "rockchip,rk3562";
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun	dc_12v: dc-12v {
19*4882a593Smuzhiyun		compatible = "regulator-fixed";
20*4882a593Smuzhiyun		regulator-name = "dc_12v";
21*4882a593Smuzhiyun		regulator-always-on;
22*4882a593Smuzhiyun		regulator-boot-on;
23*4882a593Smuzhiyun		regulator-min-microvolt = <12000000>;
24*4882a593Smuzhiyun		regulator-max-microvolt = <12000000>;
25*4882a593Smuzhiyun	};
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun	vcc5v0_sys: vcc5v0-sys {
28*4882a593Smuzhiyun		compatible = "regulator-fixed";
29*4882a593Smuzhiyun		regulator-name = "vcc5v0_sys";
30*4882a593Smuzhiyun		regulator-always-on;
31*4882a593Smuzhiyun		regulator-boot-on;
32*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
33*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
34*4882a593Smuzhiyun		vin-supply = <&dc_12v>;
35*4882a593Smuzhiyun	};
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun	vcc3v3_sys: vcc-sys {
38*4882a593Smuzhiyun		compatible = "regulator-fixed";
39*4882a593Smuzhiyun		regulator-name = "vcc3v3_sys";
40*4882a593Smuzhiyun		regulator-always-on;
41*4882a593Smuzhiyun		regulator-boot-on;
42*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
43*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
44*4882a593Smuzhiyun		vin-supply = <&dc_12v>;
45*4882a593Smuzhiyun	};
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun	vdd_npu: vdd-npu {
48*4882a593Smuzhiyun		compatible = "pwm-regulator";
49*4882a593Smuzhiyun		pwms = <&pwm6 0 5000 1>;
50*4882a593Smuzhiyun		regulator-name = "vdd_npu";
51*4882a593Smuzhiyun		regulator-min-microvolt = <800000>;
52*4882a593Smuzhiyun		regulator-max-microvolt = <1100000>;
53*4882a593Smuzhiyun		regulator-init-microvolt = <900000>;
54*4882a593Smuzhiyun		regulator-always-on;
55*4882a593Smuzhiyun		regulator-boot-on;
56*4882a593Smuzhiyun		regulator-settling-time-up-us = <250>;
57*4882a593Smuzhiyun		pwm-supply = <&vcc5v0_sys>;
58*4882a593Smuzhiyun		status = "okay";
59*4882a593Smuzhiyun	};
60*4882a593Smuzhiyun};
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun&dsi {
63*4882a593Smuzhiyun	status = "okay";
64*4882a593Smuzhiyun};
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun&dsi_in_vp0 {
67*4882a593Smuzhiyun	status = "okay";
68*4882a593Smuzhiyun};
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun&gmac0 {
71*4882a593Smuzhiyun	/* Use rgmii-rxid mode to disable rx delay inside Soc */
72*4882a593Smuzhiyun	phy-mode = "rmii";
73*4882a593Smuzhiyun	clock_in_out = "output";
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun	snps,reset-gpio = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>;
76*4882a593Smuzhiyun	snps,reset-active-low;
77*4882a593Smuzhiyun	/* Reset time is 20ms, 100ms for rtl8211f */
78*4882a593Smuzhiyun	snps,reset-delays-us = <0 20000 100000>;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun	pinctrl-names = "default";
81*4882a593Smuzhiyun	pinctrl-0 = <&rgmiim0_miim
82*4882a593Smuzhiyun		     &rgmiim0_tx_bus2
83*4882a593Smuzhiyun		     &rgmiim0_rx_bus2
84*4882a593Smuzhiyun		     &rgmiim0_clk>;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun	phy-handle = <&rmii_phy>;
87*4882a593Smuzhiyun	status = "okay";
88*4882a593Smuzhiyun};
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun&mdio0 {
91*4882a593Smuzhiyun	rmii_phy: phy@1 {
92*4882a593Smuzhiyun		compatible = "ethernet-phy-ieee802.3-c22";
93*4882a593Smuzhiyun		reg = <0x1>;
94*4882a593Smuzhiyun	};
95*4882a593Smuzhiyun};
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun&pwm6 {
98*4882a593Smuzhiyun	status = "okay";
99*4882a593Smuzhiyun};
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun&u2phy {
102*4882a593Smuzhiyun	status = "okay";
103*4882a593Smuzhiyun};
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun&u2phy_otg {
106*4882a593Smuzhiyun	status = "okay";
107*4882a593Smuzhiyun};
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun&usbdrd30 {
110*4882a593Smuzhiyun	status = "okay";
111*4882a593Smuzhiyun};
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun&usbdrd_dwc3 {
114*4882a593Smuzhiyun	status = "okay";
115*4882a593Smuzhiyun	dr_mode = "otg";
116*4882a593Smuzhiyun	extcon = <&u2phy>;
117*4882a593Smuzhiyun	maximum-speed = "high-speed";
118*4882a593Smuzhiyun	phys = <&u2phy_otg>;
119*4882a593Smuzhiyun	phy-names = "usb2-phy";
120*4882a593Smuzhiyun	snps,dis_u2_susphy_quirk;
121*4882a593Smuzhiyun	snps,usb2-lpm-disable;
122*4882a593Smuzhiyun};
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun&video_phy {
125*4882a593Smuzhiyun	status = "okay";
126*4882a593Smuzhiyun};
127