xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm64/rockchip/rk3562-rk817-tablet-v10.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun/dts-v1/;
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
10*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h>
11*4882a593Smuzhiyun#include <dt-bindings/input/rk-input.h>
12*4882a593Smuzhiyun#include <dt-bindings/sensor-dev.h>
13*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h>
14*4882a593Smuzhiyun#include "dt-bindings/usb/pd.h"
15*4882a593Smuzhiyun#include "rk3562.dtsi"
16*4882a593Smuzhiyun#include "rk3562-android.dtsi"
17*4882a593Smuzhiyun#include "rk3562-rk817-tablet-camera.dtsi"
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun/ {
20*4882a593Smuzhiyun	model = "Rockchip RK3562 RK817 TABLET LP4 Board";
21*4882a593Smuzhiyun	compatible = "rockchip,rk3562-rk817-tablet", "rockchip,rk3562";
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun	adc_keys: adc-keys {
24*4882a593Smuzhiyun		compatible = "adc-keys";
25*4882a593Smuzhiyun		io-channels = <&saradc0 1>;
26*4882a593Smuzhiyun		io-channel-names = "buttons";
27*4882a593Smuzhiyun		keyup-threshold-microvolt = <1800000>;
28*4882a593Smuzhiyun		poll-interval = <100>;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun		vol-up-key {
31*4882a593Smuzhiyun			label = "volume up";
32*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
33*4882a593Smuzhiyun			press-threshold-microvolt = <1750>;
34*4882a593Smuzhiyun		};
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun		vol-down-key {
37*4882a593Smuzhiyun			label = "volume down";
38*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEDOWN>;
39*4882a593Smuzhiyun			press-threshold-microvolt = <297500>;
40*4882a593Smuzhiyun		};
41*4882a593Smuzhiyun	};
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun	backlight: backlight {
44*4882a593Smuzhiyun		compatible = "pwm-backlight";
45*4882a593Smuzhiyun		pwms = <&pwm5 0 25000 0>;
46*4882a593Smuzhiyun		brightness-levels = <
47*4882a593Smuzhiyun			  0  20  20  21  21  22  22  23
48*4882a593Smuzhiyun			 23  24  24  25  25  26  26  27
49*4882a593Smuzhiyun			 27  28  28  29  29  30  30  31
50*4882a593Smuzhiyun			 31  32  32  33  33  34  34  35
51*4882a593Smuzhiyun			 35  36  36  37  37  38  38  39
52*4882a593Smuzhiyun			 40  41  42  43  44  45  46  47
53*4882a593Smuzhiyun			 48  49  50  50  51  52  53  54
54*4882a593Smuzhiyun			 55  55  56  57  58  59  60  61
55*4882a593Smuzhiyun			 62  63  64  64  65  65  66  67
56*4882a593Smuzhiyun			 68  69  70  71  71  72  73  74
57*4882a593Smuzhiyun			 75  76  77  78  79  79  80  81
58*4882a593Smuzhiyun			 82  83  84  85  86  86  87  88
59*4882a593Smuzhiyun			 89  90  91  92  93  94  94  95
60*4882a593Smuzhiyun			 96  97  98  99 100 101 101 102
61*4882a593Smuzhiyun			103 104 105 106 107 107 108 109
62*4882a593Smuzhiyun			110 111 112 113 114 115 115 116
63*4882a593Smuzhiyun			117 118 119 120 121 122 123 123
64*4882a593Smuzhiyun			124 125 126 127 128 129 130 130
65*4882a593Smuzhiyun			131 132 133 134 135 136 136 137
66*4882a593Smuzhiyun			138 139 140 141 142 143 143 144
67*4882a593Smuzhiyun			145 146 147 147 148 149 150 151
68*4882a593Smuzhiyun			152 153 154 155 156 156 157 158
69*4882a593Smuzhiyun			159 157 158 159 160 161 162 162
70*4882a593Smuzhiyun			163 164 165 166 167 168 169 169
71*4882a593Smuzhiyun			170 171 172 173 174 175 175 176
72*4882a593Smuzhiyun			177 178 179 180 181 182 182 183
73*4882a593Smuzhiyun			184 185 186 187 188 189 190 190
74*4882a593Smuzhiyun			191 192 193 194 195 196 197 197
75*4882a593Smuzhiyun			198 199 200 201 202 203 204 204
76*4882a593Smuzhiyun			205 206 207 208 209 209 210 211
77*4882a593Smuzhiyun			212 213 213 214 214 215 215 216
78*4882a593Smuzhiyun			216 217 217 218 218 219 219 220
79*4882a593Smuzhiyun		>;
80*4882a593Smuzhiyun		default-brightness-level = <200>;
81*4882a593Smuzhiyun	};
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun	charge-animation {
84*4882a593Smuzhiyun		compatible = "rockchip,uboot-charge";
85*4882a593Smuzhiyun		rockchip,uboot-charge-on = <1>;
86*4882a593Smuzhiyun		rockchip,android-charge-on = <0>;
87*4882a593Smuzhiyun		rockchip,uboot-low-power-voltage = <3350>;
88*4882a593Smuzhiyun		rockchip,screen-on-voltage = <3400>;
89*4882a593Smuzhiyun		status = "okay";
90*4882a593Smuzhiyun	};
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun	rk817-sound {
93*4882a593Smuzhiyun		compatible = "rockchip,multicodecs-card";
94*4882a593Smuzhiyun		rockchip,card-name = "rockchip-rk817";
95*4882a593Smuzhiyun		hp-det-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>;
96*4882a593Smuzhiyun		io-channels = <&saradc0 4>;
97*4882a593Smuzhiyun		io-channel-names = "adc-detect";
98*4882a593Smuzhiyun		keyup-threshold-microvolt = <1800000>;
99*4882a593Smuzhiyun		poll-interval = <100>;
100*4882a593Smuzhiyun		rockchip,format = "i2s";
101*4882a593Smuzhiyun		rockchip,mclk-fs = <256>;
102*4882a593Smuzhiyun		rockchip,cpu = <&sai0>;
103*4882a593Smuzhiyun		rockchip,codec = <&rk817_codec>;
104*4882a593Smuzhiyun		pinctrl-names = "default";
105*4882a593Smuzhiyun		pinctrl-0 = <&hp_det>;
106*4882a593Smuzhiyun		play-pause-key {
107*4882a593Smuzhiyun			label = "playpause";
108*4882a593Smuzhiyun			linux,code = <KEY_PLAYPAUSE>;
109*4882a593Smuzhiyun			press-threshold-microvolt = <2000>;
110*4882a593Smuzhiyun		};
111*4882a593Smuzhiyun	};
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun	sdio_pwrseq: sdio-pwrseq {
114*4882a593Smuzhiyun		compatible = "mmc-pwrseq-simple";
115*4882a593Smuzhiyun		clocks = <&rk817 1>;
116*4882a593Smuzhiyun		clock-names = "ext_clock";
117*4882a593Smuzhiyun		pinctrl-names = "default";
118*4882a593Smuzhiyun		pinctrl-0 = <&wifi_enable_h>;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun		/*
121*4882a593Smuzhiyun		 * On the module itself this is one of these (depending
122*4882a593Smuzhiyun		 * on the actual card populated):
123*4882a593Smuzhiyun		 * - SDIO_RESET_L_WL_REG_ON
124*4882a593Smuzhiyun		 * - PDN (power down when low)
125*4882a593Smuzhiyun		 */
126*4882a593Smuzhiyun		post-power-on-delay-ms = <200>;
127*4882a593Smuzhiyun		reset-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>;
128*4882a593Smuzhiyun	};
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun	vcc_sd: vcc-sd {
131*4882a593Smuzhiyun		compatible = "regulator-gpio";
132*4882a593Smuzhiyun		enable-active-low;
133*4882a593Smuzhiyun		enable-gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
134*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
135*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
136*4882a593Smuzhiyun		pinctrl-names = "default";
137*4882a593Smuzhiyun		pinctrl-0 = <&vcc_sd_h>;
138*4882a593Smuzhiyun		regulator-name = "vcc_sd";
139*4882a593Smuzhiyun		states = <3300000 0x0
140*4882a593Smuzhiyun			  3300000 0x1>;
141*4882a593Smuzhiyun	};
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun	vcc_sys: vcc-sys {
144*4882a593Smuzhiyun		compatible = "regulator-fixed";
145*4882a593Smuzhiyun		regulator-name = "vcc_sys";
146*4882a593Smuzhiyun		regulator-always-on;
147*4882a593Smuzhiyun		regulator-boot-on;
148*4882a593Smuzhiyun		regulator-min-microvolt = <3800000>;
149*4882a593Smuzhiyun		regulator-max-microvolt = <3800000>;
150*4882a593Smuzhiyun	};
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun	vdd_gpu: vdd-gpu {
153*4882a593Smuzhiyun		compatible = "pwm-regulator";
154*4882a593Smuzhiyun		pwms = <&pwm7 0 5000 1>;
155*4882a593Smuzhiyun		regulator-name = "vdd_gpu";
156*4882a593Smuzhiyun		regulator-min-microvolt = <800000>;
157*4882a593Smuzhiyun		regulator-max-microvolt = <1100000>;
158*4882a593Smuzhiyun		regulator-init-microvolt = <900000>;
159*4882a593Smuzhiyun		regulator-always-on;
160*4882a593Smuzhiyun		regulator-boot-on;
161*4882a593Smuzhiyun		regulator-settling-time-up-us = <250>;
162*4882a593Smuzhiyun		pwm-supply = <&vcc_sys>;
163*4882a593Smuzhiyun		status = "okay";
164*4882a593Smuzhiyun	};
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun	vdd_npu: vdd-npu {
167*4882a593Smuzhiyun		compatible = "pwm-regulator";
168*4882a593Smuzhiyun		pwms = <&pwm6 0 5000 1>;
169*4882a593Smuzhiyun		regulator-name = "vdd_npu";
170*4882a593Smuzhiyun		regulator-min-microvolt = <800000>;
171*4882a593Smuzhiyun		regulator-max-microvolt = <1100000>;
172*4882a593Smuzhiyun		regulator-init-microvolt = <900000>;
173*4882a593Smuzhiyun		regulator-always-on;
174*4882a593Smuzhiyun		regulator-boot-on;
175*4882a593Smuzhiyun		regulator-settling-time-up-us = <250>;
176*4882a593Smuzhiyun		pwm-supply = <&vcc_sys>;
177*4882a593Smuzhiyun		status = "okay";
178*4882a593Smuzhiyun	};
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun	wireless-wlan {
181*4882a593Smuzhiyun		compatible = "wlan-platdata";
182*4882a593Smuzhiyun		rockchip,grf = <&sys_grf>;
183*4882a593Smuzhiyun		wifi_chip_type = "ap6255";
184*4882a593Smuzhiyun		pinctrl-names = "default";
185*4882a593Smuzhiyun		pinctrl-0 = <&wifi_host_wake_irq>;
186*4882a593Smuzhiyun		WIFI,host_wake_irq = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
187*4882a593Smuzhiyun		WIFI,poweren_gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
188*4882a593Smuzhiyun		WIFI,vbat_gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
189*4882a593Smuzhiyun		status = "okay";
190*4882a593Smuzhiyun	};
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun	wireless-bluetooth {
193*4882a593Smuzhiyun		compatible = "bluetooth-platdata";
194*4882a593Smuzhiyun		clocks = <&rk817 1>;
195*4882a593Smuzhiyun		clock-names = "ext_clock";
196*4882a593Smuzhiyun		//wifi-bt-power-toggle;
197*4882a593Smuzhiyun		uart_rts_gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>;
198*4882a593Smuzhiyun		pinctrl-names = "default", "rts_gpio";
199*4882a593Smuzhiyun		pinctrl-0 = <&uart1m0_rtsn>;
200*4882a593Smuzhiyun		pinctrl-1 = <&uart1_gpios>;
201*4882a593Smuzhiyun		BT,reset_gpio    = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
202*4882a593Smuzhiyun		BT,wake_gpio     = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
203*4882a593Smuzhiyun		BT,wake_host_irq = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
204*4882a593Smuzhiyun		status = "okay";
205*4882a593Smuzhiyun	};
206*4882a593Smuzhiyun};
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun&cpu0 {
209*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu>;
210*4882a593Smuzhiyun};
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun&dfi {
213*4882a593Smuzhiyun	status = "okay";
214*4882a593Smuzhiyun};
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun&display_subsystem {
217*4882a593Smuzhiyun	status = "okay";
218*4882a593Smuzhiyun};
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun&dmc {
221*4882a593Smuzhiyun	center-supply = <&vdd_logic>;
222*4882a593Smuzhiyun	status = "okay";
223*4882a593Smuzhiyun};
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun&dsi {
226*4882a593Smuzhiyun	status = "okay";
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun	panel@0 {
229*4882a593Smuzhiyun		compatible = "aoly,sl008pa21y1285-b00", "simple-panel-dsi";
230*4882a593Smuzhiyun		reg = <0>;
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun		backlight = <&backlight>;
233*4882a593Smuzhiyun		//power-supply=<&vcc_3v3>;
234*4882a593Smuzhiyun		enable-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
235*4882a593Smuzhiyun		reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun		pinctrl-names = "default";
238*4882a593Smuzhiyun		pinctrl-0 = <&lcd_enable_gpio>, <&lcd_rst_gpio>;
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun		prepare-delay-ms = <20>;
241*4882a593Smuzhiyun		reset-delay-ms = <20>;
242*4882a593Smuzhiyun		init-delay-ms = <20>;
243*4882a593Smuzhiyun		enable-delay-ms = <120>;
244*4882a593Smuzhiyun		disable-delay-ms = <20>;
245*4882a593Smuzhiyun		unprepare-delay-ms = <20>;
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun		width-mm = <135>;
248*4882a593Smuzhiyun		height-mm = <216>;
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun		dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
251*4882a593Smuzhiyun			      MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
252*4882a593Smuzhiyun		dsi,format = <MIPI_DSI_FMT_RGB888>;
253*4882a593Smuzhiyun		dsi,lanes = <4>;
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun		panel-init-sequence = [
256*4882a593Smuzhiyun			15 00 02 E0 00
257*4882a593Smuzhiyun			//--- PASSWORD  ----//
258*4882a593Smuzhiyun			15 00 02 E1 93
259*4882a593Smuzhiyun			15 00 02 E2 65
260*4882a593Smuzhiyun			15 00 02 E3 F8
261*4882a593Smuzhiyun			15 00 02 80 03
262*4882a593Smuzhiyun			//--- Page1  ----//
263*4882a593Smuzhiyun			15 00 02 E0 01
264*4882a593Smuzhiyun			//Set VCOM
265*4882a593Smuzhiyun			15 00 02 00 00
266*4882a593Smuzhiyun			15 00 02 01 3B
267*4882a593Smuzhiyun			//Set VCOM_Reverse
268*4882a593Smuzhiyun			//15 00 02 03 00
269*4882a593Smuzhiyun			//15 00 02 04 A0
270*4882a593Smuzhiyun			15 00 02 0C 74
271*4882a593Smuzhiyun			//Set Gamma Power, VGMP,VGMN,VGSP,VGSN
272*4882a593Smuzhiyun			15 00 02 17 00
273*4882a593Smuzhiyun			15 00 02 18 AF  //VGMP=4.8V
274*4882a593Smuzhiyun			15 00 02 19 00  //VGSP=0.3V
275*4882a593Smuzhiyun			15 00 02 1A 00
276*4882a593Smuzhiyun			15 00 02 1B AF
277*4882a593Smuzhiyun			15 00 02 1C 00
278*4882a593Smuzhiyun			//SETPANEL
279*4882a593Smuzhiyun			15 00 02 35 26	//ASP=0110
280*4882a593Smuzhiyun			//SETPANEL
281*4882a593Smuzhiyun			15 00 02 37 09	//SS=1,BGR=1
282*4882a593Smuzhiyun			//SET RGBCYC
283*4882a593Smuzhiyun			15 00 02 38 04	//JDT=100 column inversion
284*4882a593Smuzhiyun			15 00 02 39 00	//RGB_N_EQ1, 0x12
285*4882a593Smuzhiyun			15 00 02 3A 01	//RGB_N_EQ2, 0x18
286*4882a593Smuzhiyun			15 00 02 3C 78	//SET EQ3 for TE_H
287*4882a593Smuzhiyun			15 00 02 3D FF	//SET CHGEN_ON,
288*4882a593Smuzhiyun			15 00 02 3E FF	//SET CHGEN_OFF,
289*4882a593Smuzhiyun			15 00 02 3F 7F	//SET CHGEN_OFF2,
290*4882a593Smuzhiyun			//Set TCON
291*4882a593Smuzhiyun			15 00 02 40 06	//RSO=800 RGB
292*4882a593Smuzhiyun			15 00 02 41 A0	//LN=640->1280 line
293*4882a593Smuzhiyun			15 00 02 42 81	//SLT
294*4882a593Smuzhiyun			15 00 02 43 14	//VFP=20
295*4882a593Smuzhiyun			15 00 02 44 23	//VBP=24
296*4882a593Smuzhiyun			15 00 02 45 28  //HBP=40
297*4882a593Smuzhiyun			//--- power voltage  ----//
298*4882a593Smuzhiyun			15 00 02 55 02	//DCDCM=0001, JD PWR_IC
299*4882a593Smuzhiyun			15 00 02 57 69
300*4882a593Smuzhiyun			15 00 02 59 0A	//VCL = -2.9V
301*4882a593Smuzhiyun			15 00 02 5A 2A	//VGH = 15V
302*4882a593Smuzhiyun			15 00 02 5B 17	//VGL = -11V
303*4882a593Smuzhiyun			//--- Gamma  ----//
304*4882a593Smuzhiyun			15 00 02 5D 7F
305*4882a593Smuzhiyun			15 00 02 5E 6B
306*4882a593Smuzhiyun			15 00 02 5F 5C
307*4882a593Smuzhiyun			15 00 02 60 4F
308*4882a593Smuzhiyun			15 00 02 61 4D
309*4882a593Smuzhiyun			15 00 02 62 3F
310*4882a593Smuzhiyun			15 00 02 63 42
311*4882a593Smuzhiyun			15 00 02 64 2B
312*4882a593Smuzhiyun			15 00 02 65 44
313*4882a593Smuzhiyun			15 00 02 66 43
314*4882a593Smuzhiyun			15 00 02 67 43
315*4882a593Smuzhiyun			15 00 02 68 63
316*4882a593Smuzhiyun			15 00 02 69 52
317*4882a593Smuzhiyun			15 00 02 6A 5A
318*4882a593Smuzhiyun			15 00 02 6B 4F
319*4882a593Smuzhiyun			15 00 02 6C 4E
320*4882a593Smuzhiyun			15 00 02 6D 20
321*4882a593Smuzhiyun			15 00 02 6E 0F
322*4882a593Smuzhiyun			15 00 02 6F 00
323*4882a593Smuzhiyun			15 00 02 70 7F
324*4882a593Smuzhiyun			15 00 02 71 6B
325*4882a593Smuzhiyun			15 00 02 72 5C
326*4882a593Smuzhiyun			15 00 02 73 4F
327*4882a593Smuzhiyun			15 00 02 74 4D
328*4882a593Smuzhiyun			15 00 02 75 3F
329*4882a593Smuzhiyun			15 00 02 76 42
330*4882a593Smuzhiyun			15 00 02 77 2B
331*4882a593Smuzhiyun			15 00 02 78 44
332*4882a593Smuzhiyun			15 00 02 79 43
333*4882a593Smuzhiyun			15 00 02 7A 43
334*4882a593Smuzhiyun			15 00 02 7B 63
335*4882a593Smuzhiyun			15 00 02 7C 52
336*4882a593Smuzhiyun			15 00 02 7D 5A
337*4882a593Smuzhiyun			15 00 02 7E 4F
338*4882a593Smuzhiyun			15 00 02 7F 4E
339*4882a593Smuzhiyun			15 00 02 80 20
340*4882a593Smuzhiyun			15 00 02 81 0F
341*4882a593Smuzhiyun			15 00 02 82 00
342*4882a593Smuzhiyun			//Page2, for GIP
343*4882a593Smuzhiyun			15 00 02 E0 02
344*4882a593Smuzhiyun			//GIP_L Pin mapping
345*4882a593Smuzhiyun			15 00 02 00 02  //STV3	->	STV2
346*4882a593Smuzhiyun			15 00 02 01 02	//Stv3	->	STV2
347*4882a593Smuzhiyun			15 00 02 02 00	//STV4	->	STV0
348*4882a593Smuzhiyun			15 00 02 03 00	//STV4	->	STV0
349*4882a593Smuzhiyun			15 00 02 04 1E	//VDS	->	VGH
350*4882a593Smuzhiyun			15 00 02 05 1E	//VDS	->	VGH
351*4882a593Smuzhiyun			15 00 02 06 1F	//VSD	->	VGL
352*4882a593Smuzhiyun			15 00 02 07 1F	//VSD	->	VGL
353*4882a593Smuzhiyun			15 00 02 08 1F
354*4882a593Smuzhiyun			15 00 02 09 17	//VDD2	->	FLM
355*4882a593Smuzhiyun			15 00 02 0A 17	//VDD2	->	FLM
356*4882a593Smuzhiyun			15 00 02 0B 37	//VDD1	->	INV_FLM
357*4882a593Smuzhiyun			15 00 02 0C 37	//VDD1	->	INV_FLM
358*4882a593Smuzhiyun			15 00 02 0D 47	//CLK8	->	CLK3
359*4882a593Smuzhiyun			15 00 02 0E 47	//CLK8	->	CLK3
360*4882a593Smuzhiyun			15 00 02 0F 45	//CLK6	->	CLK1
361*4882a593Smuzhiyun			15 00 02 10 45	//CLK6	->	CLK1
362*4882a593Smuzhiyun			15 00 02 11 4B	//CLK4	->	CLK7
363*4882a593Smuzhiyun			15 00 02 12 4B	//CLK4	->	CLK7
364*4882a593Smuzhiyun			15 00 02 13 49	//CLK2	->	CLK5
365*4882a593Smuzhiyun			15 00 02 14 49	//CLK2	->	CLK5
366*4882a593Smuzhiyun			15 00 02 15 1F	//VGL
367*4882a593Smuzhiyun			//GIP_R Pin mapping
368*4882a593Smuzhiyun			15 00 02 16 01	//STV1	->	STV1
369*4882a593Smuzhiyun			15 00 02 17 01	//STV1	->	STV1
370*4882a593Smuzhiyun			15 00 02 18 00	//STV2	->	STV0
371*4882a593Smuzhiyun			15 00 02 19 00	//STV2	->	STV0
372*4882a593Smuzhiyun			15 00 02 1A 1E	//VDS	->	VGH
373*4882a593Smuzhiyun			15 00 02 1B 1E	//VDS	->	VGH
374*4882a593Smuzhiyun			15 00 02 1C 1F	//VSD	->	VGL
375*4882a593Smuzhiyun			15 00 02 1D 1F	//VSD	->	VGL
376*4882a593Smuzhiyun			15 00 02 1E 1F
377*4882a593Smuzhiyun			15 00 02 1F 17	//VDD2	->	FLM
378*4882a593Smuzhiyun			15 00 02 20 17	//VDD2	->	FLM
379*4882a593Smuzhiyun			15 00 02 21 37	//VDD1	->	INV_FLM
380*4882a593Smuzhiyun			15 00 02 22 37	//VDD1	->	INV_FLM
381*4882a593Smuzhiyun			15 00 02 23 46	//CLK7	->	CLK2
382*4882a593Smuzhiyun			15 00 02 24 46	//CLK7	->	CLK2
383*4882a593Smuzhiyun			15 00 02 25 44	//CLK5	->	CLK0
384*4882a593Smuzhiyun			15 00 02 26 44	//CLK5	->	CLK0
385*4882a593Smuzhiyun			15 00 02 27 4A	//CLK3	->	CLK6
386*4882a593Smuzhiyun			15 00 02 28 4A	//CLK3	->	CLK6
387*4882a593Smuzhiyun			15 00 02 29 48	//CLK1	->	CLK4
388*4882a593Smuzhiyun			15 00 02 2A 48	//CLK1	->	CLK4
389*4882a593Smuzhiyun			15 00 02 2B 1F	//VGL
390*4882a593Smuzhiyun			//GIP_L_GS Pin mapping
391*4882a593Smuzhiyun			15 00 02 2C 01	//STV3	->	STV1
392*4882a593Smuzhiyun			15 00 02 2D 01
393*4882a593Smuzhiyun			15 00 02 2E 00	//STV4	->	STV0
394*4882a593Smuzhiyun			15 00 02 2F 00
395*4882a593Smuzhiyun			15 00 02 30 1F	//VDS	->	VGL
396*4882a593Smuzhiyun			15 00 02 31 1F
397*4882a593Smuzhiyun			15 00 02 32 1E	//VSD	->	VGH
398*4882a593Smuzhiyun			15 00 02 33 1E
399*4882a593Smuzhiyun			15 00 02 34 1F	//
400*4882a593Smuzhiyun			15 00 02 35 17	//VDD2	->	FLM
401*4882a593Smuzhiyun			15 00 02 36 17
402*4882a593Smuzhiyun			15 00 02 37 37	//VDD1	->	INV_FLM
403*4882a593Smuzhiyun			15 00 02 38 37
404*4882a593Smuzhiyun			15 00 02 39 08	//CLK8	->	CLK4
405*4882a593Smuzhiyun			15 00 02 3A 08
406*4882a593Smuzhiyun			15 00 02 3B 0A	//CLK6	->	CLK6
407*4882a593Smuzhiyun			15 00 02 3C 0A
408*4882a593Smuzhiyun			15 00 02 3D 04	//CLK4	->	CLK0
409*4882a593Smuzhiyun			15 00 02 3E 04
410*4882a593Smuzhiyun			15 00 02 3F 06	//CLK2	->	CLK2
411*4882a593Smuzhiyun			15 00 02 40 06
412*4882a593Smuzhiyun			15 00 02 41 1F	//VGL
413*4882a593Smuzhiyun			//GIP_R_GS Pin mapping
414*4882a593Smuzhiyun			15 00 02 42 02	//STV1	->	STV2
415*4882a593Smuzhiyun			15 00 02 43 02
416*4882a593Smuzhiyun			15 00 02 44 00	//STV2	->	STV0
417*4882a593Smuzhiyun			15 00 02 45 00
418*4882a593Smuzhiyun			15 00 02 46 1F	//VDS	->	VGL
419*4882a593Smuzhiyun			15 00 02 47 1F
420*4882a593Smuzhiyun			15 00 02 48 1E	//VSD	->	VGH
421*4882a593Smuzhiyun			15 00 02 49 1E
422*4882a593Smuzhiyun			15 00 02 4A 1F	//
423*4882a593Smuzhiyun			15 00 02 4B 17	//VDD2	->	FLM
424*4882a593Smuzhiyun			15 00 02 4C 17
425*4882a593Smuzhiyun			15 00 02 4D 37	//VDD1	->	INV_FLM
426*4882a593Smuzhiyun			15 00 02 4E 37
427*4882a593Smuzhiyun			15 00 02 4F 09	//CLK7	->	CLK5
428*4882a593Smuzhiyun			15 00 02 50 09
429*4882a593Smuzhiyun			15 00 02 51 0B	//CLK5	->	CLK7
430*4882a593Smuzhiyun			15 00 02 52 0B
431*4882a593Smuzhiyun			15 00 02 53 05	//CLK3	->	CLK1
432*4882a593Smuzhiyun			15 00 02 54 05
433*4882a593Smuzhiyun			15 00 02 55 07	//CLK1	->	CLK3
434*4882a593Smuzhiyun			15 00 02 56 07
435*4882a593Smuzhiyun			15 00 02 57 1F	//VGL
436*4882a593Smuzhiyun			//GIP Timing
437*4882a593Smuzhiyun			15 00 02 58 40
438*4882a593Smuzhiyun			15 00 02 5B 30  //STV_NUM,STV_S0
439*4882a593Smuzhiyun			15 00 02 5C 16  //STV_S0
440*4882a593Smuzhiyun			15 00 02 5D 34  //STV_W / S1
441*4882a593Smuzhiyun			15 00 02 5E 05  //STV_S2
442*4882a593Smuzhiyun			15 00 02 5F 02  //STV_S3
443*4882a593Smuzhiyun			15 00 02 63 00  //SETV_ON
444*4882a593Smuzhiyun			15 00 02 64 6A  //SETV_OFF
445*4882a593Smuzhiyun			15 00 02 67 73
446*4882a593Smuzhiyun			15 00 02 68 1D  //CKV_S0
447*4882a593Smuzhiyun			15 00 02 69 08
448*4882a593Smuzhiyun			15 00 02 6A 6A
449*4882a593Smuzhiyun			15 00 02 6B 08  //Dummy clk
450*4882a593Smuzhiyun			15 00 02 6C 00
451*4882a593Smuzhiyun			15 00 02 6D 00
452*4882a593Smuzhiyun			15 00 02 6E 00
453*4882a593Smuzhiyun			15 00 02 6F 88
454*4882a593Smuzhiyun			15 00 02 75 FF
455*4882a593Smuzhiyun			15 00 02 77 DD  //VEN_EN=1
456*4882a593Smuzhiyun			15 00 02 78 3F
457*4882a593Smuzhiyun			15 00 02 79 15  //0x0C
458*4882a593Smuzhiyun			15 00 02 7A 17  //VEN_S0
459*4882a593Smuzhiyun			15 00 02 7D 14  //VEN_ON
460*4882a593Smuzhiyun			15 00 02 7E 82  //VEN_OFF
461*4882a593Smuzhiyun			//Page4
462*4882a593Smuzhiyun			15 00 02 E0 04
463*4882a593Smuzhiyun			15 00 02 00 0E
464*4882a593Smuzhiyun			15 00 02 02 B3
465*4882a593Smuzhiyun			15 00 02 09 61
466*4882a593Smuzhiyun			15 00 02 0E 48
467*4882a593Smuzhiyun			//Page0
468*4882a593Smuzhiyun			15 00 02 E0 00
469*4882a593Smuzhiyun			15 00 02 E6 02
470*4882a593Smuzhiyun			15 00 02 E7 0C
471*4882a593Smuzhiyun			05 78 01 11
472*4882a593Smuzhiyun			05 64 01 29
473*4882a593Smuzhiyun		];
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun		panel-exit-sequence = [
476*4882a593Smuzhiyun			05 01 01 28
477*4882a593Smuzhiyun			05 03 01 10
478*4882a593Smuzhiyun		];
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun		display-timings {
481*4882a593Smuzhiyun			native-mode = <&timing0>;
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun			timing0: timing0 {
484*4882a593Smuzhiyun				clock-frequency = <70000000>;
485*4882a593Smuzhiyun				hactive = <800>;
486*4882a593Smuzhiyun				vactive = <1280>;
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun				hfront-porch = <40>;
489*4882a593Smuzhiyun				hsync-len = <20>;
490*4882a593Smuzhiyun				hback-porch = <20>;
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun				vfront-porch = <20>;
493*4882a593Smuzhiyun				vsync-len = <4>;
494*4882a593Smuzhiyun				vback-porch = <20>;
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun				hsync-active = <0>;
497*4882a593Smuzhiyun				vsync-active = <0>;
498*4882a593Smuzhiyun				de-active = <0>;
499*4882a593Smuzhiyun				pixelclk-active = <1>;
500*4882a593Smuzhiyun			};
501*4882a593Smuzhiyun		};
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun		ports {
504*4882a593Smuzhiyun			#address-cells = <1>;
505*4882a593Smuzhiyun			#size-cells = <0>;
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun			port@0 {
508*4882a593Smuzhiyun				reg = <0>;
509*4882a593Smuzhiyun				panel_in_dsi: endpoint {
510*4882a593Smuzhiyun					remote-endpoint = <&dsi_out_panel>;
511*4882a593Smuzhiyun				};
512*4882a593Smuzhiyun			};
513*4882a593Smuzhiyun		};
514*4882a593Smuzhiyun	};
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun	ports {
517*4882a593Smuzhiyun		#address-cells = <1>;
518*4882a593Smuzhiyun		#size-cells = <0>;
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun		port@1 {
521*4882a593Smuzhiyun			reg = <1>;
522*4882a593Smuzhiyun			dsi_out_panel: endpoint {
523*4882a593Smuzhiyun				remote-endpoint = <&panel_in_dsi>;
524*4882a593Smuzhiyun			};
525*4882a593Smuzhiyun		};
526*4882a593Smuzhiyun	};
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun};
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun&dsi_in_vp0 {
531*4882a593Smuzhiyun	status = "okay";
532*4882a593Smuzhiyun};
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun&gpu {
535*4882a593Smuzhiyun	mali-supply = <&vdd_gpu>;
536*4882a593Smuzhiyun	status = "okay";
537*4882a593Smuzhiyun};
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun&i2c0 {
540*4882a593Smuzhiyun	status = "okay";
541*4882a593Smuzhiyun
542*4882a593Smuzhiyun	rk817: pmic@20 {
543*4882a593Smuzhiyun		compatible = "rockchip,rk817";
544*4882a593Smuzhiyun		reg = <0x20>;
545*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
546*4882a593Smuzhiyun		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun		pinctrl-names = "default", "pmic-sleep",
549*4882a593Smuzhiyun			"pmic-power-off", "pmic-reset";
550*4882a593Smuzhiyun		pinctrl-0 = <&pmic_int>;
551*4882a593Smuzhiyun		pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
552*4882a593Smuzhiyun		pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
553*4882a593Smuzhiyun		pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>;
554*4882a593Smuzhiyun		rockchip,system-power-controller;
555*4882a593Smuzhiyun		wakeup-source;
556*4882a593Smuzhiyun		#clock-cells = <1>;
557*4882a593Smuzhiyun		clock-output-names = "rk808-clkout1", "rk808-clkout2";
558*4882a593Smuzhiyun		/* 1: rst regs (default in codes), 0: rst the pmic */
559*4882a593Smuzhiyun		pmic-reset-func = <0>;
560*4882a593Smuzhiyun		vcc1-supply = <&vcc_sys>;
561*4882a593Smuzhiyun		vcc2-supply = <&vcc_sys>;
562*4882a593Smuzhiyun		vcc3-supply = <&vcc_sys>;
563*4882a593Smuzhiyun		vcc4-supply = <&vcc_sys>;
564*4882a593Smuzhiyun		vcc5-supply = <&vcc_sys>;
565*4882a593Smuzhiyun		vcc6-supply = <&vcc_sys>;
566*4882a593Smuzhiyun		vcc7-supply = <&vcc_sys>;
567*4882a593Smuzhiyun		vcc8-supply = <&vcc_sys>;
568*4882a593Smuzhiyun		vcc9-supply = <&dcdc_boost>;
569*4882a593Smuzhiyun		pwrkey {
570*4882a593Smuzhiyun			status = "okay";
571*4882a593Smuzhiyun		};
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun		pinctrl_rk8xx: pinctrl_rk8xx {
574*4882a593Smuzhiyun			gpio-controller;
575*4882a593Smuzhiyun			#gpio-cells = <2>;
576*4882a593Smuzhiyun
577*4882a593Smuzhiyun			rk817_slppin_null: rk817_slppin_null {
578*4882a593Smuzhiyun				pins = "gpio_slp";
579*4882a593Smuzhiyun				function = "pin_fun0";
580*4882a593Smuzhiyun			};
581*4882a593Smuzhiyun
582*4882a593Smuzhiyun			rk817_slppin_slp: rk817_slppin_slp {
583*4882a593Smuzhiyun				pins = "gpio_slp";
584*4882a593Smuzhiyun				function = "pin_fun1";
585*4882a593Smuzhiyun			};
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun			rk817_slppin_pwrdn: rk817_slppin_pwrdn {
588*4882a593Smuzhiyun				pins = "gpio_slp";
589*4882a593Smuzhiyun				function = "pin_fun2";
590*4882a593Smuzhiyun			};
591*4882a593Smuzhiyun
592*4882a593Smuzhiyun			rk817_slppin_rst: rk817_slppin_rst {
593*4882a593Smuzhiyun				pins = "gpio_slp";
594*4882a593Smuzhiyun				function = "pin_fun3";
595*4882a593Smuzhiyun			};
596*4882a593Smuzhiyun		};
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun		regulators {
599*4882a593Smuzhiyun			vdd_logic: DCDC_REG1 {
600*4882a593Smuzhiyun				regulator-always-on;
601*4882a593Smuzhiyun				regulator-boot-on;
602*4882a593Smuzhiyun				regulator-min-microvolt = <500000>;
603*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
604*4882a593Smuzhiyun				regulator-init-microvolt = <900000>;
605*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
606*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
607*4882a593Smuzhiyun				regulator-name = "vdd_logic";
608*4882a593Smuzhiyun				regulator-state-mem {
609*4882a593Smuzhiyun					regulator-off-in-suspend;
610*4882a593Smuzhiyun					regulator-suspend-microvolt = <900000>;
611*4882a593Smuzhiyun				};
612*4882a593Smuzhiyun			};
613*4882a593Smuzhiyun
614*4882a593Smuzhiyun			vdd_cpu: DCDC_REG2 {
615*4882a593Smuzhiyun				regulator-always-on;
616*4882a593Smuzhiyun				regulator-boot-on;
617*4882a593Smuzhiyun				regulator-min-microvolt = <500000>;
618*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
619*4882a593Smuzhiyun				regulator-init-microvolt = <900000>;
620*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
621*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
622*4882a593Smuzhiyun				regulator-name = "vdd_cpu";
623*4882a593Smuzhiyun				regulator-state-mem {
624*4882a593Smuzhiyun					regulator-off-in-suspend;
625*4882a593Smuzhiyun				};
626*4882a593Smuzhiyun			};
627*4882a593Smuzhiyun
628*4882a593Smuzhiyun			vcc_ddr: DCDC_REG3 {
629*4882a593Smuzhiyun				regulator-always-on;
630*4882a593Smuzhiyun				regulator-boot-on;
631*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
632*4882a593Smuzhiyun				regulator-name = "vcc_ddr";
633*4882a593Smuzhiyun				regulator-state-mem {
634*4882a593Smuzhiyun					regulator-on-in-suspend;
635*4882a593Smuzhiyun				};
636*4882a593Smuzhiyun			};
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun			vcc_3v3: DCDC_REG4 {
639*4882a593Smuzhiyun				regulator-always-on;
640*4882a593Smuzhiyun				regulator-boot-on;
641*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
642*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
643*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
644*4882a593Smuzhiyun				regulator-name = "vcc_3v3";
645*4882a593Smuzhiyun				regulator-state-mem {
646*4882a593Smuzhiyun					regulator-on-in-suspend;
647*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
648*4882a593Smuzhiyun				};
649*4882a593Smuzhiyun			};
650*4882a593Smuzhiyun
651*4882a593Smuzhiyun			vcca1v8_pmu: LDO_REG1 {
652*4882a593Smuzhiyun				regulator-always-on;
653*4882a593Smuzhiyun				regulator-boot-on;
654*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
655*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
656*4882a593Smuzhiyun				regulator-name = "vcca1v8_pmu";
657*4882a593Smuzhiyun				regulator-state-mem {
658*4882a593Smuzhiyun					regulator-on-in-suspend;
659*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
660*4882a593Smuzhiyun				};
661*4882a593Smuzhiyun			};
662*4882a593Smuzhiyun
663*4882a593Smuzhiyun			vdda_0v9: LDO_REG2 {
664*4882a593Smuzhiyun				regulator-always-on;
665*4882a593Smuzhiyun				regulator-boot-on;
666*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
667*4882a593Smuzhiyun				regulator-max-microvolt = <900000>;
668*4882a593Smuzhiyun				regulator-name = "vdda_0v9";
669*4882a593Smuzhiyun				regulator-state-mem {
670*4882a593Smuzhiyun					regulator-off-in-suspend;
671*4882a593Smuzhiyun				};
672*4882a593Smuzhiyun			};
673*4882a593Smuzhiyun
674*4882a593Smuzhiyun			vdda0v9_pmu: LDO_REG3 {
675*4882a593Smuzhiyun				regulator-always-on;
676*4882a593Smuzhiyun				regulator-boot-on;
677*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
678*4882a593Smuzhiyun				regulator-max-microvolt = <900000>;
679*4882a593Smuzhiyun				regulator-name = "vdda0v9_pmu";
680*4882a593Smuzhiyun				regulator-state-mem {
681*4882a593Smuzhiyun					regulator-on-in-suspend;
682*4882a593Smuzhiyun					regulator-suspend-microvolt = <900000>;
683*4882a593Smuzhiyun				};
684*4882a593Smuzhiyun			};
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun			vccio_acodec: LDO_REG4 {
687*4882a593Smuzhiyun				regulator-always-on;
688*4882a593Smuzhiyun				regulator-boot-on;
689*4882a593Smuzhiyun				regulator-min-microvolt = <3000000>;
690*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
691*4882a593Smuzhiyun				regulator-name = "vccio_acodec";
692*4882a593Smuzhiyun				regulator-state-mem {
693*4882a593Smuzhiyun					regulator-off-in-suspend;
694*4882a593Smuzhiyun				};
695*4882a593Smuzhiyun			};
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun			vccio_sd: LDO_REG5 {
698*4882a593Smuzhiyun				regulator-always-on;
699*4882a593Smuzhiyun				regulator-boot-on;
700*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
701*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
702*4882a593Smuzhiyun				regulator-name = "vccio_sd";
703*4882a593Smuzhiyun				regulator-state-mem {
704*4882a593Smuzhiyun					regulator-off-in-suspend;
705*4882a593Smuzhiyun				};
706*4882a593Smuzhiyun			};
707*4882a593Smuzhiyun
708*4882a593Smuzhiyun			vcc3v3_pmu: LDO_REG6 {
709*4882a593Smuzhiyun				regulator-always-on;
710*4882a593Smuzhiyun				regulator-boot-on;
711*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
712*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
713*4882a593Smuzhiyun				regulator-name = "vcc3v3_pmu";
714*4882a593Smuzhiyun				regulator-state-mem {
715*4882a593Smuzhiyun					regulator-on-in-suspend;
716*4882a593Smuzhiyun					regulator-suspend-microvolt = <3000000>;
717*4882a593Smuzhiyun				};
718*4882a593Smuzhiyun			};
719*4882a593Smuzhiyun
720*4882a593Smuzhiyun			vcc_1v8: LDO_REG7 {
721*4882a593Smuzhiyun				regulator-always-on;
722*4882a593Smuzhiyun				regulator-boot-on;
723*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
724*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
725*4882a593Smuzhiyun				regulator-name = "vcc_1v8";
726*4882a593Smuzhiyun				regulator-state-mem {
727*4882a593Smuzhiyun					regulator-off-in-suspend;
728*4882a593Smuzhiyun				};
729*4882a593Smuzhiyun			};
730*4882a593Smuzhiyun
731*4882a593Smuzhiyun			vcc1v2_dvp: LDO_REG8 {
732*4882a593Smuzhiyun				regulator-min-microvolt = <1200000>;
733*4882a593Smuzhiyun				regulator-max-microvolt = <1200000>;
734*4882a593Smuzhiyun				regulator-name = "vcc1v2_dvp";
735*4882a593Smuzhiyun				regulator-state-mem {
736*4882a593Smuzhiyun					regulator-off-in-suspend;
737*4882a593Smuzhiyun				};
738*4882a593Smuzhiyun			};
739*4882a593Smuzhiyun
740*4882a593Smuzhiyun			vcc2v8_dvp: LDO_REG9 {
741*4882a593Smuzhiyun				regulator-min-microvolt = <2800000>;
742*4882a593Smuzhiyun				regulator-max-microvolt = <2800000>;
743*4882a593Smuzhiyun				regulator-name = "vcc2v8_dvp";
744*4882a593Smuzhiyun				regulator-state-mem {
745*4882a593Smuzhiyun					regulator-off-in-suspend;
746*4882a593Smuzhiyun				};
747*4882a593Smuzhiyun			};
748*4882a593Smuzhiyun
749*4882a593Smuzhiyun			dcdc_boost: BOOST {
750*4882a593Smuzhiyun				regulator-always-on;
751*4882a593Smuzhiyun				regulator-boot-on;
752*4882a593Smuzhiyun				regulator-min-microvolt = <5000000>;
753*4882a593Smuzhiyun				regulator-max-microvolt = <5400000>;
754*4882a593Smuzhiyun				regulator-name = "boost";
755*4882a593Smuzhiyun				regulator-state-mem {
756*4882a593Smuzhiyun					regulator-off-in-suspend;
757*4882a593Smuzhiyun				};
758*4882a593Smuzhiyun			};
759*4882a593Smuzhiyun
760*4882a593Smuzhiyun			otg_switch: OTG_SWITCH {
761*4882a593Smuzhiyun				regulator-name = "otg_switch";
762*4882a593Smuzhiyun				regulator-state-mem {
763*4882a593Smuzhiyun					regulator-off-in-suspend;
764*4882a593Smuzhiyun				};
765*4882a593Smuzhiyun			};
766*4882a593Smuzhiyun		};
767*4882a593Smuzhiyun
768*4882a593Smuzhiyun		battery {
769*4882a593Smuzhiyun			compatible = "rk817,battery";
770*4882a593Smuzhiyun			ocv_table = <3400 3671 3686 3712 3738 3756 3773
771*4882a593Smuzhiyun				     3787 3802 3819 3840 3868 3916 3959
772*4882a593Smuzhiyun				     3998 4041 4087 4138 4191 4247 4313>;
773*4882a593Smuzhiyun			design_capacity = <5780>;
774*4882a593Smuzhiyun			design_qmax = <6358>;
775*4882a593Smuzhiyun			bat_res = <100>;
776*4882a593Smuzhiyun			sleep_enter_current = <150>;
777*4882a593Smuzhiyun			sleep_exit_current = <180>;
778*4882a593Smuzhiyun			sleep_filter_current = <100>;
779*4882a593Smuzhiyun			power_off_thresd = <3400>;
780*4882a593Smuzhiyun			zero_algorithm_vol = <3950>;
781*4882a593Smuzhiyun			max_soc_offset = <60>;
782*4882a593Smuzhiyun			monitor_sec = <5>;
783*4882a593Smuzhiyun			sample_res = <10>;
784*4882a593Smuzhiyun			virtual_power = <0>;
785*4882a593Smuzhiyun		};
786*4882a593Smuzhiyun
787*4882a593Smuzhiyun		charger {
788*4882a593Smuzhiyun			compatible = "rk817,charger";
789*4882a593Smuzhiyun			min_input_voltage = <4500>;
790*4882a593Smuzhiyun			max_input_current = <1500>;
791*4882a593Smuzhiyun			max_chrg_current = <2000>;
792*4882a593Smuzhiyun			max_chrg_voltage = <4350>;
793*4882a593Smuzhiyun			chrg_term_mode = <0>;
794*4882a593Smuzhiyun			chrg_finish_cur = <300>;
795*4882a593Smuzhiyun			virtual_power = <0>;
796*4882a593Smuzhiyun			dc_det_adc = <0>;
797*4882a593Smuzhiyun			extcon = <&u2phy>;
798*4882a593Smuzhiyun			gate_function_disable = <1>;
799*4882a593Smuzhiyun		};
800*4882a593Smuzhiyun
801*4882a593Smuzhiyun		rk817_codec: codec {
802*4882a593Smuzhiyun			#sound-dai-cells = <0>;
803*4882a593Smuzhiyun			compatible = "rockchip,rk817-codec";
804*4882a593Smuzhiyun			clocks = <&mclkout_sai0>;
805*4882a593Smuzhiyun			clock-names = "mclk";
806*4882a593Smuzhiyun			assigned-clocks = <&mclkout_sai0>;
807*4882a593Smuzhiyun			assigned-clock-rates = <12288000>;
808*4882a593Smuzhiyun			pinctrl-names = "default";
809*4882a593Smuzhiyun			pinctrl-0 = <&i2s0m0_mclk>;
810*4882a593Smuzhiyun			hp-volume = <20>;
811*4882a593Smuzhiyun			spk-volume = <25>;
812*4882a593Smuzhiyun			use-ext-amplifier;
813*4882a593Smuzhiyun			spk-ctl-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
814*4882a593Smuzhiyun			status = "okay";
815*4882a593Smuzhiyun		};
816*4882a593Smuzhiyun	};
817*4882a593Smuzhiyun};
818*4882a593Smuzhiyun
819*4882a593Smuzhiyun&i2c2 {
820*4882a593Smuzhiyun	status = "okay";
821*4882a593Smuzhiyun
822*4882a593Smuzhiyun	ts@40 {
823*4882a593Smuzhiyun		compatible = "GSL,GSL3673_800X1280";
824*4882a593Smuzhiyun		reg = <0x40>;
825*4882a593Smuzhiyun		irq_gpio_number = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
826*4882a593Smuzhiyun		rst_gpio_number = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
827*4882a593Smuzhiyun		pinctrl-names = "default";
828*4882a593Smuzhiyun		pinctrl-0 = <&tp_gpio>;
829*4882a593Smuzhiyun	};
830*4882a593Smuzhiyun};
831*4882a593Smuzhiyun
832*4882a593Smuzhiyun&i2c3 {
833*4882a593Smuzhiyun	status = "okay";
834*4882a593Smuzhiyun	pinctrl-names = "default";
835*4882a593Smuzhiyun	pinctrl-0 = <&i2c3m1_xfer>;
836*4882a593Smuzhiyun
837*4882a593Smuzhiyun	mpu6500_acc: mpu_acc@68 {
838*4882a593Smuzhiyun		compatible = "mpu6500_acc";
839*4882a593Smuzhiyun		reg = <0x68>;
840*4882a593Smuzhiyun		irq-gpio = <&gpio0 RK_PA7 IRQ_TYPE_EDGE_RISING>;
841*4882a593Smuzhiyun		irq_enable = <0>;
842*4882a593Smuzhiyun		poll_delay_ms = <30>;
843*4882a593Smuzhiyun		type = <SENSOR_TYPE_ACCEL>;
844*4882a593Smuzhiyun		layout = <5>;
845*4882a593Smuzhiyun	};
846*4882a593Smuzhiyun
847*4882a593Smuzhiyun	mpu6500_gyro: mpu_gyro@68 {
848*4882a593Smuzhiyun		compatible = "mpu6500_gyro";
849*4882a593Smuzhiyun		reg = <0x68>;
850*4882a593Smuzhiyun		poll_delay_ms = <30>;
851*4882a593Smuzhiyun		type = <SENSOR_TYPE_GYROSCOPE>;
852*4882a593Smuzhiyun		layout = <5>;
853*4882a593Smuzhiyun	};
854*4882a593Smuzhiyun};
855*4882a593Smuzhiyun
856*4882a593Smuzhiyun&jpegd {
857*4882a593Smuzhiyun	status = "okay";
858*4882a593Smuzhiyun};
859*4882a593Smuzhiyun
860*4882a593Smuzhiyun&jpegd_mmu {
861*4882a593Smuzhiyun	status = "okay";
862*4882a593Smuzhiyun};
863*4882a593Smuzhiyun
864*4882a593Smuzhiyun&mpp_srv {
865*4882a593Smuzhiyun	status = "okay";
866*4882a593Smuzhiyun};
867*4882a593Smuzhiyun
868*4882a593Smuzhiyun&pinctrl {
869*4882a593Smuzhiyun	tp {
870*4882a593Smuzhiyun		tp_gpio: tp-gpio {
871*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_down>,
872*4882a593Smuzhiyun					<0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
873*4882a593Smuzhiyun		};
874*4882a593Smuzhiyun	};
875*4882a593Smuzhiyun
876*4882a593Smuzhiyun	headphone {
877*4882a593Smuzhiyun		hp_det: hp-det {
878*4882a593Smuzhiyun			rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
879*4882a593Smuzhiyun		};
880*4882a593Smuzhiyun	};
881*4882a593Smuzhiyun
882*4882a593Smuzhiyun	lcd {
883*4882a593Smuzhiyun		lcd_rst_gpio: lcd-rst-gpio {
884*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
885*4882a593Smuzhiyun		};
886*4882a593Smuzhiyun
887*4882a593Smuzhiyun		lcd_enable_gpio: lcd-enable-gpio {
888*4882a593Smuzhiyun			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
889*4882a593Smuzhiyun		};
890*4882a593Smuzhiyun	};
891*4882a593Smuzhiyun
892*4882a593Smuzhiyun	sdio-pwrseq {
893*4882a593Smuzhiyun		wifi_enable_h: wifi-enable-h {
894*4882a593Smuzhiyun			rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
895*4882a593Smuzhiyun		};
896*4882a593Smuzhiyun	};
897*4882a593Smuzhiyun
898*4882a593Smuzhiyun	vcc_sd {
899*4882a593Smuzhiyun		vcc_sd_h: vcc-sd-h {
900*4882a593Smuzhiyun			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
901*4882a593Smuzhiyun		};
902*4882a593Smuzhiyun	};
903*4882a593Smuzhiyun
904*4882a593Smuzhiyun	wireless-wlan {
905*4882a593Smuzhiyun		wifi_host_wake_irq: wifi-host-wake-irq {
906*4882a593Smuzhiyun			rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
907*4882a593Smuzhiyun		};
908*4882a593Smuzhiyun	};
909*4882a593Smuzhiyun
910*4882a593Smuzhiyun	wireless-bluetooth {
911*4882a593Smuzhiyun		uart1_gpios: uart1-gpios {
912*4882a593Smuzhiyun			rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
913*4882a593Smuzhiyun		};
914*4882a593Smuzhiyun	};
915*4882a593Smuzhiyun};
916*4882a593Smuzhiyun
917*4882a593Smuzhiyun&pwm5 {
918*4882a593Smuzhiyun	status = "okay";
919*4882a593Smuzhiyun};
920*4882a593Smuzhiyun
921*4882a593Smuzhiyun&pwm6 {
922*4882a593Smuzhiyun	status = "okay";
923*4882a593Smuzhiyun};
924*4882a593Smuzhiyun
925*4882a593Smuzhiyun&pwm7 {
926*4882a593Smuzhiyun	status = "okay";
927*4882a593Smuzhiyun};
928*4882a593Smuzhiyun
929*4882a593Smuzhiyun&rga2 {
930*4882a593Smuzhiyun	status = "okay";
931*4882a593Smuzhiyun};
932*4882a593Smuzhiyun
933*4882a593Smuzhiyun&rga2_mmu {
934*4882a593Smuzhiyun	status = "okay";
935*4882a593Smuzhiyun};
936*4882a593Smuzhiyun
937*4882a593Smuzhiyun&rkvdec {
938*4882a593Smuzhiyun	status = "okay";
939*4882a593Smuzhiyun};
940*4882a593Smuzhiyun
941*4882a593Smuzhiyun&rkvdec_mmu {
942*4882a593Smuzhiyun	status = "okay";
943*4882a593Smuzhiyun};
944*4882a593Smuzhiyun
945*4882a593Smuzhiyun&rkvenc {
946*4882a593Smuzhiyun	status = "okay";
947*4882a593Smuzhiyun};
948*4882a593Smuzhiyun
949*4882a593Smuzhiyun&rkvenc_mmu {
950*4882a593Smuzhiyun	status = "okay";
951*4882a593Smuzhiyun};
952*4882a593Smuzhiyun
953*4882a593Smuzhiyun&route_dsi {
954*4882a593Smuzhiyun	status = "okay";
955*4882a593Smuzhiyun};
956*4882a593Smuzhiyun
957*4882a593Smuzhiyun&sai0 {
958*4882a593Smuzhiyun	status = "okay";
959*4882a593Smuzhiyun	pinctrl-names = "default";
960*4882a593Smuzhiyun	pinctrl-0 = <&i2s0m0_lrck
961*4882a593Smuzhiyun		     &i2s0m0_sclk
962*4882a593Smuzhiyun		     &i2s0m0_sdi0
963*4882a593Smuzhiyun		     &i2s0m0_sdo0>;
964*4882a593Smuzhiyun};
965*4882a593Smuzhiyun
966*4882a593Smuzhiyun&saradc0 {
967*4882a593Smuzhiyun	status = "okay";
968*4882a593Smuzhiyun	vref-supply = <&vcc_1v8>;
969*4882a593Smuzhiyun};
970*4882a593Smuzhiyun
971*4882a593Smuzhiyun&sdhci {
972*4882a593Smuzhiyun	bus-width = <8>;
973*4882a593Smuzhiyun	no-sdio;
974*4882a593Smuzhiyun	no-sd;
975*4882a593Smuzhiyun	non-removable;
976*4882a593Smuzhiyun	max-frequency = <200000000>;
977*4882a593Smuzhiyun	mmc-hs400-1_8v;
978*4882a593Smuzhiyun	mmc-hs400-enhanced-strobe;
979*4882a593Smuzhiyun	status = "okay";
980*4882a593Smuzhiyun};
981*4882a593Smuzhiyun
982*4882a593Smuzhiyun&sdmmc0 {
983*4882a593Smuzhiyun	max-frequency = <200000000>;
984*4882a593Smuzhiyun	no-sdio;
985*4882a593Smuzhiyun	no-mmc;
986*4882a593Smuzhiyun	bus-width = <4>;
987*4882a593Smuzhiyun	cap-mmc-highspeed;
988*4882a593Smuzhiyun	cap-sd-highspeed;
989*4882a593Smuzhiyun	disable-wp;
990*4882a593Smuzhiyun	sd-uhs-sdr104;
991*4882a593Smuzhiyun	vmmc-supply = <&vcc_sd>;
992*4882a593Smuzhiyun	vqmmc-supply = <&vccio_sd>;
993*4882a593Smuzhiyun	pinctrl-names = "default";
994*4882a593Smuzhiyun	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
995*4882a593Smuzhiyun	status = "okay";
996*4882a593Smuzhiyun};
997*4882a593Smuzhiyun
998*4882a593Smuzhiyun&sdmmc1 {
999*4882a593Smuzhiyun	max-frequency = <200000000>;
1000*4882a593Smuzhiyun	no-sd;
1001*4882a593Smuzhiyun	no-mmc;
1002*4882a593Smuzhiyun	bus-width = <4>;
1003*4882a593Smuzhiyun	disable-wp;
1004*4882a593Smuzhiyun	cap-sd-highspeed;
1005*4882a593Smuzhiyun	cap-sdio-irq;
1006*4882a593Smuzhiyun	keep-power-in-suspend;
1007*4882a593Smuzhiyun	mmc-pwrseq = <&sdio_pwrseq>;
1008*4882a593Smuzhiyun	non-removable;
1009*4882a593Smuzhiyun	pinctrl-names = "default";
1010*4882a593Smuzhiyun	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
1011*4882a593Smuzhiyun	sd-uhs-sdr104;
1012*4882a593Smuzhiyun	status = "okay";
1013*4882a593Smuzhiyun};
1014*4882a593Smuzhiyun
1015*4882a593Smuzhiyun&tsadc {
1016*4882a593Smuzhiyun	status = "okay";
1017*4882a593Smuzhiyun};
1018*4882a593Smuzhiyun
1019*4882a593Smuzhiyun&u2phy {
1020*4882a593Smuzhiyun	status = "okay";
1021*4882a593Smuzhiyun};
1022*4882a593Smuzhiyun
1023*4882a593Smuzhiyun&u2phy_otg {
1024*4882a593Smuzhiyun	status = "okay";
1025*4882a593Smuzhiyun	vbus-supply = <&otg_switch>;
1026*4882a593Smuzhiyun};
1027*4882a593Smuzhiyun
1028*4882a593Smuzhiyun&uart1 {
1029*4882a593Smuzhiyun	status = "okay";
1030*4882a593Smuzhiyun	pinctrl-names = "default";
1031*4882a593Smuzhiyun	pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
1032*4882a593Smuzhiyun};
1033*4882a593Smuzhiyun
1034*4882a593Smuzhiyun&usbdrd30 {
1035*4882a593Smuzhiyun	status = "okay";
1036*4882a593Smuzhiyun};
1037*4882a593Smuzhiyun
1038*4882a593Smuzhiyun&usbdrd_dwc3 {
1039*4882a593Smuzhiyun	status = "okay";
1040*4882a593Smuzhiyun
1041*4882a593Smuzhiyun	dr_mode = "otg";
1042*4882a593Smuzhiyun	extcon = <&u2phy>;
1043*4882a593Smuzhiyun	maximum-speed = "high-speed";
1044*4882a593Smuzhiyun	phys = <&u2phy_otg>;
1045*4882a593Smuzhiyun	phy-names = "usb2-phy";
1046*4882a593Smuzhiyun	snps,dis_u2_susphy_quirk;
1047*4882a593Smuzhiyun	snps,usb2-lpm-disable;
1048*4882a593Smuzhiyun};
1049*4882a593Smuzhiyun
1050*4882a593Smuzhiyun&video_phy {
1051*4882a593Smuzhiyun	status = "okay";
1052*4882a593Smuzhiyun};
1053*4882a593Smuzhiyun
1054*4882a593Smuzhiyun&vop {
1055*4882a593Smuzhiyun	status = "okay";
1056*4882a593Smuzhiyun};
1057*4882a593Smuzhiyun
1058*4882a593Smuzhiyun&vop_mmu {
1059*4882a593Smuzhiyun	status = "okay";
1060*4882a593Smuzhiyun};
1061