1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include "rk3562.dtsi" 10*4882a593Smuzhiyun#include "rk3562-android.dtsi" 11*4882a593Smuzhiyun#include "rk3562-rk809.dtsi" 12*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun/ { 15*4882a593Smuzhiyun model = "Rockchip RK3562 IOTEST LP3 V10 Board"; 16*4882a593Smuzhiyun compatible = "rockchip,rk3562-iotest-lp3-v10", "rockchip,rk3562"; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun backlight: backlight { 19*4882a593Smuzhiyun compatible = "pwm-backlight"; 20*4882a593Smuzhiyun pwms = <&pwm5 0 25000 0>; 21*4882a593Smuzhiyun brightness-levels = < 22*4882a593Smuzhiyun 0 20 20 21 21 22 22 23 23*4882a593Smuzhiyun 23 24 24 25 25 26 26 27 24*4882a593Smuzhiyun 27 28 28 29 29 30 30 31 25*4882a593Smuzhiyun 31 32 32 33 33 34 34 35 26*4882a593Smuzhiyun 35 36 36 37 37 38 38 39 27*4882a593Smuzhiyun 40 41 42 43 44 45 46 47 28*4882a593Smuzhiyun 48 49 50 51 52 53 54 55 29*4882a593Smuzhiyun 56 57 58 59 60 61 62 63 30*4882a593Smuzhiyun 64 65 66 67 68 69 70 71 31*4882a593Smuzhiyun 72 73 74 75 76 77 78 79 32*4882a593Smuzhiyun 80 81 82 83 84 85 86 87 33*4882a593Smuzhiyun 88 89 90 91 92 93 94 95 34*4882a593Smuzhiyun 96 97 98 99 100 101 102 103 35*4882a593Smuzhiyun 104 105 106 107 108 109 110 111 36*4882a593Smuzhiyun 112 113 114 115 116 117 118 119 37*4882a593Smuzhiyun 120 121 122 123 124 125 126 127 38*4882a593Smuzhiyun 128 129 130 131 132 133 134 135 39*4882a593Smuzhiyun 136 137 138 139 140 141 142 143 40*4882a593Smuzhiyun 144 145 146 147 148 149 150 151 41*4882a593Smuzhiyun 152 153 154 155 156 157 158 159 42*4882a593Smuzhiyun 160 161 162 163 164 165 166 167 43*4882a593Smuzhiyun 168 169 170 171 172 173 174 175 44*4882a593Smuzhiyun 176 177 178 179 180 181 182 183 45*4882a593Smuzhiyun 184 185 186 187 188 189 190 191 46*4882a593Smuzhiyun 192 193 194 195 196 197 198 199 47*4882a593Smuzhiyun 200 201 202 203 204 205 206 207 48*4882a593Smuzhiyun 208 209 210 211 212 213 214 215 49*4882a593Smuzhiyun 216 217 218 219 220 221 222 223 50*4882a593Smuzhiyun 224 225 226 227 228 229 230 231 51*4882a593Smuzhiyun 232 233 234 235 236 237 238 239 52*4882a593Smuzhiyun 240 241 242 243 244 245 246 247 53*4882a593Smuzhiyun 248 249 250 251 252 253 254 255 54*4882a593Smuzhiyun >; 55*4882a593Smuzhiyun default-brightness-level = <200>; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun dc_12v: dc-12v { 59*4882a593Smuzhiyun compatible = "regulator-fixed"; 60*4882a593Smuzhiyun regulator-name = "dc_12v"; 61*4882a593Smuzhiyun regulator-always-on; 62*4882a593Smuzhiyun regulator-boot-on; 63*4882a593Smuzhiyun regulator-min-microvolt = <12000000>; 64*4882a593Smuzhiyun regulator-max-microvolt = <12000000>; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun test-power { 68*4882a593Smuzhiyun status = "okay"; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun vcc3v3_lcd_n: vcc3v3-lcd0-n { 72*4882a593Smuzhiyun compatible = "regulator-fixed"; 73*4882a593Smuzhiyun regulator-name = "vcc3v3_lcd_n"; 74*4882a593Smuzhiyun gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; 75*4882a593Smuzhiyun enable-active-high; 76*4882a593Smuzhiyun regulator-boot-on; 77*4882a593Smuzhiyun regulator-state-mem { 78*4882a593Smuzhiyun regulator-off-in-suspend; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun vcc5v0_sys: vcc5v0-sys { 83*4882a593Smuzhiyun compatible = "regulator-fixed"; 84*4882a593Smuzhiyun regulator-name = "vcc5v0_sys"; 85*4882a593Smuzhiyun regulator-always-on; 86*4882a593Smuzhiyun regulator-boot-on; 87*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 88*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 89*4882a593Smuzhiyun vin-supply = <&dc_12v>; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun vcc3v3_sys: vcc-sys { 93*4882a593Smuzhiyun compatible = "regulator-fixed"; 94*4882a593Smuzhiyun regulator-name = "vcc3v3_sys"; 95*4882a593Smuzhiyun regulator-always-on; 96*4882a593Smuzhiyun regulator-boot-on; 97*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 98*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 99*4882a593Smuzhiyun vin-supply = <&dc_12v>; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun dsm_sound: dsm-sound { 103*4882a593Smuzhiyun status = "disabled"; 104*4882a593Smuzhiyun compatible = "simple-audio-card"; 105*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 106*4882a593Smuzhiyun simple-audio-card,mclk-fs = <256>; 107*4882a593Smuzhiyun simple-audio-card,name = "rockchip,dsm-sound"; 108*4882a593Smuzhiyun simple-audio-card,bitclock-master = <&sndcodec>; 109*4882a593Smuzhiyun simple-audio-card,frame-master = <&sndcodec>; 110*4882a593Smuzhiyun sndcpu: simple-audio-card,cpu { 111*4882a593Smuzhiyun sound-dai = <&sai1>; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun sndcodec: simple-audio-card,codec { 114*4882a593Smuzhiyun sound-dai = <&dsm>; 115*4882a593Smuzhiyun }; 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun}; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun&combphy_pu { 120*4882a593Smuzhiyun status = "okay"; 121*4882a593Smuzhiyun}; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun&cpu0 { 125*4882a593Smuzhiyun cpu-supply = <&vdd_cpu>; 126*4882a593Smuzhiyun}; 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun&display_subsystem { 129*4882a593Smuzhiyun status = "okay"; 130*4882a593Smuzhiyun}; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun&dsi { 133*4882a593Smuzhiyun status = "okay"; 134*4882a593Smuzhiyun //rockchip,lane-rate = <1000>; 135*4882a593Smuzhiyun dsi_panel: panel@0 { 136*4882a593Smuzhiyun status = "okay"; 137*4882a593Smuzhiyun compatible = "simple-panel-dsi"; 138*4882a593Smuzhiyun reg = <0>; 139*4882a593Smuzhiyun backlight = <&backlight>; 140*4882a593Smuzhiyun reset-delay-ms = <60>; 141*4882a593Smuzhiyun enable-delay-ms = <60>; 142*4882a593Smuzhiyun prepare-delay-ms = <60>; 143*4882a593Smuzhiyun unprepare-delay-ms = <60>; 144*4882a593Smuzhiyun disable-delay-ms = <60>; 145*4882a593Smuzhiyun dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 146*4882a593Smuzhiyun MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; 147*4882a593Smuzhiyun dsi,format = <MIPI_DSI_FMT_RGB888>; 148*4882a593Smuzhiyun dsi,lanes = <4>; 149*4882a593Smuzhiyun panel-init-sequence = [ 150*4882a593Smuzhiyun 23 00 02 FE 21 151*4882a593Smuzhiyun 23 00 02 04 00 152*4882a593Smuzhiyun 23 00 02 00 64 153*4882a593Smuzhiyun 23 00 02 2A 00 154*4882a593Smuzhiyun 23 00 02 26 64 155*4882a593Smuzhiyun 23 00 02 54 00 156*4882a593Smuzhiyun 23 00 02 50 64 157*4882a593Smuzhiyun 23 00 02 7B 00 158*4882a593Smuzhiyun 23 00 02 77 64 159*4882a593Smuzhiyun 23 00 02 A2 00 160*4882a593Smuzhiyun 23 00 02 9D 64 161*4882a593Smuzhiyun 23 00 02 C9 00 162*4882a593Smuzhiyun 23 00 02 C5 64 163*4882a593Smuzhiyun 23 00 02 01 71 164*4882a593Smuzhiyun 23 00 02 27 71 165*4882a593Smuzhiyun 23 00 02 51 71 166*4882a593Smuzhiyun 23 00 02 78 71 167*4882a593Smuzhiyun 23 00 02 9E 71 168*4882a593Smuzhiyun 23 00 02 C6 71 169*4882a593Smuzhiyun 23 00 02 02 89 170*4882a593Smuzhiyun 23 00 02 28 89 171*4882a593Smuzhiyun 23 00 02 52 89 172*4882a593Smuzhiyun 23 00 02 79 89 173*4882a593Smuzhiyun 23 00 02 9F 89 174*4882a593Smuzhiyun 23 00 02 C7 89 175*4882a593Smuzhiyun 23 00 02 03 9E 176*4882a593Smuzhiyun 23 00 02 29 9E 177*4882a593Smuzhiyun 23 00 02 53 9E 178*4882a593Smuzhiyun 23 00 02 7A 9E 179*4882a593Smuzhiyun 23 00 02 A0 9E 180*4882a593Smuzhiyun 23 00 02 C8 9E 181*4882a593Smuzhiyun 23 00 02 09 00 182*4882a593Smuzhiyun 23 00 02 05 B0 183*4882a593Smuzhiyun 23 00 02 31 00 184*4882a593Smuzhiyun 23 00 02 2B B0 185*4882a593Smuzhiyun 23 00 02 5A 00 186*4882a593Smuzhiyun 23 00 02 55 B0 187*4882a593Smuzhiyun 23 00 02 80 00 188*4882a593Smuzhiyun 23 00 02 7C B0 189*4882a593Smuzhiyun 23 00 02 A7 00 190*4882a593Smuzhiyun 23 00 02 A3 B0 191*4882a593Smuzhiyun 23 00 02 CE 00 192*4882a593Smuzhiyun 23 00 02 CA B0 193*4882a593Smuzhiyun 23 00 02 06 C0 194*4882a593Smuzhiyun 23 00 02 2D C0 195*4882a593Smuzhiyun 23 00 02 56 C0 196*4882a593Smuzhiyun 23 00 02 7D C0 197*4882a593Smuzhiyun 23 00 02 A4 C0 198*4882a593Smuzhiyun 23 00 02 CB C0 199*4882a593Smuzhiyun 23 00 02 07 CF 200*4882a593Smuzhiyun 23 00 02 2F CF 201*4882a593Smuzhiyun 23 00 02 58 CF 202*4882a593Smuzhiyun 23 00 02 7E CF 203*4882a593Smuzhiyun 23 00 02 A5 CF 204*4882a593Smuzhiyun 23 00 02 CC CF 205*4882a593Smuzhiyun 23 00 02 08 DD 206*4882a593Smuzhiyun 23 00 02 30 DD 207*4882a593Smuzhiyun 23 00 02 59 DD 208*4882a593Smuzhiyun 23 00 02 7F DD 209*4882a593Smuzhiyun 23 00 02 A6 DD 210*4882a593Smuzhiyun 23 00 02 CD DD 211*4882a593Smuzhiyun 23 00 02 0E 15 212*4882a593Smuzhiyun 23 00 02 0A E9 213*4882a593Smuzhiyun 23 00 02 36 15 214*4882a593Smuzhiyun 23 00 02 32 E9 215*4882a593Smuzhiyun 23 00 02 5F 15 216*4882a593Smuzhiyun 23 00 02 5B E9 217*4882a593Smuzhiyun 23 00 02 85 15 218*4882a593Smuzhiyun 23 00 02 81 E9 219*4882a593Smuzhiyun 23 00 02 AD 15 220*4882a593Smuzhiyun 23 00 02 A9 E9 221*4882a593Smuzhiyun 23 00 02 D3 15 222*4882a593Smuzhiyun 23 00 02 CF E9 223*4882a593Smuzhiyun 23 00 02 0B 14 224*4882a593Smuzhiyun 23 00 02 33 14 225*4882a593Smuzhiyun 23 00 02 5C 14 226*4882a593Smuzhiyun 23 00 02 82 14 227*4882a593Smuzhiyun 23 00 02 AA 14 228*4882a593Smuzhiyun 23 00 02 D0 14 229*4882a593Smuzhiyun 23 00 02 0C 36 230*4882a593Smuzhiyun 23 00 02 34 36 231*4882a593Smuzhiyun 23 00 02 5D 36 232*4882a593Smuzhiyun 23 00 02 83 36 233*4882a593Smuzhiyun 23 00 02 AB 36 234*4882a593Smuzhiyun 23 00 02 D1 36 235*4882a593Smuzhiyun 23 00 02 0D 6B 236*4882a593Smuzhiyun 23 00 02 35 6B 237*4882a593Smuzhiyun 23 00 02 5E 6B 238*4882a593Smuzhiyun 23 00 02 84 6B 239*4882a593Smuzhiyun 23 00 02 AC 6B 240*4882a593Smuzhiyun 23 00 02 D2 6B 241*4882a593Smuzhiyun 23 00 02 13 5A 242*4882a593Smuzhiyun 23 00 02 0F 94 243*4882a593Smuzhiyun 23 00 02 3B 5A 244*4882a593Smuzhiyun 23 00 02 37 94 245*4882a593Smuzhiyun 23 00 02 64 5A 246*4882a593Smuzhiyun 23 00 02 60 94 247*4882a593Smuzhiyun 23 00 02 8A 5A 248*4882a593Smuzhiyun 23 00 02 86 94 249*4882a593Smuzhiyun 23 00 02 B2 5A 250*4882a593Smuzhiyun 23 00 02 AE 94 251*4882a593Smuzhiyun 23 00 02 D8 5A 252*4882a593Smuzhiyun 23 00 02 D4 94 253*4882a593Smuzhiyun 23 00 02 10 D1 254*4882a593Smuzhiyun 23 00 02 38 D1 255*4882a593Smuzhiyun 23 00 02 61 D1 256*4882a593Smuzhiyun 23 00 02 87 D1 257*4882a593Smuzhiyun 23 00 02 AF D1 258*4882a593Smuzhiyun 23 00 02 D5 D1 259*4882a593Smuzhiyun 23 00 02 11 04 260*4882a593Smuzhiyun 23 00 02 39 04 261*4882a593Smuzhiyun 23 00 02 62 04 262*4882a593Smuzhiyun 23 00 02 88 04 263*4882a593Smuzhiyun 23 00 02 B0 04 264*4882a593Smuzhiyun 23 00 02 D6 04 265*4882a593Smuzhiyun 23 00 02 12 05 266*4882a593Smuzhiyun 23 00 02 3A 05 267*4882a593Smuzhiyun 23 00 02 63 05 268*4882a593Smuzhiyun 23 00 02 89 05 269*4882a593Smuzhiyun 23 00 02 B1 05 270*4882a593Smuzhiyun 23 00 02 D7 05 271*4882a593Smuzhiyun 23 00 02 18 AA 272*4882a593Smuzhiyun 23 00 02 14 36 273*4882a593Smuzhiyun 23 00 02 42 AA 274*4882a593Smuzhiyun 23 00 02 3D 36 275*4882a593Smuzhiyun 23 00 02 69 AA 276*4882a593Smuzhiyun 23 00 02 65 36 277*4882a593Smuzhiyun 23 00 02 8F AA 278*4882a593Smuzhiyun 23 00 02 8B 36 279*4882a593Smuzhiyun 23 00 02 B7 AA 280*4882a593Smuzhiyun 23 00 02 B3 36 281*4882a593Smuzhiyun 23 00 02 DD AA 282*4882a593Smuzhiyun 23 00 02 D9 36 283*4882a593Smuzhiyun 23 00 02 15 74 284*4882a593Smuzhiyun 23 00 02 3F 74 285*4882a593Smuzhiyun 23 00 02 66 74 286*4882a593Smuzhiyun 23 00 02 8C 74 287*4882a593Smuzhiyun 23 00 02 B4 74 288*4882a593Smuzhiyun 23 00 02 DA 74 289*4882a593Smuzhiyun 23 00 02 16 9F 290*4882a593Smuzhiyun 23 00 02 40 9F 291*4882a593Smuzhiyun 23 00 02 67 9F 292*4882a593Smuzhiyun 23 00 02 8D 9F 293*4882a593Smuzhiyun 23 00 02 B5 9F 294*4882a593Smuzhiyun 23 00 02 DB 9F 295*4882a593Smuzhiyun 23 00 02 17 DC 296*4882a593Smuzhiyun 23 00 02 41 DC 297*4882a593Smuzhiyun 23 00 02 68 DC 298*4882a593Smuzhiyun 23 00 02 8E DC 299*4882a593Smuzhiyun 23 00 02 B6 DC 300*4882a593Smuzhiyun 23 00 02 DC DC 301*4882a593Smuzhiyun 23 00 02 1D FF 302*4882a593Smuzhiyun 23 00 02 19 03 303*4882a593Smuzhiyun 23 00 02 47 FF 304*4882a593Smuzhiyun 23 00 02 43 03 305*4882a593Smuzhiyun 23 00 02 6E FF 306*4882a593Smuzhiyun 23 00 02 6A 03 307*4882a593Smuzhiyun 23 00 02 94 FF 308*4882a593Smuzhiyun 23 00 02 90 03 309*4882a593Smuzhiyun 23 00 02 BC FF 310*4882a593Smuzhiyun 23 00 02 B8 03 311*4882a593Smuzhiyun 23 00 02 E2 FF 312*4882a593Smuzhiyun 23 00 02 DE 03 313*4882a593Smuzhiyun 23 00 02 1A 35 314*4882a593Smuzhiyun 23 00 02 44 35 315*4882a593Smuzhiyun 23 00 02 6B 35 316*4882a593Smuzhiyun 23 00 02 91 35 317*4882a593Smuzhiyun 23 00 02 B9 35 318*4882a593Smuzhiyun 23 00 02 DF 35 319*4882a593Smuzhiyun 23 00 02 1B 45 320*4882a593Smuzhiyun 23 00 02 45 45 321*4882a593Smuzhiyun 23 00 02 6C 45 322*4882a593Smuzhiyun 23 00 02 92 45 323*4882a593Smuzhiyun 23 00 02 BA 45 324*4882a593Smuzhiyun 23 00 02 E0 45 325*4882a593Smuzhiyun 23 00 02 1C 55 326*4882a593Smuzhiyun 23 00 02 46 55 327*4882a593Smuzhiyun 23 00 02 6D 55 328*4882a593Smuzhiyun 23 00 02 93 55 329*4882a593Smuzhiyun 23 00 02 BB 55 330*4882a593Smuzhiyun 23 00 02 E1 55 331*4882a593Smuzhiyun 23 00 02 22 FF 332*4882a593Smuzhiyun 23 00 02 1E 68 333*4882a593Smuzhiyun 23 00 02 4C FF 334*4882a593Smuzhiyun 23 00 02 48 68 335*4882a593Smuzhiyun 23 00 02 73 FF 336*4882a593Smuzhiyun 23 00 02 6F 68 337*4882a593Smuzhiyun 23 00 02 99 FF 338*4882a593Smuzhiyun 23 00 02 95 68 339*4882a593Smuzhiyun 23 00 02 C1 FF 340*4882a593Smuzhiyun 23 00 02 BD 68 341*4882a593Smuzhiyun 23 00 02 E7 FF 342*4882a593Smuzhiyun 23 00 02 E3 68 343*4882a593Smuzhiyun 23 00 02 1F 7E 344*4882a593Smuzhiyun 23 00 02 49 7E 345*4882a593Smuzhiyun 23 00 02 70 7E 346*4882a593Smuzhiyun 23 00 02 96 7E 347*4882a593Smuzhiyun 23 00 02 BE 7E 348*4882a593Smuzhiyun 23 00 02 E4 7E 349*4882a593Smuzhiyun 23 00 02 20 97 350*4882a593Smuzhiyun 23 00 02 4A 97 351*4882a593Smuzhiyun 23 00 02 71 97 352*4882a593Smuzhiyun 23 00 02 97 97 353*4882a593Smuzhiyun 23 00 02 BF 97 354*4882a593Smuzhiyun 23 00 02 E5 97 355*4882a593Smuzhiyun 23 00 02 21 B5 356*4882a593Smuzhiyun 23 00 02 4B B5 357*4882a593Smuzhiyun 23 00 02 72 B5 358*4882a593Smuzhiyun 23 00 02 98 B5 359*4882a593Smuzhiyun 23 00 02 C0 B5 360*4882a593Smuzhiyun 23 00 02 E6 B5 361*4882a593Smuzhiyun 23 00 02 25 F0 362*4882a593Smuzhiyun 23 00 02 23 E8 363*4882a593Smuzhiyun 23 00 02 4F F0 364*4882a593Smuzhiyun 23 00 02 4D E8 365*4882a593Smuzhiyun 23 00 02 76 F0 366*4882a593Smuzhiyun 23 00 02 74 E8 367*4882a593Smuzhiyun 23 00 02 9C F0 368*4882a593Smuzhiyun 23 00 02 9A E8 369*4882a593Smuzhiyun 23 00 02 C4 F0 370*4882a593Smuzhiyun 23 00 02 C2 E8 371*4882a593Smuzhiyun 23 00 02 EA F0 372*4882a593Smuzhiyun 23 00 02 E8 E8 373*4882a593Smuzhiyun 23 00 02 24 FF 374*4882a593Smuzhiyun 23 00 02 4E FF 375*4882a593Smuzhiyun 23 00 02 75 FF 376*4882a593Smuzhiyun 23 00 02 9B FF 377*4882a593Smuzhiyun 23 00 02 C3 FF 378*4882a593Smuzhiyun 23 00 02 E9 FF 379*4882a593Smuzhiyun 23 00 02 FE 3D 380*4882a593Smuzhiyun 23 00 02 00 04 381*4882a593Smuzhiyun 23 00 02 FE 23 382*4882a593Smuzhiyun 23 00 02 08 82 383*4882a593Smuzhiyun 23 00 02 0A 00 384*4882a593Smuzhiyun 23 00 02 0B 00 385*4882a593Smuzhiyun 23 00 02 0C 01 386*4882a593Smuzhiyun 23 00 02 16 00 387*4882a593Smuzhiyun 23 00 02 18 02 388*4882a593Smuzhiyun 23 00 02 1B 04 389*4882a593Smuzhiyun 23 00 02 19 04 390*4882a593Smuzhiyun 23 00 02 1C 81 391*4882a593Smuzhiyun 23 00 02 1F 00 392*4882a593Smuzhiyun 23 00 02 20 03 393*4882a593Smuzhiyun 23 00 02 23 04 394*4882a593Smuzhiyun 23 00 02 21 01 395*4882a593Smuzhiyun 23 00 02 54 63 396*4882a593Smuzhiyun 23 00 02 55 54 397*4882a593Smuzhiyun 23 00 02 6E 45 398*4882a593Smuzhiyun 23 00 02 6D 36 399*4882a593Smuzhiyun 23 00 02 FE 3D 400*4882a593Smuzhiyun 23 00 02 55 78 401*4882a593Smuzhiyun 23 00 02 FE 20 402*4882a593Smuzhiyun 23 00 02 26 30 403*4882a593Smuzhiyun 23 00 02 FE 3D 404*4882a593Smuzhiyun 23 00 02 20 71 405*4882a593Smuzhiyun 23 00 02 50 8F 406*4882a593Smuzhiyun 23 00 02 51 8F 407*4882a593Smuzhiyun 23 00 02 FE 00 408*4882a593Smuzhiyun 23 00 02 35 00 409*4882a593Smuzhiyun 05 78 01 11 410*4882a593Smuzhiyun 05 1E 01 29 411*4882a593Smuzhiyun ]; 412*4882a593Smuzhiyun 413*4882a593Smuzhiyun panel-exit-sequence = [ 414*4882a593Smuzhiyun 05 00 01 28 415*4882a593Smuzhiyun 05 00 01 10 416*4882a593Smuzhiyun ]; 417*4882a593Smuzhiyun 418*4882a593Smuzhiyun disp_timings0: display-timings { 419*4882a593Smuzhiyun native-mode = <&dsi_timing0>; 420*4882a593Smuzhiyun dsi_timing0: timing0 { 421*4882a593Smuzhiyun clock-frequency = <132000000>; 422*4882a593Smuzhiyun hactive = <1080>; 423*4882a593Smuzhiyun vactive = <1920>; 424*4882a593Smuzhiyun hfront-porch = <15>; 425*4882a593Smuzhiyun hsync-len = <2>; 426*4882a593Smuzhiyun hback-porch = <30>; 427*4882a593Smuzhiyun vfront-porch = <15>; 428*4882a593Smuzhiyun vsync-len = <2>; 429*4882a593Smuzhiyun vback-porch = <15>; 430*4882a593Smuzhiyun hsync-active = <0>; 431*4882a593Smuzhiyun vsync-active = <0>; 432*4882a593Smuzhiyun de-active = <0>; 433*4882a593Smuzhiyun pixelclk-active = <1>; 434*4882a593Smuzhiyun }; 435*4882a593Smuzhiyun }; 436*4882a593Smuzhiyun 437*4882a593Smuzhiyun ports { 438*4882a593Smuzhiyun #address-cells = <1>; 439*4882a593Smuzhiyun #size-cells = <0>; 440*4882a593Smuzhiyun 441*4882a593Smuzhiyun port@0 { 442*4882a593Smuzhiyun reg = <0>; 443*4882a593Smuzhiyun panel_in_dsi: endpoint { 444*4882a593Smuzhiyun remote-endpoint = <&dsi_out_panel>; 445*4882a593Smuzhiyun }; 446*4882a593Smuzhiyun }; 447*4882a593Smuzhiyun }; 448*4882a593Smuzhiyun }; 449*4882a593Smuzhiyun 450*4882a593Smuzhiyun ports { 451*4882a593Smuzhiyun #address-cells = <1>; 452*4882a593Smuzhiyun #size-cells = <0>; 453*4882a593Smuzhiyun 454*4882a593Smuzhiyun port@1 { 455*4882a593Smuzhiyun reg = <1>; 456*4882a593Smuzhiyun dsi_out_panel: endpoint { 457*4882a593Smuzhiyun remote-endpoint = <&panel_in_dsi>; 458*4882a593Smuzhiyun }; 459*4882a593Smuzhiyun }; 460*4882a593Smuzhiyun }; 461*4882a593Smuzhiyun 462*4882a593Smuzhiyun}; 463*4882a593Smuzhiyun 464*4882a593Smuzhiyun&dsi_in_vp0 { 465*4882a593Smuzhiyun status = "okay"; 466*4882a593Smuzhiyun}; 467*4882a593Smuzhiyun 468*4882a593Smuzhiyun&dsi_panel { 469*4882a593Smuzhiyun power-supply = <&vcc3v3_lcd_n>; 470*4882a593Smuzhiyun reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; 471*4882a593Smuzhiyun pinctrl-names = "default"; 472*4882a593Smuzhiyun pinctrl-0 = <&lcd_rst_gpio>; 473*4882a593Smuzhiyun}; 474*4882a593Smuzhiyun 475*4882a593Smuzhiyun&gpu { 476*4882a593Smuzhiyun status = "okay"; 477*4882a593Smuzhiyun mali-supply = <&vdd_gpu>; 478*4882a593Smuzhiyun}; 479*4882a593Smuzhiyun 480*4882a593Smuzhiyun&i2c2 { 481*4882a593Smuzhiyun status = "okay"; 482*4882a593Smuzhiyun 483*4882a593Smuzhiyun gt1x: gt1x@14 { 484*4882a593Smuzhiyun compatible = "goodix,gt1x"; 485*4882a593Smuzhiyun reg = <0x14>; 486*4882a593Smuzhiyun pinctrl-names = "default"; 487*4882a593Smuzhiyun pinctrl-0 = <&touch_gpio>; 488*4882a593Smuzhiyun goodix,rst-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; 489*4882a593Smuzhiyun goodix,irq-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; 490*4882a593Smuzhiyun /* 491*4882a593Smuzhiyun * power-supply should switche to vcc3v3_lcd1_n 492*4882a593Smuzhiyun * when mipi panel is connected to dsi1. 493*4882a593Smuzhiyun */ 494*4882a593Smuzhiyun power-supply = <&vcc3v3_lcd_n>; 495*4882a593Smuzhiyun }; 496*4882a593Smuzhiyun}; 497*4882a593Smuzhiyun 498*4882a593Smuzhiyun&pinctrl { 499*4882a593Smuzhiyun lcd { 500*4882a593Smuzhiyun lcd_rst_gpio: lcd-rst-gpio { 501*4882a593Smuzhiyun rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; 502*4882a593Smuzhiyun }; 503*4882a593Smuzhiyun }; 504*4882a593Smuzhiyun 505*4882a593Smuzhiyun touch { 506*4882a593Smuzhiyun touch_gpio: touch-gpio { 507*4882a593Smuzhiyun rockchip,pins = 508*4882a593Smuzhiyun <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>, 509*4882a593Smuzhiyun <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 510*4882a593Smuzhiyun }; 511*4882a593Smuzhiyun }; 512*4882a593Smuzhiyun}; 513*4882a593Smuzhiyun 514*4882a593Smuzhiyun&pwm5 { 515*4882a593Smuzhiyun status = "okay"; 516*4882a593Smuzhiyun}; 517*4882a593Smuzhiyun 518*4882a593Smuzhiyun&route_dsi { 519*4882a593Smuzhiyun status = "okay"; 520*4882a593Smuzhiyun}; 521*4882a593Smuzhiyun 522*4882a593Smuzhiyun&sdhci { 523*4882a593Smuzhiyun bus-width = <8>; 524*4882a593Smuzhiyun no-sdio; 525*4882a593Smuzhiyun no-sd; 526*4882a593Smuzhiyun non-removable; 527*4882a593Smuzhiyun max-frequency = <200000000>; 528*4882a593Smuzhiyun mmc-hs400-1_8v; 529*4882a593Smuzhiyun mmc-hs400-enhanced-strobe; 530*4882a593Smuzhiyun full-pwr-cycle-in-suspend; 531*4882a593Smuzhiyun status = "okay"; 532*4882a593Smuzhiyun}; 533*4882a593Smuzhiyun 534*4882a593Smuzhiyun&u2phy { 535*4882a593Smuzhiyun status = "okay"; 536*4882a593Smuzhiyun}; 537*4882a593Smuzhiyun 538*4882a593Smuzhiyun&u2phy_host { 539*4882a593Smuzhiyun status = "okay"; 540*4882a593Smuzhiyun}; 541*4882a593Smuzhiyun 542*4882a593Smuzhiyun&u2phy_otg { 543*4882a593Smuzhiyun status = "okay"; 544*4882a593Smuzhiyun}; 545*4882a593Smuzhiyun 546*4882a593Smuzhiyun&usb_host0_ehci { 547*4882a593Smuzhiyun status = "okay"; 548*4882a593Smuzhiyun}; 549*4882a593Smuzhiyun 550*4882a593Smuzhiyun&usb_host0_ohci { 551*4882a593Smuzhiyun status = "okay"; 552*4882a593Smuzhiyun}; 553*4882a593Smuzhiyun 554*4882a593Smuzhiyun&usbdrd30 { 555*4882a593Smuzhiyun status = "okay"; 556*4882a593Smuzhiyun}; 557*4882a593Smuzhiyun 558*4882a593Smuzhiyun&usbdrd_dwc3 { 559*4882a593Smuzhiyun status = "okay"; 560*4882a593Smuzhiyun dr_mode = "otg"; 561*4882a593Smuzhiyun extcon = <&u2phy>; 562*4882a593Smuzhiyun snps,dis_u2_susphy_quirk; 563*4882a593Smuzhiyun snps,usb2-lpm-disable; 564*4882a593Smuzhiyun}; 565*4882a593Smuzhiyun 566*4882a593Smuzhiyun&video_phy { 567*4882a593Smuzhiyun status = "okay"; 568*4882a593Smuzhiyun}; 569*4882a593Smuzhiyun 570*4882a593Smuzhiyun&vop { 571*4882a593Smuzhiyun status = "okay"; 572*4882a593Smuzhiyun}; 573*4882a593Smuzhiyun 574*4882a593Smuzhiyun&vop_mmu { 575*4882a593Smuzhiyun status = "okay"; 576*4882a593Smuzhiyun}; 577