1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun vcc_mipicsi0: vcc-mipicsi0-regulator { 9*4882a593Smuzhiyun compatible = "regulator-fixed"; 10*4882a593Smuzhiyun gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; 11*4882a593Smuzhiyun pinctrl-names = "default"; 12*4882a593Smuzhiyun pinctrl-0 = <&mipicsi0_pwr>; 13*4882a593Smuzhiyun regulator-name = "vcc_mipicsi0"; 14*4882a593Smuzhiyun enable-active-high; 15*4882a593Smuzhiyun regulator-always-on; 16*4882a593Smuzhiyun regulator-boot-on; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun}; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun&csi2_dphy0 { 21*4882a593Smuzhiyun status = "okay"; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun ports { 24*4882a593Smuzhiyun #address-cells = <1>; 25*4882a593Smuzhiyun #size-cells = <0>; 26*4882a593Smuzhiyun port@0 { 27*4882a593Smuzhiyun reg = <0>; 28*4882a593Smuzhiyun #address-cells = <1>; 29*4882a593Smuzhiyun #size-cells = <0>; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun mipi_in_ucam0: endpoint@1 { 32*4882a593Smuzhiyun reg = <1>; 33*4882a593Smuzhiyun remote-endpoint = <&n4_out>; 34*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun port@1 { 38*4882a593Smuzhiyun reg = <1>; 39*4882a593Smuzhiyun #address-cells = <1>; 40*4882a593Smuzhiyun #size-cells = <0>; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun csidphy0_out: endpoint@0 { 43*4882a593Smuzhiyun reg = <0>; 44*4882a593Smuzhiyun remote-endpoint = <&mipi0_csi2_input>; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun}; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun&i2c4 { 51*4882a593Smuzhiyun status = "okay"; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun jaguar1: jaguar1@30 { 54*4882a593Smuzhiyun compatible = "jaguar1-v4l2"; 55*4882a593Smuzhiyun status = "okay"; 56*4882a593Smuzhiyun reg = <0x30>; 57*4882a593Smuzhiyun clocks = <&cru CLK_CAM0_OUT2IO>; 58*4882a593Smuzhiyun clock-names = "xvclk"; 59*4882a593Smuzhiyun pinctrl-names = "default"; 60*4882a593Smuzhiyun pinctrl-0 = <&camm0_clk0_out>; 61*4882a593Smuzhiyun pd-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; 62*4882a593Smuzhiyun rst-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; 63*4882a593Smuzhiyun rockchip,camera-module-index = <0>; 64*4882a593Smuzhiyun rockchip,camera-module-facing = "back"; 65*4882a593Smuzhiyun rockchip,camera-module-name = "jaguar1"; 66*4882a593Smuzhiyun rockchip,camera-module-lens-name = "jaguar1"; 67*4882a593Smuzhiyun rockchip,default_rect= <1920 1080>; // default resolution 68*4882a593Smuzhiyun port { 69*4882a593Smuzhiyun n4_out: endpoint { 70*4882a593Smuzhiyun remote-endpoint = <&mipi_in_ucam0>; 71*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun}; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun&csi2_dphy0_hw { 78*4882a593Smuzhiyun status = "okay"; 79*4882a593Smuzhiyun}; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun&mipi0_csi2 { 82*4882a593Smuzhiyun status = "okay"; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun ports { 85*4882a593Smuzhiyun #address-cells = <1>; 86*4882a593Smuzhiyun #size-cells = <0>; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun port@0 { 89*4882a593Smuzhiyun reg = <0>; 90*4882a593Smuzhiyun #address-cells = <1>; 91*4882a593Smuzhiyun #size-cells = <0>; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun mipi0_csi2_input: endpoint@1 { 94*4882a593Smuzhiyun reg = <1>; 95*4882a593Smuzhiyun remote-endpoint = <&csidphy0_out>; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun port@1 { 100*4882a593Smuzhiyun reg = <1>; 101*4882a593Smuzhiyun #address-cells = <1>; 102*4882a593Smuzhiyun #size-cells = <0>; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun mipi0_csi2_output: endpoint@0 { 105*4882a593Smuzhiyun reg = <0>; 106*4882a593Smuzhiyun remote-endpoint = <&cif_mipi_in0>; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun}; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun&rkcif { 113*4882a593Smuzhiyun status = "okay"; 114*4882a593Smuzhiyun rockchip,android-usb-camerahal-enable; 115*4882a593Smuzhiyun}; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun&rkcif_mipi_lvds { 118*4882a593Smuzhiyun status = "okay"; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun port { 121*4882a593Smuzhiyun cif_mipi_in0: endpoint { 122*4882a593Smuzhiyun remote-endpoint = <&mipi0_csi2_output>; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun}; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun&rkcif_mmu { 128*4882a593Smuzhiyun status = "okay"; 129*4882a593Smuzhiyun}; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun&pinctrl { 132*4882a593Smuzhiyun cam { 133*4882a593Smuzhiyun mipicsi0_pwr: mipicsi0-pwr { 134*4882a593Smuzhiyun rockchip,pins = 135*4882a593Smuzhiyun /* camera power en */ 136*4882a593Smuzhiyun <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun}; 140*4882a593Smuzhiyun 141