1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun#include <dt-bindings/display/media-bus-format.h>
8*4882a593Smuzhiyun#include "rk3562-evb1-lp4x-v10.dtsi"
9*4882a593Smuzhiyun#include "rk3562-android.dtsi"
10*4882a593Smuzhiyun#include "rk3562-rk817.dtsi"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun/ {
14*4882a593Smuzhiyun	model = "Rockchip RK3562 EVB1 LP4X V10 Board + RK EVB VOP3 RGB24BIT DISPLAY Ext Board";
15*4882a593Smuzhiyun	compatible = "rockchip,rk3562-evb1-lp4x-v10-rgb-FX070-DHM11BOE-A", "rockchip,rk3562";
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun	panel: panel {
18*4882a593Smuzhiyun		compatible = "simple-panel";
19*4882a593Smuzhiyun		bus-format = <MEDIA_BUS_FMT_RGB888_1X24>;
20*4882a593Smuzhiyun		backlight = <&backlight>;
21*4882a593Smuzhiyun		enable-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
22*4882a593Smuzhiyun		enable-delay-ms = <20>;
23*4882a593Smuzhiyun		reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
24*4882a593Smuzhiyun		reset-value = <0>;
25*4882a593Smuzhiyun		reset-delay-ms = <10>;
26*4882a593Smuzhiyun		status = "okay";
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun		display-timings {
29*4882a593Smuzhiyun			native-mode = <&fx070_dhm11boe_timing>;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun			fx070_dhm11boe_timing: timing0 {
32*4882a593Smuzhiyun				clock-frequency = <50000000>;
33*4882a593Smuzhiyun				hactive = <1024>;
34*4882a593Smuzhiyun				vactive = <600>;
35*4882a593Smuzhiyun				hback-porch = <140>;
36*4882a593Smuzhiyun				hfront-porch = <160>;
37*4882a593Smuzhiyun				vback-porch = <20>;
38*4882a593Smuzhiyun				vfront-porch = <20>;
39*4882a593Smuzhiyun				hsync-len = <20>;
40*4882a593Smuzhiyun				vsync-len = <2>; //value range <2~22>
41*4882a593Smuzhiyun				hsync-active = <0>;
42*4882a593Smuzhiyun				vsync-active = <0>;
43*4882a593Smuzhiyun				de-active = <0>;
44*4882a593Smuzhiyun				pixelclk-active = <0>;
45*4882a593Smuzhiyun			};
46*4882a593Smuzhiyun		};
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun		port {
49*4882a593Smuzhiyun			panel_in_rgb: endpoint {
50*4882a593Smuzhiyun				remote-endpoint = <&rgb_out_panel>;
51*4882a593Smuzhiyun			};
52*4882a593Smuzhiyun		};
53*4882a593Smuzhiyun	};
54*4882a593Smuzhiyun};
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun&backlight {
57*4882a593Smuzhiyun	pwms = <&pwm9 0 25000 0>;
58*4882a593Smuzhiyun	status = "okay";
59*4882a593Smuzhiyun};
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun&csi2_dphy0 {
62*4882a593Smuzhiyun	status = "disabled";
63*4882a593Smuzhiyun};
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun&dsi {
66*4882a593Smuzhiyun	status = "disabled";
67*4882a593Smuzhiyun};
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun/*
70*4882a593Smuzhiyun * The pins of gmac0/pcie2x1/pdm_codec and rgb are multiplexed
71*4882a593Smuzhiyun */
72*4882a593Smuzhiyun&gmac0 {
73*4882a593Smuzhiyun	status = "disabled";
74*4882a593Smuzhiyun};
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun&pcie2x1 {
77*4882a593Smuzhiyun	status = "disabled";
78*4882a593Smuzhiyun};
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun&pdm_codec {
81*4882a593Smuzhiyun	status = "disabled";
82*4882a593Smuzhiyun};
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun&pwm9 {
85*4882a593Smuzhiyun	pinctrl-names = "active";
86*4882a593Smuzhiyun	pinctrl-0 = <&pwm9m0_pins>;
87*4882a593Smuzhiyun	status = "okay";
88*4882a593Smuzhiyun};
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun&rgb {
91*4882a593Smuzhiyun	status = "okay";
92*4882a593Smuzhiyun	pinctrl-0 = <&rgb666_pins>;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun	ports {
95*4882a593Smuzhiyun		port@1 {
96*4882a593Smuzhiyun			reg = <1>;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun			rgb_out_panel: endpoint {
99*4882a593Smuzhiyun				remote-endpoint = <&panel_in_rgb>;
100*4882a593Smuzhiyun			};
101*4882a593Smuzhiyun		};
102*4882a593Smuzhiyun	};
103*4882a593Smuzhiyun};
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun&rgb_in_vp0 {
106*4882a593Smuzhiyun	status = "okay";
107*4882a593Smuzhiyun};
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun&route_rgb {
110*4882a593Smuzhiyun	status = "okay";
111*4882a593Smuzhiyun	connect = <&vp0_out_rgb>;
112*4882a593Smuzhiyun};
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun/*
115*4882a593Smuzhiyun * The pins of sai0/vcc_mipicsi0 and rgb are multiplexed
116*4882a593Smuzhiyun */
117*4882a593Smuzhiyun&sai0 {
118*4882a593Smuzhiyun	status = "disabled";
119*4882a593Smuzhiyun};
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun&vcc_mipicsi0 {
122*4882a593Smuzhiyun	status = "disabled";
123*4882a593Smuzhiyun};
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun&video_phy {
126*4882a593Smuzhiyun	status = "disabled";
127*4882a593Smuzhiyun};
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