xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm64/rockchip/rk3562-dictpen-test3-v20.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun/dts-v1/;
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
9*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h>
10*4882a593Smuzhiyun#include <dt-bindings/input/rk-input.h>
11*4882a593Smuzhiyun#include <dt-bindings/sensor-dev.h>
12*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h>
13*4882a593Smuzhiyun#include "dt-bindings/usb/pd.h"
14*4882a593Smuzhiyun#include "rk3562.dtsi"
15*4882a593Smuzhiyun#include "rk3562-linux.dtsi"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun/ {
18*4882a593Smuzhiyun	model = "Rockchip RK3562 DICTPEN TEST3 LP4 V20 Board";
19*4882a593Smuzhiyun	compatible = "rockchip,rk3562-dictpen-test3-v20", "rockchip,rk3562";
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun	adc_keys: adc-keys {
22*4882a593Smuzhiyun		compatible = "adc-keys";
23*4882a593Smuzhiyun		io-channels = <&saradc0 1>;
24*4882a593Smuzhiyun		io-channel-names = "buttons";
25*4882a593Smuzhiyun		keyup-threshold-microvolt = <1800000>;
26*4882a593Smuzhiyun		poll-interval = <100>;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun		vol-up-key {
29*4882a593Smuzhiyun			label = "volume up";
30*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
31*4882a593Smuzhiyun			press-threshold-microvolt = <17000>;
32*4882a593Smuzhiyun		};
33*4882a593Smuzhiyun	};
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun	backlight: backlight {
36*4882a593Smuzhiyun		compatible = "pwm-backlight";
37*4882a593Smuzhiyun		pwms = <&pwm12 0 25000 0>;
38*4882a593Smuzhiyun		brightness-levels = <
39*4882a593Smuzhiyun			  0  20  20  21  21  22  22  23
40*4882a593Smuzhiyun			 23  24  24  25  25  26  26  27
41*4882a593Smuzhiyun			 27  28  28  29  29  30  30  31
42*4882a593Smuzhiyun			 31  32  32  33  33  34  34  35
43*4882a593Smuzhiyun			 35  36  36  37  37  38  38  39
44*4882a593Smuzhiyun			 40  41  42  43  44  45  46  47
45*4882a593Smuzhiyun			 48  49  50  50  51  52  53  54
46*4882a593Smuzhiyun			 55  55  56  57  58  59  60  61
47*4882a593Smuzhiyun			 62  63  64  64  65  65  66  67
48*4882a593Smuzhiyun			 68  69  70  71  71  72  73  74
49*4882a593Smuzhiyun			 75  76  77  78  79  79  80  81
50*4882a593Smuzhiyun			 82  83  84  85  86  86  87  88
51*4882a593Smuzhiyun			 89  90  91  92  93  94  94  95
52*4882a593Smuzhiyun			 96  97  98  99 100 101 101 102
53*4882a593Smuzhiyun			103 104 105 106 107 107 108 109
54*4882a593Smuzhiyun			110 111 112 113 114 115 115 116
55*4882a593Smuzhiyun			117 118 119 120 121 122 123 123
56*4882a593Smuzhiyun			124 125 126 127 128 129 130 130
57*4882a593Smuzhiyun			131 132 133 134 135 136 136 137
58*4882a593Smuzhiyun			138 139 140 141 142 143 143 144
59*4882a593Smuzhiyun			145 146 147 147 148 149 150 151
60*4882a593Smuzhiyun			152 153 154 155 156 156 157 158
61*4882a593Smuzhiyun			159 157 158 159 160 161 162 162
62*4882a593Smuzhiyun			163 164 165 166 167 168 169 169
63*4882a593Smuzhiyun			170 171 172 173 174 175 175 176
64*4882a593Smuzhiyun			177 178 179 180 181 182 182 183
65*4882a593Smuzhiyun			184 185 186 187 188 189 190 190
66*4882a593Smuzhiyun			191 192 193 194 195 196 197 197
67*4882a593Smuzhiyun			198 199 200 201 202 203 204 204
68*4882a593Smuzhiyun			205 206 207 208 209 209 210 211
69*4882a593Smuzhiyun			212 213 213 214 214 215 215 216
70*4882a593Smuzhiyun			216 217 217 218 218 219 219 220
71*4882a593Smuzhiyun		>;
72*4882a593Smuzhiyun		default-brightness-level = <60>;
73*4882a593Smuzhiyun	};
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun	charge-animation {
76*4882a593Smuzhiyun		compatible = "rockchip,uboot-charge";
77*4882a593Smuzhiyun		rockchip,uboot-charge-on = <0>;
78*4882a593Smuzhiyun		rockchip,android-charge-on = <0>;
79*4882a593Smuzhiyun		rockchip,uboot-low-power-voltage = <2800>;
80*4882a593Smuzhiyun		rockchip,screen-on-voltage = <3000>;
81*4882a593Smuzhiyun		status = "okay";
82*4882a593Smuzhiyun	};
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun	gpio-keys {
85*4882a593Smuzhiyun		compatible = "gpio-keys";
86*4882a593Smuzhiyun		autorepeat;
87*4882a593Smuzhiyun		pinctrl-names = "default";
88*4882a593Smuzhiyun		pinctrl-0 = <&scan_key>;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun		button@0 {
91*4882a593Smuzhiyun			label = "home";
92*4882a593Smuzhiyun			linux,code = <KEY_HOME>;
93*4882a593Smuzhiyun			gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
94*4882a593Smuzhiyun			debounce-interval = <50>;
95*4882a593Smuzhiyun		};
96*4882a593Smuzhiyun	};
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun	rk817-sound {
99*4882a593Smuzhiyun		compatible = "rockchip,multicodecs-card";
100*4882a593Smuzhiyun		rockchip,card-name = "rockchip-rk817";
101*4882a593Smuzhiyun		rockchip,format = "i2s";
102*4882a593Smuzhiyun		rockchip,mclk-fs = <256>;
103*4882a593Smuzhiyun		rockchip,cpu = <&sai0>;
104*4882a593Smuzhiyun		rockchip,codec = <&rk817_codec>;
105*4882a593Smuzhiyun	};
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun	vcc_sys: vcc-sys {
108*4882a593Smuzhiyun		compatible = "regulator-fixed";
109*4882a593Smuzhiyun		regulator-name = "vcc_sys";
110*4882a593Smuzhiyun		regulator-always-on;
111*4882a593Smuzhiyun		regulator-boot-on;
112*4882a593Smuzhiyun		regulator-min-microvolt = <3800000>;
113*4882a593Smuzhiyun		regulator-max-microvolt = <3800000>;
114*4882a593Smuzhiyun	};
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun	vccsys_lcd: vccsys-lcd {
117*4882a593Smuzhiyun		compatible = "regulator-fixed";
118*4882a593Smuzhiyun		regulator-name = "vccsys_lcd";
119*4882a593Smuzhiyun		regulator-boot-on;
120*4882a593Smuzhiyun		enable-active-high;
121*4882a593Smuzhiyun		gpio = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>;
122*4882a593Smuzhiyun		vin-supply = <&vcc3v3_lcd>;
123*4882a593Smuzhiyun	};
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun	sdio_pwrseq: sdio-pwrseq {
126*4882a593Smuzhiyun		compatible = "mmc-pwrseq-simple";
127*4882a593Smuzhiyun		pinctrl-names = "default";
128*4882a593Smuzhiyun		pinctrl-0 = <&wifi_enable_l>;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun		/*
131*4882a593Smuzhiyun		 * On the module itself this is one of these (depending
132*4882a593Smuzhiyun		 * on the actual card populated):
133*4882a593Smuzhiyun		 * - SDIO_RESET_L_WL_REG_ON
134*4882a593Smuzhiyun		 * - PDN (power down when low)
135*4882a593Smuzhiyun		 */
136*4882a593Smuzhiyun		post-power-on-delay-ms = <200>;
137*4882a593Smuzhiyun		reset-gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_HIGH>;
138*4882a593Smuzhiyun	};
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun	wireless-wlan {
141*4882a593Smuzhiyun		compatible = "wlan-platdata";
142*4882a593Smuzhiyun		rockchip,grf = <&sys_grf>;
143*4882a593Smuzhiyun		wifi_chip_type = "ap6203";
144*4882a593Smuzhiyun		pinctrl-names = "default";
145*4882a593Smuzhiyun		pinctrl-0 = <&wifi_host_wake_irq>;
146*4882a593Smuzhiyun		WIFI,host_wake_irq = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>;
147*4882a593Smuzhiyun		status = "okay";
148*4882a593Smuzhiyun	};
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun	wireless-bluetooth {
151*4882a593Smuzhiyun		compatible = "bluetooth-platdata";
152*4882a593Smuzhiyun		clocks = <&rk817 1>;
153*4882a593Smuzhiyun		clock-names = "ext_clock";
154*4882a593Smuzhiyun		uart_rts_gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>;
155*4882a593Smuzhiyun		pinctrl-names = "default", "rts_gpio";
156*4882a593Smuzhiyun		pinctrl-0 = <&uart1m0_rtsn>;
157*4882a593Smuzhiyun		pinctrl-1 = <&uart1_gpios>;
158*4882a593Smuzhiyun		BT,power_gpio    = <&gpio1 RK_PD7 GPIO_ACTIVE_LOW>;
159*4882a593Smuzhiyun		//BT,wake_gpio     = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
160*4882a593Smuzhiyun		//BT,wake_host_irq = <&gpio1 RK_PD6 GPIO_ACTIVE_HIGH>;
161*4882a593Smuzhiyun		status = "okay";
162*4882a593Smuzhiyun	};
163*4882a593Smuzhiyun};
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun&cpu0 {
166*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu>;
167*4882a593Smuzhiyun};
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun&cpu0_opp_table {
170*4882a593Smuzhiyun	opp-408000000 {
171*4882a593Smuzhiyun	/delete-property/ opp-suspend;
172*4882a593Smuzhiyun	};
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun	opp-1200000000 {
175*4882a593Smuzhiyun		opp-suspend;
176*4882a593Smuzhiyun	};
177*4882a593Smuzhiyun	/delete-node/ opp-1608000000;
178*4882a593Smuzhiyun	/delete-node/ opp-1800000000;
179*4882a593Smuzhiyun	/delete-node/ opp-2016000000;
180*4882a593Smuzhiyun};
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun&csi2_dphy0 {
183*4882a593Smuzhiyun	status = "okay";
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun	ports {
186*4882a593Smuzhiyun		#address-cells = <1>;
187*4882a593Smuzhiyun		#size-cells = <0>;
188*4882a593Smuzhiyun		port@0 {
189*4882a593Smuzhiyun			reg = <0>;
190*4882a593Smuzhiyun			#address-cells = <1>;
191*4882a593Smuzhiyun			#size-cells = <0>;
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun			mipi_in_ucam0: endpoint@1 {
194*4882a593Smuzhiyun				reg = <1>;
195*4882a593Smuzhiyun				remote-endpoint = <&sc031gs_out>;
196*4882a593Smuzhiyun				data-lanes = <1>;
197*4882a593Smuzhiyun			};
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun		};
200*4882a593Smuzhiyun		port@1 {
201*4882a593Smuzhiyun			reg = <1>;
202*4882a593Smuzhiyun			#address-cells = <1>;
203*4882a593Smuzhiyun			#size-cells = <0>;
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun			csidcphy0_out: endpoint@0 {
206*4882a593Smuzhiyun				reg = <0>;
207*4882a593Smuzhiyun				remote-endpoint = <&mipi0_csi2_input>;
208*4882a593Smuzhiyun			};
209*4882a593Smuzhiyun		};
210*4882a593Smuzhiyun	};
211*4882a593Smuzhiyun};
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun&csi2_dphy0_hw {
214*4882a593Smuzhiyun	status = "okay";
215*4882a593Smuzhiyun};
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun&dfi {
218*4882a593Smuzhiyun	status = "okay";
219*4882a593Smuzhiyun};
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun&display_subsystem {
222*4882a593Smuzhiyun	status = "okay";
223*4882a593Smuzhiyun};
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun&dmc {
226*4882a593Smuzhiyun	center-supply = <&vdd_logic>;
227*4882a593Smuzhiyun	status = "okay";
228*4882a593Smuzhiyun};
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun&dsi {
231*4882a593Smuzhiyun	status = "okay";
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun	panel@0 {
234*4882a593Smuzhiyun		status = "okay";
235*4882a593Smuzhiyun		compatible = "simple-panel-dsi";
236*4882a593Smuzhiyun		reg = <0>;
237*4882a593Smuzhiyun		backlight = <&backlight>;
238*4882a593Smuzhiyun		power-supply=<&vccsys_lcd>;
239*4882a593Smuzhiyun		reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
240*4882a593Smuzhiyun		enable-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>;
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun		reset-delay-ms = <60>;
243*4882a593Smuzhiyun		enable-delay-ms = <60>;
244*4882a593Smuzhiyun		prepare-delay-ms = <60>;
245*4882a593Smuzhiyun		unprepare-delay-ms = <60>;
246*4882a593Smuzhiyun		disable-delay-ms = <60>;
247*4882a593Smuzhiyun		dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
248*4882a593Smuzhiyun			MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
249*4882a593Smuzhiyun		dsi,format = <MIPI_DSI_FMT_RGB888>;
250*4882a593Smuzhiyun		dsi,lanes  = <4>;
251*4882a593Smuzhiyun		panel-init-sequence = [
252*4882a593Smuzhiyun			23 00 02 FE 21
253*4882a593Smuzhiyun			23 00 02 04 00
254*4882a593Smuzhiyun			23 00 02 00 64
255*4882a593Smuzhiyun			23 00 02 2A 00
256*4882a593Smuzhiyun			23 00 02 26 64
257*4882a593Smuzhiyun			23 00 02 54 00
258*4882a593Smuzhiyun			23 00 02 50 64
259*4882a593Smuzhiyun			23 00 02 7B 00
260*4882a593Smuzhiyun			23 00 02 77 64
261*4882a593Smuzhiyun			23 00 02 A2 00
262*4882a593Smuzhiyun			23 00 02 9D 64
263*4882a593Smuzhiyun			23 00 02 C9 00
264*4882a593Smuzhiyun			23 00 02 C5 64
265*4882a593Smuzhiyun			23 00 02 01 71
266*4882a593Smuzhiyun			23 00 02 27 71
267*4882a593Smuzhiyun			23 00 02 51 71
268*4882a593Smuzhiyun			23 00 02 78 71
269*4882a593Smuzhiyun			23 00 02 9E 71
270*4882a593Smuzhiyun			23 00 02 C6 71
271*4882a593Smuzhiyun			23 00 02 02 89
272*4882a593Smuzhiyun			23 00 02 28 89
273*4882a593Smuzhiyun			23 00 02 52 89
274*4882a593Smuzhiyun			23 00 02 79 89
275*4882a593Smuzhiyun			23 00 02 9F 89
276*4882a593Smuzhiyun			23 00 02 C7 89
277*4882a593Smuzhiyun			23 00 02 03 9E
278*4882a593Smuzhiyun			23 00 02 29 9E
279*4882a593Smuzhiyun			23 00 02 53 9E
280*4882a593Smuzhiyun			23 00 02 7A 9E
281*4882a593Smuzhiyun			23 00 02 A0 9E
282*4882a593Smuzhiyun			23 00 02 C8 9E
283*4882a593Smuzhiyun			23 00 02 09 00
284*4882a593Smuzhiyun			23 00 02 05 B0
285*4882a593Smuzhiyun			23 00 02 31 00
286*4882a593Smuzhiyun			23 00 02 2B B0
287*4882a593Smuzhiyun			23 00 02 5A 00
288*4882a593Smuzhiyun			23 00 02 55 B0
289*4882a593Smuzhiyun			23 00 02 80 00
290*4882a593Smuzhiyun			23 00 02 7C B0
291*4882a593Smuzhiyun			23 00 02 A7 00
292*4882a593Smuzhiyun			23 00 02 A3 B0
293*4882a593Smuzhiyun			23 00 02 CE 00
294*4882a593Smuzhiyun			23 00 02 CA B0
295*4882a593Smuzhiyun			23 00 02 06 C0
296*4882a593Smuzhiyun			23 00 02 2D C0
297*4882a593Smuzhiyun			23 00 02 56 C0
298*4882a593Smuzhiyun			23 00 02 7D C0
299*4882a593Smuzhiyun			23 00 02 A4 C0
300*4882a593Smuzhiyun			23 00 02 CB C0
301*4882a593Smuzhiyun			23 00 02 07 CF
302*4882a593Smuzhiyun			23 00 02 2F CF
303*4882a593Smuzhiyun			23 00 02 58 CF
304*4882a593Smuzhiyun			23 00 02 7E CF
305*4882a593Smuzhiyun			23 00 02 A5 CF
306*4882a593Smuzhiyun			23 00 02 CC CF
307*4882a593Smuzhiyun			23 00 02 08 DD
308*4882a593Smuzhiyun			23 00 02 30 DD
309*4882a593Smuzhiyun			23 00 02 59 DD
310*4882a593Smuzhiyun			23 00 02 7F DD
311*4882a593Smuzhiyun			23 00 02 A6 DD
312*4882a593Smuzhiyun			23 00 02 CD DD
313*4882a593Smuzhiyun			23 00 02 0E 15
314*4882a593Smuzhiyun			23 00 02 0A E9
315*4882a593Smuzhiyun			23 00 02 36 15
316*4882a593Smuzhiyun			23 00 02 32 E9
317*4882a593Smuzhiyun			23 00 02 5F 15
318*4882a593Smuzhiyun			23 00 02 5B E9
319*4882a593Smuzhiyun			23 00 02 85 15
320*4882a593Smuzhiyun			23 00 02 81 E9
321*4882a593Smuzhiyun			23 00 02 AD 15
322*4882a593Smuzhiyun			23 00 02 A9 E9
323*4882a593Smuzhiyun			23 00 02 D3 15
324*4882a593Smuzhiyun			23 00 02 CF E9
325*4882a593Smuzhiyun			23 00 02 0B 14
326*4882a593Smuzhiyun			23 00 02 33 14
327*4882a593Smuzhiyun			23 00 02 5C 14
328*4882a593Smuzhiyun			23 00 02 82 14
329*4882a593Smuzhiyun			23 00 02 AA 14
330*4882a593Smuzhiyun			23 00 02 D0 14
331*4882a593Smuzhiyun			23 00 02 0C 36
332*4882a593Smuzhiyun			23 00 02 34 36
333*4882a593Smuzhiyun			23 00 02 5D 36
334*4882a593Smuzhiyun			23 00 02 83 36
335*4882a593Smuzhiyun			23 00 02 AB 36
336*4882a593Smuzhiyun			23 00 02 D1 36
337*4882a593Smuzhiyun			23 00 02 0D 6B
338*4882a593Smuzhiyun			23 00 02 35 6B
339*4882a593Smuzhiyun			23 00 02 5E 6B
340*4882a593Smuzhiyun			23 00 02 84 6B
341*4882a593Smuzhiyun			23 00 02 AC 6B
342*4882a593Smuzhiyun			23 00 02 D2 6B
343*4882a593Smuzhiyun			23 00 02 13 5A
344*4882a593Smuzhiyun			23 00 02 0F 94
345*4882a593Smuzhiyun			23 00 02 3B 5A
346*4882a593Smuzhiyun			23 00 02 37 94
347*4882a593Smuzhiyun			23 00 02 64 5A
348*4882a593Smuzhiyun			23 00 02 60 94
349*4882a593Smuzhiyun			23 00 02 8A 5A
350*4882a593Smuzhiyun			23 00 02 86 94
351*4882a593Smuzhiyun			23 00 02 B2 5A
352*4882a593Smuzhiyun			23 00 02 AE 94
353*4882a593Smuzhiyun			23 00 02 D8 5A
354*4882a593Smuzhiyun			23 00 02 D4 94
355*4882a593Smuzhiyun			23 00 02 10 D1
356*4882a593Smuzhiyun			23 00 02 38 D1
357*4882a593Smuzhiyun			23 00 02 61 D1
358*4882a593Smuzhiyun			23 00 02 87 D1
359*4882a593Smuzhiyun			23 00 02 AF D1
360*4882a593Smuzhiyun			23 00 02 D5 D1
361*4882a593Smuzhiyun			23 00 02 11 04
362*4882a593Smuzhiyun			23 00 02 39 04
363*4882a593Smuzhiyun			23 00 02 62 04
364*4882a593Smuzhiyun			23 00 02 88 04
365*4882a593Smuzhiyun			23 00 02 B0 04
366*4882a593Smuzhiyun			23 00 02 D6 04
367*4882a593Smuzhiyun			23 00 02 12 05
368*4882a593Smuzhiyun			23 00 02 3A 05
369*4882a593Smuzhiyun			23 00 02 63 05
370*4882a593Smuzhiyun			23 00 02 89 05
371*4882a593Smuzhiyun			23 00 02 B1 05
372*4882a593Smuzhiyun			23 00 02 D7 05
373*4882a593Smuzhiyun			23 00 02 18 AA
374*4882a593Smuzhiyun			23 00 02 14 36
375*4882a593Smuzhiyun			23 00 02 42 AA
376*4882a593Smuzhiyun			23 00 02 3D 36
377*4882a593Smuzhiyun			23 00 02 69 AA
378*4882a593Smuzhiyun			23 00 02 65 36
379*4882a593Smuzhiyun			23 00 02 8F AA
380*4882a593Smuzhiyun			23 00 02 8B 36
381*4882a593Smuzhiyun			23 00 02 B7 AA
382*4882a593Smuzhiyun			23 00 02 B3 36
383*4882a593Smuzhiyun			23 00 02 DD AA
384*4882a593Smuzhiyun			23 00 02 D9 36
385*4882a593Smuzhiyun			23 00 02 15 74
386*4882a593Smuzhiyun			23 00 02 3F 74
387*4882a593Smuzhiyun			23 00 02 66 74
388*4882a593Smuzhiyun			23 00 02 8C 74
389*4882a593Smuzhiyun			23 00 02 B4 74
390*4882a593Smuzhiyun			23 00 02 DA 74
391*4882a593Smuzhiyun			23 00 02 16 9F
392*4882a593Smuzhiyun			23 00 02 40 9F
393*4882a593Smuzhiyun			23 00 02 67 9F
394*4882a593Smuzhiyun			23 00 02 8D 9F
395*4882a593Smuzhiyun			23 00 02 B5 9F
396*4882a593Smuzhiyun			23 00 02 DB 9F
397*4882a593Smuzhiyun			23 00 02 17 DC
398*4882a593Smuzhiyun			23 00 02 41 DC
399*4882a593Smuzhiyun			23 00 02 68 DC
400*4882a593Smuzhiyun			23 00 02 8E DC
401*4882a593Smuzhiyun			23 00 02 B6 DC
402*4882a593Smuzhiyun			23 00 02 DC DC
403*4882a593Smuzhiyun			23 00 02 1D FF
404*4882a593Smuzhiyun			23 00 02 19 03
405*4882a593Smuzhiyun			23 00 02 47 FF
406*4882a593Smuzhiyun			23 00 02 43 03
407*4882a593Smuzhiyun			23 00 02 6E FF
408*4882a593Smuzhiyun			23 00 02 6A 03
409*4882a593Smuzhiyun			23 00 02 94 FF
410*4882a593Smuzhiyun			23 00 02 90 03
411*4882a593Smuzhiyun			23 00 02 BC FF
412*4882a593Smuzhiyun			23 00 02 B8 03
413*4882a593Smuzhiyun			23 00 02 E2 FF
414*4882a593Smuzhiyun			23 00 02 DE 03
415*4882a593Smuzhiyun			23 00 02 1A 35
416*4882a593Smuzhiyun			23 00 02 44 35
417*4882a593Smuzhiyun			23 00 02 6B 35
418*4882a593Smuzhiyun			23 00 02 91 35
419*4882a593Smuzhiyun			23 00 02 B9 35
420*4882a593Smuzhiyun			23 00 02 DF 35
421*4882a593Smuzhiyun			23 00 02 1B 45
422*4882a593Smuzhiyun			23 00 02 45 45
423*4882a593Smuzhiyun			23 00 02 6C 45
424*4882a593Smuzhiyun			23 00 02 92 45
425*4882a593Smuzhiyun			23 00 02 BA 45
426*4882a593Smuzhiyun			23 00 02 E0 45
427*4882a593Smuzhiyun			23 00 02 1C 55
428*4882a593Smuzhiyun			23 00 02 46 55
429*4882a593Smuzhiyun			23 00 02 6D 55
430*4882a593Smuzhiyun			23 00 02 93 55
431*4882a593Smuzhiyun			23 00 02 BB 55
432*4882a593Smuzhiyun			23 00 02 E1 55
433*4882a593Smuzhiyun			23 00 02 22 FF
434*4882a593Smuzhiyun			23 00 02 1E 68
435*4882a593Smuzhiyun			23 00 02 4C FF
436*4882a593Smuzhiyun			23 00 02 48 68
437*4882a593Smuzhiyun			23 00 02 73 FF
438*4882a593Smuzhiyun			23 00 02 6F 68
439*4882a593Smuzhiyun			23 00 02 99 FF
440*4882a593Smuzhiyun			23 00 02 95 68
441*4882a593Smuzhiyun			23 00 02 C1 FF
442*4882a593Smuzhiyun			23 00 02 BD 68
443*4882a593Smuzhiyun			23 00 02 E7 FF
444*4882a593Smuzhiyun			23 00 02 E3 68
445*4882a593Smuzhiyun			23 00 02 1F 7E
446*4882a593Smuzhiyun			23 00 02 49 7E
447*4882a593Smuzhiyun			23 00 02 70 7E
448*4882a593Smuzhiyun			23 00 02 96 7E
449*4882a593Smuzhiyun			23 00 02 BE 7E
450*4882a593Smuzhiyun			23 00 02 E4 7E
451*4882a593Smuzhiyun			23 00 02 20 97
452*4882a593Smuzhiyun			23 00 02 4A 97
453*4882a593Smuzhiyun			23 00 02 71 97
454*4882a593Smuzhiyun			23 00 02 97 97
455*4882a593Smuzhiyun			23 00 02 BF 97
456*4882a593Smuzhiyun			23 00 02 E5 97
457*4882a593Smuzhiyun			23 00 02 21 B5
458*4882a593Smuzhiyun			23 00 02 4B B5
459*4882a593Smuzhiyun			23 00 02 72 B5
460*4882a593Smuzhiyun			23 00 02 98 B5
461*4882a593Smuzhiyun			23 00 02 C0 B5
462*4882a593Smuzhiyun			23 00 02 E6 B5
463*4882a593Smuzhiyun			23 00 02 25 F0
464*4882a593Smuzhiyun			23 00 02 23 E8
465*4882a593Smuzhiyun			23 00 02 4F F0
466*4882a593Smuzhiyun			23 00 02 4D E8
467*4882a593Smuzhiyun			23 00 02 76 F0
468*4882a593Smuzhiyun			23 00 02 74 E8
469*4882a593Smuzhiyun			23 00 02 9C F0
470*4882a593Smuzhiyun			23 00 02 9A E8
471*4882a593Smuzhiyun			23 00 02 C4 F0
472*4882a593Smuzhiyun			23 00 02 C2 E8
473*4882a593Smuzhiyun			23 00 02 EA F0
474*4882a593Smuzhiyun			23 00 02 E8 E8
475*4882a593Smuzhiyun			23 00 02 24 FF
476*4882a593Smuzhiyun			23 00 02 4E FF
477*4882a593Smuzhiyun			23 00 02 75 FF
478*4882a593Smuzhiyun			23 00 02 9B FF
479*4882a593Smuzhiyun			23 00 02 C3 FF
480*4882a593Smuzhiyun			23 00 02 E9 FF
481*4882a593Smuzhiyun			23 00 02 FE 3D
482*4882a593Smuzhiyun			23 00 02 00 04
483*4882a593Smuzhiyun			23 00 02 FE 23
484*4882a593Smuzhiyun			23 00 02 08 82
485*4882a593Smuzhiyun			23 00 02 0A 00
486*4882a593Smuzhiyun			23 00 02 0B 00
487*4882a593Smuzhiyun			23 00 02 0C 01
488*4882a593Smuzhiyun			23 00 02 16 00
489*4882a593Smuzhiyun			23 00 02 18 02
490*4882a593Smuzhiyun			23 00 02 1B 04
491*4882a593Smuzhiyun			23 00 02 19 04
492*4882a593Smuzhiyun			23 00 02 1C 81
493*4882a593Smuzhiyun			23 00 02 1F 00
494*4882a593Smuzhiyun			23 00 02 20 03
495*4882a593Smuzhiyun			23 00 02 23 04
496*4882a593Smuzhiyun			23 00 02 21 01
497*4882a593Smuzhiyun			23 00 02 54 63
498*4882a593Smuzhiyun			23 00 02 55 54
499*4882a593Smuzhiyun			23 00 02 6E 45
500*4882a593Smuzhiyun			23 00 02 6D 36
501*4882a593Smuzhiyun			23 00 02 FE 3D
502*4882a593Smuzhiyun			23 00 02 55 78
503*4882a593Smuzhiyun			23 00 02 FE 20
504*4882a593Smuzhiyun			23 00 02 26 30
505*4882a593Smuzhiyun			23 00 02 FE 3D
506*4882a593Smuzhiyun			23 00 02 20 71
507*4882a593Smuzhiyun			23 00 02 50 8F
508*4882a593Smuzhiyun			23 00 02 51 8F
509*4882a593Smuzhiyun			23 00 02 FE 00
510*4882a593Smuzhiyun			23 00 02 35 00
511*4882a593Smuzhiyun			05 78 01 11
512*4882a593Smuzhiyun			05 1E 01 29
513*4882a593Smuzhiyun		];
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun		panel-exit-sequence = [
516*4882a593Smuzhiyun			05 00 01 28
517*4882a593Smuzhiyun			05 00 01 10
518*4882a593Smuzhiyun		];
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun		disp_timings0: display-timings {
521*4882a593Smuzhiyun			native-mode = <&dsi_timing0>;
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun			dsi_timing0: timing0 {
524*4882a593Smuzhiyun				clock-frequency = <132000000>;
525*4882a593Smuzhiyun				hactive = <1080>;
526*4882a593Smuzhiyun				vactive = <1920>;
527*4882a593Smuzhiyun				hfront-porch = <15>;
528*4882a593Smuzhiyun				hsync-len = <2>;
529*4882a593Smuzhiyun				hback-porch = <30>;
530*4882a593Smuzhiyun				vfront-porch = <15>;
531*4882a593Smuzhiyun				vsync-len = <2>;
532*4882a593Smuzhiyun				vback-porch = <15>;
533*4882a593Smuzhiyun				hsync-active = <0>;
534*4882a593Smuzhiyun				vsync-active = <0>;
535*4882a593Smuzhiyun				de-active = <0>;
536*4882a593Smuzhiyun				pixelclk-active = <1>;
537*4882a593Smuzhiyun			};
538*4882a593Smuzhiyun		};
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun		ports {
541*4882a593Smuzhiyun			#address-cells = <1>;
542*4882a593Smuzhiyun			#size-cells = <0>;
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun			port@0 {
545*4882a593Smuzhiyun				reg = <0>;
546*4882a593Smuzhiyun				panel_in_dsi: endpoint {
547*4882a593Smuzhiyun					remote-endpoint = <&dsi_out_panel>;
548*4882a593Smuzhiyun				};
549*4882a593Smuzhiyun			};
550*4882a593Smuzhiyun		};
551*4882a593Smuzhiyun	};
552*4882a593Smuzhiyun
553*4882a593Smuzhiyun	ports {
554*4882a593Smuzhiyun		#address-cells = <1>;
555*4882a593Smuzhiyun		#size-cells = <0>;
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun		port@1 {
558*4882a593Smuzhiyun			reg = <1>;
559*4882a593Smuzhiyun			dsi_out_panel: endpoint {
560*4882a593Smuzhiyun				remote-endpoint = <&panel_in_dsi>;
561*4882a593Smuzhiyun			};
562*4882a593Smuzhiyun		};
563*4882a593Smuzhiyun	};
564*4882a593Smuzhiyun};
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun&dsi_in_vp0 {
567*4882a593Smuzhiyun	status = "okay";
568*4882a593Smuzhiyun};
569*4882a593Smuzhiyun
570*4882a593Smuzhiyun&gpu {
571*4882a593Smuzhiyun	mali-supply = <&vdd_gpu>;
572*4882a593Smuzhiyun	status = "okay";
573*4882a593Smuzhiyun};
574*4882a593Smuzhiyun
575*4882a593Smuzhiyun&gpu_opp_table {
576*4882a593Smuzhiyun	/delete-node/ opp-800000000;
577*4882a593Smuzhiyun	/delete-node/ opp-900000000;
578*4882a593Smuzhiyun};
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun&i2c0 {
581*4882a593Smuzhiyun	status = "okay";
582*4882a593Smuzhiyun	clock-frequency = <400000>;
583*4882a593Smuzhiyun
584*4882a593Smuzhiyun	usbc0: fusb302@22 {
585*4882a593Smuzhiyun		compatible = "fcs,fusb302";
586*4882a593Smuzhiyun		reg = <0x22>;
587*4882a593Smuzhiyun		interrupt-parent = <&gpio3>;
588*4882a593Smuzhiyun		interrupts = <RK_PA1 IRQ_TYPE_LEVEL_LOW>;
589*4882a593Smuzhiyun		pinctrl-names = "default";
590*4882a593Smuzhiyun		pinctrl-0 = <&usbc0_int>;
591*4882a593Smuzhiyun		vbus-supply = <&otg_switch>;
592*4882a593Smuzhiyun		status = "okay";
593*4882a593Smuzhiyun
594*4882a593Smuzhiyun		ports {
595*4882a593Smuzhiyun			#address-cells = <1>;
596*4882a593Smuzhiyun			#size-cells = <0>;
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun			port@0 {
599*4882a593Smuzhiyun				reg = <0>;
600*4882a593Smuzhiyun				usbc0_role_sw: endpoint@0 {
601*4882a593Smuzhiyun					remote-endpoint = <&dwc3_role_switch>;
602*4882a593Smuzhiyun				};
603*4882a593Smuzhiyun			};
604*4882a593Smuzhiyun		};
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun		usb_con: connector {
607*4882a593Smuzhiyun			compatible = "usb-c-connector";
608*4882a593Smuzhiyun			label = "USB-C";
609*4882a593Smuzhiyun			data-role = "dual";
610*4882a593Smuzhiyun			power-role = "dual";
611*4882a593Smuzhiyun			try-power-role = "sink";
612*4882a593Smuzhiyun			op-sink-microwatt = <1000000>;
613*4882a593Smuzhiyun			sink-pdos =
614*4882a593Smuzhiyun				<PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
615*4882a593Smuzhiyun			source-pdos =
616*4882a593Smuzhiyun				<PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
617*4882a593Smuzhiyun		};
618*4882a593Smuzhiyun	};
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun	rk817: pmic@20 {
621*4882a593Smuzhiyun		compatible = "rockchip,rk817";
622*4882a593Smuzhiyun		reg = <0x20>;
623*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
624*4882a593Smuzhiyun		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun		pinctrl-names = "default", "pmic-sleep",
627*4882a593Smuzhiyun			"pmic-power-off", "pmic-reset";
628*4882a593Smuzhiyun		pinctrl-0 = <&pmic_int>;
629*4882a593Smuzhiyun		pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
630*4882a593Smuzhiyun		pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
631*4882a593Smuzhiyun		pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>;
632*4882a593Smuzhiyun		rockchip,system-power-controller;
633*4882a593Smuzhiyun		wakeup-source;
634*4882a593Smuzhiyun		#clock-cells = <1>;
635*4882a593Smuzhiyun		clock-output-names = "rk808-clkout1", "rk808-clkout2";
636*4882a593Smuzhiyun		/* 1: rst regs (default in codes), 0: rst the pmic */
637*4882a593Smuzhiyun		pmic-reset-func = <0>;
638*4882a593Smuzhiyun		not-save-power-en = <1>;
639*4882a593Smuzhiyun		vcc1-supply = <&vcc_sys>;
640*4882a593Smuzhiyun		vcc2-supply = <&vcc_sys>;
641*4882a593Smuzhiyun		vcc3-supply = <&vcc_sys>;
642*4882a593Smuzhiyun		vcc4-supply = <&vcc_sys>;
643*4882a593Smuzhiyun		vcc5-supply = <&vcc_sys>;
644*4882a593Smuzhiyun		vcc6-supply = <&vcc_sys>;
645*4882a593Smuzhiyun		vcc7-supply = <&vcc_sys>;
646*4882a593Smuzhiyun		vcc8-supply = <&vcc_sys>;
647*4882a593Smuzhiyun		vcc9-supply = <&dcdc_boost>;
648*4882a593Smuzhiyun		pwrkey {
649*4882a593Smuzhiyun			status = "okay";
650*4882a593Smuzhiyun		};
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun		pinctrl_rk8xx: pinctrl_rk8xx {
653*4882a593Smuzhiyun			gpio-controller;
654*4882a593Smuzhiyun			#gpio-cells = <2>;
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun			rk817_slppin_null: rk817_slppin_null {
657*4882a593Smuzhiyun				pins = "gpio_slp";
658*4882a593Smuzhiyun				function = "pin_fun0";
659*4882a593Smuzhiyun			};
660*4882a593Smuzhiyun
661*4882a593Smuzhiyun			rk817_slppin_slp: rk817_slppin_slp {
662*4882a593Smuzhiyun				pins = "gpio_slp";
663*4882a593Smuzhiyun				function = "pin_fun1";
664*4882a593Smuzhiyun			};
665*4882a593Smuzhiyun
666*4882a593Smuzhiyun			rk817_slppin_pwrdn: rk817_slppin_pwrdn {
667*4882a593Smuzhiyun				pins = "gpio_slp";
668*4882a593Smuzhiyun				function = "pin_fun2";
669*4882a593Smuzhiyun			};
670*4882a593Smuzhiyun
671*4882a593Smuzhiyun			rk817_slppin_rst: rk817_slppin_rst {
672*4882a593Smuzhiyun				pins = "gpio_slp";
673*4882a593Smuzhiyun				function = "pin_fun3";
674*4882a593Smuzhiyun			};
675*4882a593Smuzhiyun		};
676*4882a593Smuzhiyun
677*4882a593Smuzhiyun		regulators {
678*4882a593Smuzhiyun			vdda_0v9: vdd_logic: DCDC_REG1 {
679*4882a593Smuzhiyun				regulator-always-on;
680*4882a593Smuzhiyun				regulator-boot-on;
681*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
682*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
683*4882a593Smuzhiyun				regulator-init-microvolt = <900000>;
684*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
685*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
686*4882a593Smuzhiyun				regulator-name = "vdd_logic";
687*4882a593Smuzhiyun				regulator-state-mem {
688*4882a593Smuzhiyun					regulator-off-in-suspend;
689*4882a593Smuzhiyun					regulator-suspend-microvolt = <900000>;
690*4882a593Smuzhiyun				};
691*4882a593Smuzhiyun			};
692*4882a593Smuzhiyun
693*4882a593Smuzhiyun			vdd_npu: vdd_gpu: vdd_cpu: DCDC_REG2 {
694*4882a593Smuzhiyun				regulator-always-on;
695*4882a593Smuzhiyun				regulator-boot-on;
696*4882a593Smuzhiyun				regulator-min-microvolt = <825000>;
697*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
698*4882a593Smuzhiyun				regulator-init-microvolt = <900000>;
699*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
700*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
701*4882a593Smuzhiyun				regulator-name = "vdd_cpu";
702*4882a593Smuzhiyun				regulator-state-mem {
703*4882a593Smuzhiyun					regulator-off-in-suspend;
704*4882a593Smuzhiyun				};
705*4882a593Smuzhiyun			};
706*4882a593Smuzhiyun
707*4882a593Smuzhiyun			vcc_1v8: DCDC_REG3 {
708*4882a593Smuzhiyun				regulator-always-on;
709*4882a593Smuzhiyun				regulator-boot-on;
710*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
711*4882a593Smuzhiyun				regulator-name = "vcc_1v8";
712*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
713*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
714*4882a593Smuzhiyun				regulator-state-mem {
715*4882a593Smuzhiyun					regulator-off-in-suspend;
716*4882a593Smuzhiyun				};
717*4882a593Smuzhiyun			};
718*4882a593Smuzhiyun
719*4882a593Smuzhiyun			vcc3v3_sys: DCDC_REG4 {
720*4882a593Smuzhiyun				regulator-always-on;
721*4882a593Smuzhiyun				regulator-boot-on;
722*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
723*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
724*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
725*4882a593Smuzhiyun				regulator-name = "vcc3v3_sys";
726*4882a593Smuzhiyun				regulator-state-mem {
727*4882a593Smuzhiyun					regulator-on-in-suspend;
728*4882a593Smuzhiyun				};
729*4882a593Smuzhiyun			};
730*4882a593Smuzhiyun
731*4882a593Smuzhiyun			vcc_ldo1: LDO_REG1 {
732*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
733*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
734*4882a593Smuzhiyun				regulator-name = "vcc_ldo1";
735*4882a593Smuzhiyun				regulator-state-mem {
736*4882a593Smuzhiyun					regulator-off-in-suspend;
737*4882a593Smuzhiyun				};
738*4882a593Smuzhiyun			};
739*4882a593Smuzhiyun
740*4882a593Smuzhiyun			vcc1v5_dvp: LDO_REG2 {
741*4882a593Smuzhiyun				regulator-min-microvolt = <1500000>;
742*4882a593Smuzhiyun				regulator-max-microvolt = <1500000>;
743*4882a593Smuzhiyun				regulator-name = "vcc1v5_dvp";
744*4882a593Smuzhiyun				regulator-state-mem {
745*4882a593Smuzhiyun					regulator-off-in-suspend;
746*4882a593Smuzhiyun				};
747*4882a593Smuzhiyun			};
748*4882a593Smuzhiyun
749*4882a593Smuzhiyun			vdda0v9_pmu: LDO_REG3 {
750*4882a593Smuzhiyun				regulator-always-on;
751*4882a593Smuzhiyun				regulator-boot-on;
752*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
753*4882a593Smuzhiyun				regulator-max-microvolt = <900000>;
754*4882a593Smuzhiyun				regulator-name = "vdda0v9_pmu";
755*4882a593Smuzhiyun				regulator-state-mem {
756*4882a593Smuzhiyun					regulator-on-in-suspend;
757*4882a593Smuzhiyun					regulator-suspend-microvolt = <900000>;
758*4882a593Smuzhiyun				};
759*4882a593Smuzhiyun			};
760*4882a593Smuzhiyun
761*4882a593Smuzhiyun			vccio_acodec: LDO_REG4 {
762*4882a593Smuzhiyun				regulator-always-on;
763*4882a593Smuzhiyun				regulator-boot-on;
764*4882a593Smuzhiyun				regulator-min-microvolt = <3000000>;
765*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
766*4882a593Smuzhiyun				regulator-name = "vccio_acodec";
767*4882a593Smuzhiyun				regulator-state-mem {
768*4882a593Smuzhiyun					regulator-off-in-suspend;
769*4882a593Smuzhiyun				};
770*4882a593Smuzhiyun			};
771*4882a593Smuzhiyun
772*4882a593Smuzhiyun			vcc3v3_lcd: LDO_REG5 {
773*4882a593Smuzhiyun				regulator-min-microvolt = <3000000>;
774*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
775*4882a593Smuzhiyun				regulator-name = "vcc3v3_lcd";
776*4882a593Smuzhiyun				regulator-state-mem {
777*4882a593Smuzhiyun					regulator-off-in-suspend;
778*4882a593Smuzhiyun				};
779*4882a593Smuzhiyun			};
780*4882a593Smuzhiyun
781*4882a593Smuzhiyun			vcc3v3_pmu: LDO_REG6 {
782*4882a593Smuzhiyun				regulator-always-on;
783*4882a593Smuzhiyun				regulator-boot-on;
784*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
785*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
786*4882a593Smuzhiyun				regulator-name = "vcc3v3_pmu";
787*4882a593Smuzhiyun				regulator-state-mem {
788*4882a593Smuzhiyun					regulator-on-in-suspend;
789*4882a593Smuzhiyun					regulator-suspend-microvolt = <3000000>;
790*4882a593Smuzhiyun				};
791*4882a593Smuzhiyun			};
792*4882a593Smuzhiyun
793*4882a593Smuzhiyun			vcc_ldo7: LDO_REG7 {
794*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
795*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
796*4882a593Smuzhiyun				regulator-name = "vcc_ldo7";
797*4882a593Smuzhiyun				regulator-state-mem {
798*4882a593Smuzhiyun					regulator-off-in-suspend;
799*4882a593Smuzhiyun				};
800*4882a593Smuzhiyun			};
801*4882a593Smuzhiyun
802*4882a593Smuzhiyun			vcc1v8_dvp: LDO_REG8 {
803*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
804*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
805*4882a593Smuzhiyun				regulator-name = "vcc1v8_dvp";
806*4882a593Smuzhiyun				regulator-state-mem {
807*4882a593Smuzhiyun					regulator-off-in-suspend;
808*4882a593Smuzhiyun				};
809*4882a593Smuzhiyun			};
810*4882a593Smuzhiyun
811*4882a593Smuzhiyun			vcc2v8_dvp: LDO_REG9 {
812*4882a593Smuzhiyun				regulator-min-microvolt = <2800000>;
813*4882a593Smuzhiyun				regulator-max-microvolt = <2800000>;
814*4882a593Smuzhiyun				regulator-name = "vcc2v8_dvp";
815*4882a593Smuzhiyun				regulator-state-mem {
816*4882a593Smuzhiyun					regulator-off-in-suspend;
817*4882a593Smuzhiyun				};
818*4882a593Smuzhiyun			};
819*4882a593Smuzhiyun
820*4882a593Smuzhiyun			dcdc_boost: BOOST {
821*4882a593Smuzhiyun				regulator-always-on;
822*4882a593Smuzhiyun				regulator-boot-on;
823*4882a593Smuzhiyun				regulator-min-microvolt = <5000000>;
824*4882a593Smuzhiyun				regulator-max-microvolt = <5000000>;
825*4882a593Smuzhiyun				regulator-name = "boost";
826*4882a593Smuzhiyun				regulator-state-mem {
827*4882a593Smuzhiyun					regulator-off-in-suspend;
828*4882a593Smuzhiyun				};
829*4882a593Smuzhiyun			};
830*4882a593Smuzhiyun
831*4882a593Smuzhiyun			otg_switch: OTG_SWITCH {
832*4882a593Smuzhiyun				regulator-name = "otg_switch";
833*4882a593Smuzhiyun				regulator-state-mem {
834*4882a593Smuzhiyun					regulator-off-in-suspend;
835*4882a593Smuzhiyun				};
836*4882a593Smuzhiyun			};
837*4882a593Smuzhiyun		};
838*4882a593Smuzhiyun
839*4882a593Smuzhiyun		battery {
840*4882a593Smuzhiyun			compatible = "rk817,battery";
841*4882a593Smuzhiyun			ntc_table = <42450 40570 38780 37080 35460 33930
842*4882a593Smuzhiyun				     32460 31070 29750 28490 27280 26140
843*4882a593Smuzhiyun				     25050 24010 23020 22070 21170 20310
844*4882a593Smuzhiyun				     19490 18710 17960 17250 16570 15910
845*4882a593Smuzhiyun				     15290 14700 14130 13590 13070 12570
846*4882a593Smuzhiyun				     12090 11640 11200 10780 10380 10000
847*4882a593Smuzhiyun				     9633 9282 8945 8622 8312 8015 7730
848*4882a593Smuzhiyun				     7456 7194 6942 6700 6468 6245 6031
849*4882a593Smuzhiyun				     5826 5628 5438 5255 5080 4911 4749
850*4882a593Smuzhiyun				     4592 4442 4297 4158 4024 3895 3771
851*4882a593Smuzhiyun				     3651 3536 3425 3318 3215 3115 3019
852*4882a593Smuzhiyun				     2927 2837 2751 2668 2588>;
853*4882a593Smuzhiyun				ntc_degree_from = <1 10>;
854*4882a593Smuzhiyun				ocv_table = <3400 3653 3679 3704 3731 3750
855*4882a593Smuzhiyun				     3771 3788 3806 3828 3855 3890
856*4882a593Smuzhiyun				     3943 3993 4043 4095 4149 4206
857*4882a593Smuzhiyun				     4264 4321 4377>;
858*4882a593Smuzhiyun				design_capacity = <1000>;
859*4882a593Smuzhiyun				design_qmax = <1010>;
860*4882a593Smuzhiyun				bat_res = <110>;
861*4882a593Smuzhiyun				sleep_enter_current = <30>;
862*4882a593Smuzhiyun				sleep_exit_current = <30>;
863*4882a593Smuzhiyun				sleep_filter_current = <20>;
864*4882a593Smuzhiyun				power_off_thresd = <3400>;
865*4882a593Smuzhiyun				zero_algorithm_vol = <3000>;
866*4882a593Smuzhiyun				max_soc_offset = <60>;
867*4882a593Smuzhiyun				monitor_sec = <5>;
868*4882a593Smuzhiyun				sample_res = <26>;
869*4882a593Smuzhiyun				virtual_power = <0>;
870*4882a593Smuzhiyun				chrg_finish_cur = <50>;
871*4882a593Smuzhiyun		};
872*4882a593Smuzhiyun
873*4882a593Smuzhiyun		charger {
874*4882a593Smuzhiyun			compatible = "rk817,charger";
875*4882a593Smuzhiyun			min_input_voltage = <4500>;
876*4882a593Smuzhiyun			max_input_current = <2000>;
877*4882a593Smuzhiyun			max_chrg_current = <500>;
878*4882a593Smuzhiyun			max_chrg_voltage = <4400>;
879*4882a593Smuzhiyun			otg5v_suspend_enable = <0>;
880*4882a593Smuzhiyun			chrg_term_mode = <0>;
881*4882a593Smuzhiyun			chrg_finish_cur = <50>;
882*4882a593Smuzhiyun			virtual_power = <0>;
883*4882a593Smuzhiyun			dc_det_adc = <0>;
884*4882a593Smuzhiyun			sample_res = <26>;
885*4882a593Smuzhiyun			extcon = <&u2phy>;
886*4882a593Smuzhiyun			gate_function_disable = <1>;
887*4882a593Smuzhiyun		};
888*4882a593Smuzhiyun
889*4882a593Smuzhiyun		rk817_codec: codec {
890*4882a593Smuzhiyun			#sound-dai-cells = <0>;
891*4882a593Smuzhiyun			compatible = "rockchip,rk817-codec";
892*4882a593Smuzhiyun			clocks = <&mclkout_sai0>;
893*4882a593Smuzhiyun			clock-names = "mclk";
894*4882a593Smuzhiyun			assigned-clocks = <&mclkout_sai0>;
895*4882a593Smuzhiyun			assigned-clock-rates = <12288000>;
896*4882a593Smuzhiyun			pinctrl-names = "default";
897*4882a593Smuzhiyun			pinctrl-0 = <&i2s0m0_mclk>;
898*4882a593Smuzhiyun			hp-volume = <20>;
899*4882a593Smuzhiyun			spk-volume = <3>;
900*4882a593Smuzhiyun			mic-in-differential;
901*4882a593Smuzhiyun			status = "okay";
902*4882a593Smuzhiyun		};
903*4882a593Smuzhiyun	};
904*4882a593Smuzhiyun};
905*4882a593Smuzhiyun
906*4882a593Smuzhiyun&i2c2 {
907*4882a593Smuzhiyun	status = "okay";
908*4882a593Smuzhiyun	clock-frequency = <400000>;
909*4882a593Smuzhiyun
910*4882a593Smuzhiyun	gt1x: gt1x@14 {
911*4882a593Smuzhiyun		compatible = "goodix,gt1x";
912*4882a593Smuzhiyun		reg = <0x14>;
913*4882a593Smuzhiyun		pinctrl-names = "default";
914*4882a593Smuzhiyun		pinctrl-0 = <&touch_gpio>;
915*4882a593Smuzhiyun		goodix,rst-gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
916*4882a593Smuzhiyun		goodix,irq-gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>;
917*4882a593Smuzhiyun
918*4882a593Smuzhiyun		power-supply = <&vcc3v3_lcd>;
919*4882a593Smuzhiyun	};
920*4882a593Smuzhiyun};
921*4882a593Smuzhiyun
922*4882a593Smuzhiyun&i2c5 {
923*4882a593Smuzhiyun	status = "okay";
924*4882a593Smuzhiyun	clock-frequency = <400000>;
925*4882a593Smuzhiyun
926*4882a593Smuzhiyun	sc031gs: sc031gs@30 {
927*4882a593Smuzhiyun		status = "okay";
928*4882a593Smuzhiyun		compatible = "smartsens,sc031gs";
929*4882a593Smuzhiyun		reg = <0x30>;
930*4882a593Smuzhiyun		clocks = <&cru CLK_CAM0_OUT2IO>;
931*4882a593Smuzhiyun		clock-names = "xvclk";
932*4882a593Smuzhiyun		pinctrl-names = "default";
933*4882a593Smuzhiyun		pinctrl-0 = <&camm0_clk0_out>;
934*4882a593Smuzhiyun		pwdn-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
935*4882a593Smuzhiyun		avdd-supply = <&vcc2v8_dvp>;
936*4882a593Smuzhiyun		dovdd-supply = <&vcc1v8_dvp>;
937*4882a593Smuzhiyun		dvdd-supply = <&vcc1v5_dvp>;
938*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
939*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
940*4882a593Smuzhiyun		rockchip,camera-module-name = "default";
941*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "default";
942*4882a593Smuzhiyun
943*4882a593Smuzhiyun		port {
944*4882a593Smuzhiyun			sc031gs_out: endpoint {
945*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ucam0>;
946*4882a593Smuzhiyun				data-lanes = <1>;
947*4882a593Smuzhiyun			};
948*4882a593Smuzhiyun		};
949*4882a593Smuzhiyun	};
950*4882a593Smuzhiyun};
951*4882a593Smuzhiyun
952*4882a593Smuzhiyun&jpegd {
953*4882a593Smuzhiyun	status = "okay";
954*4882a593Smuzhiyun};
955*4882a593Smuzhiyun
956*4882a593Smuzhiyun&jpegd_mmu {
957*4882a593Smuzhiyun	status = "okay";
958*4882a593Smuzhiyun};
959*4882a593Smuzhiyun
960*4882a593Smuzhiyun&mipi0_csi2 {
961*4882a593Smuzhiyun	status = "okay";
962*4882a593Smuzhiyun
963*4882a593Smuzhiyun	ports {
964*4882a593Smuzhiyun		#address-cells = <1>;
965*4882a593Smuzhiyun		#size-cells = <0>;
966*4882a593Smuzhiyun
967*4882a593Smuzhiyun		port@0 {
968*4882a593Smuzhiyun			reg = <0>;
969*4882a593Smuzhiyun			#address-cells = <1>;
970*4882a593Smuzhiyun			#size-cells = <0>;
971*4882a593Smuzhiyun
972*4882a593Smuzhiyun			mipi0_csi2_input: endpoint@1 {
973*4882a593Smuzhiyun				reg = <1>;
974*4882a593Smuzhiyun				remote-endpoint = <&csidcphy0_out>;
975*4882a593Smuzhiyun			};
976*4882a593Smuzhiyun		};
977*4882a593Smuzhiyun
978*4882a593Smuzhiyun		port@1 {
979*4882a593Smuzhiyun			reg = <1>;
980*4882a593Smuzhiyun			#address-cells = <1>;
981*4882a593Smuzhiyun			#size-cells = <0>;
982*4882a593Smuzhiyun
983*4882a593Smuzhiyun			mipi0_csi2_output: endpoint@0 {
984*4882a593Smuzhiyun				reg = <0>;
985*4882a593Smuzhiyun				remote-endpoint = <&cif_mipi_in0>;
986*4882a593Smuzhiyun			};
987*4882a593Smuzhiyun		};
988*4882a593Smuzhiyun	};
989*4882a593Smuzhiyun};
990*4882a593Smuzhiyun
991*4882a593Smuzhiyun&mpp_srv {
992*4882a593Smuzhiyun	status = "okay";
993*4882a593Smuzhiyun};
994*4882a593Smuzhiyun
995*4882a593Smuzhiyun&npu_opp_table {
996*4882a593Smuzhiyun	/delete-node/ opp-900000000;
997*4882a593Smuzhiyun	/delete-node/ opp-1000000000;
998*4882a593Smuzhiyun};
999*4882a593Smuzhiyun
1000*4882a593Smuzhiyun&pinctrl {
1001*4882a593Smuzhiyun	led_control {
1002*4882a593Smuzhiyun		scan_key: scan-key {
1003*4882a593Smuzhiyun			rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
1004*4882a593Smuzhiyun		};
1005*4882a593Smuzhiyun	};
1006*4882a593Smuzhiyun
1007*4882a593Smuzhiyun	touch {
1008*4882a593Smuzhiyun		touch_gpio: touch-gpio {
1009*4882a593Smuzhiyun			rockchip,pins =
1010*4882a593Smuzhiyun				<0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>,
1011*4882a593Smuzhiyun				<0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
1012*4882a593Smuzhiyun		};
1013*4882a593Smuzhiyun	};
1014*4882a593Smuzhiyun
1015*4882a593Smuzhiyun	sdio-pwrseq {
1016*4882a593Smuzhiyun		wifi_enable_l: wifi-enable-l {
1017*4882a593Smuzhiyun			rockchip,pins = <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
1018*4882a593Smuzhiyun		};
1019*4882a593Smuzhiyun	};
1020*4882a593Smuzhiyun
1021*4882a593Smuzhiyun	usb {
1022*4882a593Smuzhiyun		usbc0_int: usbc0-int {
1023*4882a593Smuzhiyun			rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
1024*4882a593Smuzhiyun		};
1025*4882a593Smuzhiyun	};
1026*4882a593Smuzhiyun
1027*4882a593Smuzhiyun	wireless-wlan {
1028*4882a593Smuzhiyun		wifi_host_wake_irq: wifi-host-wake-irq {
1029*4882a593Smuzhiyun			rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_down>;
1030*4882a593Smuzhiyun		};
1031*4882a593Smuzhiyun	};
1032*4882a593Smuzhiyun
1033*4882a593Smuzhiyun	wireless-bluetooth {
1034*4882a593Smuzhiyun		uart1_gpios: uart1-gpios {
1035*4882a593Smuzhiyun			rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
1036*4882a593Smuzhiyun		};
1037*4882a593Smuzhiyun	};
1038*4882a593Smuzhiyun};
1039*4882a593Smuzhiyun
1040*4882a593Smuzhiyun&pwm12 {
1041*4882a593Smuzhiyun	status = "okay";
1042*4882a593Smuzhiyun	pinctrl-0 = <&pwm12m1_pins>;
1043*4882a593Smuzhiyun};
1044*4882a593Smuzhiyun
1045*4882a593Smuzhiyun&rga2 {
1046*4882a593Smuzhiyun	status = "okay";
1047*4882a593Smuzhiyun};
1048*4882a593Smuzhiyun
1049*4882a593Smuzhiyun&rga2_mmu {
1050*4882a593Smuzhiyun	status = "okay";
1051*4882a593Smuzhiyun};
1052*4882a593Smuzhiyun
1053*4882a593Smuzhiyun&rkcif {
1054*4882a593Smuzhiyun	status = "okay";
1055*4882a593Smuzhiyun};
1056*4882a593Smuzhiyun
1057*4882a593Smuzhiyun&rkcif_mipi_lvds {
1058*4882a593Smuzhiyun	status = "okay";
1059*4882a593Smuzhiyun
1060*4882a593Smuzhiyun	port {
1061*4882a593Smuzhiyun		cif_mipi_in0: endpoint {
1062*4882a593Smuzhiyun			remote-endpoint = <&mipi0_csi2_output>;
1063*4882a593Smuzhiyun		};
1064*4882a593Smuzhiyun	};
1065*4882a593Smuzhiyun};
1066*4882a593Smuzhiyun
1067*4882a593Smuzhiyun&rkcif_mipi_lvds_sditf {
1068*4882a593Smuzhiyun	status = "okay";
1069*4882a593Smuzhiyun
1070*4882a593Smuzhiyun	port {
1071*4882a593Smuzhiyun		mipi_lvds_sditf: endpoint {
1072*4882a593Smuzhiyun			remote-endpoint = <&isp_vir0>;
1073*4882a593Smuzhiyun		};
1074*4882a593Smuzhiyun	};
1075*4882a593Smuzhiyun};
1076*4882a593Smuzhiyun
1077*4882a593Smuzhiyun&rkcif_mmu {
1078*4882a593Smuzhiyun	status = "okay";
1079*4882a593Smuzhiyun};
1080*4882a593Smuzhiyun
1081*4882a593Smuzhiyun&rkisp {
1082*4882a593Smuzhiyun	status = "okay";
1083*4882a593Smuzhiyun};
1084*4882a593Smuzhiyun
1085*4882a593Smuzhiyun&rkisp_mmu {
1086*4882a593Smuzhiyun	status = "okay";
1087*4882a593Smuzhiyun};
1088*4882a593Smuzhiyun
1089*4882a593Smuzhiyun&rkisp_vir0 {
1090*4882a593Smuzhiyun	status = "okay";
1091*4882a593Smuzhiyun
1092*4882a593Smuzhiyun	port {
1093*4882a593Smuzhiyun		#address-cells = <1>;
1094*4882a593Smuzhiyun		#size-cells = <0>;
1095*4882a593Smuzhiyun
1096*4882a593Smuzhiyun		isp_vir0: endpoint@0 {
1097*4882a593Smuzhiyun			reg = <0>;
1098*4882a593Smuzhiyun			remote-endpoint = <&mipi_lvds_sditf>;
1099*4882a593Smuzhiyun		};
1100*4882a593Smuzhiyun	};
1101*4882a593Smuzhiyun};
1102*4882a593Smuzhiyun
1103*4882a593Smuzhiyun&rknpu {
1104*4882a593Smuzhiyun	rknpu-supply = <&vdd_npu>;
1105*4882a593Smuzhiyun	status = "okay";
1106*4882a593Smuzhiyun};
1107*4882a593Smuzhiyun
1108*4882a593Smuzhiyun&rknpu_mmu {
1109*4882a593Smuzhiyun	status = "okay";
1110*4882a593Smuzhiyun};
1111*4882a593Smuzhiyun
1112*4882a593Smuzhiyun&rkvdec {
1113*4882a593Smuzhiyun	status = "okay";
1114*4882a593Smuzhiyun};
1115*4882a593Smuzhiyun
1116*4882a593Smuzhiyun&rkvdec_mmu {
1117*4882a593Smuzhiyun	status = "okay";
1118*4882a593Smuzhiyun};
1119*4882a593Smuzhiyun
1120*4882a593Smuzhiyun&rockchip_suspend {
1121*4882a593Smuzhiyun	status = "okay";
1122*4882a593Smuzhiyun
1123*4882a593Smuzhiyun	rockchip,sleep-mode-config = <
1124*4882a593Smuzhiyun		(0
1125*4882a593Smuzhiyun		| RKPM_SLP_ULTRA_MODE
1126*4882a593Smuzhiyun		| RKPM_SLP_PMIC_LP
1127*4882a593Smuzhiyun		| RKPM_SLP_HW_PLLS_OFF
1128*4882a593Smuzhiyun		| RKPM_SLP_PMUALIVE_32K
1129*4882a593Smuzhiyun		| RKPM_SLP_OSC_DIS
1130*4882a593Smuzhiyun		| RKPM_SLP_32K_PVTM
1131*4882a593Smuzhiyun		)
1132*4882a593Smuzhiyun	>;
1133*4882a593Smuzhiyun};
1134*4882a593Smuzhiyun
1135*4882a593Smuzhiyun&route_dsi {
1136*4882a593Smuzhiyun	status = "okay";
1137*4882a593Smuzhiyun};
1138*4882a593Smuzhiyun
1139*4882a593Smuzhiyun&sai0 {
1140*4882a593Smuzhiyun	status = "okay";
1141*4882a593Smuzhiyun	pinctrl-names = "default";
1142*4882a593Smuzhiyun	pinctrl-0 = <&i2s0m0_lrck
1143*4882a593Smuzhiyun		     &i2s0m0_sclk
1144*4882a593Smuzhiyun		     &i2s0m0_sdi0
1145*4882a593Smuzhiyun		     &i2s0m0_sdo0>;
1146*4882a593Smuzhiyun};
1147*4882a593Smuzhiyun
1148*4882a593Smuzhiyun&saradc0 {
1149*4882a593Smuzhiyun	status = "okay";
1150*4882a593Smuzhiyun	vref-supply = <&vcc_1v8>;
1151*4882a593Smuzhiyun};
1152*4882a593Smuzhiyun
1153*4882a593Smuzhiyun&sdhci {
1154*4882a593Smuzhiyun	bus-width = <8>;
1155*4882a593Smuzhiyun	no-sdio;
1156*4882a593Smuzhiyun	no-sd;
1157*4882a593Smuzhiyun	non-removable;
1158*4882a593Smuzhiyun	max-frequency = <200000000>;
1159*4882a593Smuzhiyun	mmc-hs400-1_8v;
1160*4882a593Smuzhiyun	mmc-hs400-enhanced-strobe;
1161*4882a593Smuzhiyun	status = "okay";
1162*4882a593Smuzhiyun};
1163*4882a593Smuzhiyun
1164*4882a593Smuzhiyun&sdmmc1 {
1165*4882a593Smuzhiyun	no-sd;
1166*4882a593Smuzhiyun	no-mmc;
1167*4882a593Smuzhiyun	bus-width = <4>;
1168*4882a593Smuzhiyun	disable-wp;
1169*4882a593Smuzhiyun	cap-sd-highspeed;
1170*4882a593Smuzhiyun	cap-sdio-irq;
1171*4882a593Smuzhiyun	mmc-pwrseq = <&sdio_pwrseq>;
1172*4882a593Smuzhiyun	non-removable;
1173*4882a593Smuzhiyun	keep-power-in-suspend;
1174*4882a593Smuzhiyun	pinctrl-names = "default";
1175*4882a593Smuzhiyun	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
1176*4882a593Smuzhiyun	sd-uhs-sdr104;
1177*4882a593Smuzhiyun	status = "disabled";
1178*4882a593Smuzhiyun};
1179*4882a593Smuzhiyun
1180*4882a593Smuzhiyun&tsadc {
1181*4882a593Smuzhiyun	status = "okay";
1182*4882a593Smuzhiyun};
1183*4882a593Smuzhiyun
1184*4882a593Smuzhiyun&u2phy {
1185*4882a593Smuzhiyun	status = "okay";
1186*4882a593Smuzhiyun};
1187*4882a593Smuzhiyun
1188*4882a593Smuzhiyun/* for inno usb2 phy driver probe and set to phy_sus status */
1189*4882a593Smuzhiyun&u2phy_host {
1190*4882a593Smuzhiyun	/delete-property/ phy-supply;
1191*4882a593Smuzhiyun	status = "okay";
1192*4882a593Smuzhiyun};
1193*4882a593Smuzhiyun
1194*4882a593Smuzhiyun&u2phy_otg {
1195*4882a593Smuzhiyun	status = "okay";
1196*4882a593Smuzhiyun	vbus-supply = <&otg_switch>;
1197*4882a593Smuzhiyun};
1198*4882a593Smuzhiyun
1199*4882a593Smuzhiyun&uart1 {
1200*4882a593Smuzhiyun	status = "okay";
1201*4882a593Smuzhiyun	pinctrl-names = "default";
1202*4882a593Smuzhiyun	pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
1203*4882a593Smuzhiyun};
1204*4882a593Smuzhiyun
1205*4882a593Smuzhiyun&usbdrd30 {
1206*4882a593Smuzhiyun	status = "okay";
1207*4882a593Smuzhiyun};
1208*4882a593Smuzhiyun
1209*4882a593Smuzhiyun&usbdrd_dwc3 {
1210*4882a593Smuzhiyun	status = "okay";
1211*4882a593Smuzhiyun	dr_mode = "otg";
1212*4882a593Smuzhiyun	maximum-speed = "high-speed";
1213*4882a593Smuzhiyun	phys = <&u2phy_otg>;
1214*4882a593Smuzhiyun	phy-names = "usb2-phy";
1215*4882a593Smuzhiyun	snps,dis_u2_susphy_quirk;
1216*4882a593Smuzhiyun	snps,usb2-lpm-disable;
1217*4882a593Smuzhiyun
1218*4882a593Smuzhiyun	usb-role-switch;
1219*4882a593Smuzhiyun	port {
1220*4882a593Smuzhiyun		#address-cells = <1>;
1221*4882a593Smuzhiyun		#size-cells = <0>;
1222*4882a593Smuzhiyun		dwc3_role_switch: endpoint@0 {
1223*4882a593Smuzhiyun			reg = <0>;
1224*4882a593Smuzhiyun			remote-endpoint = <&usbc0_role_sw>;
1225*4882a593Smuzhiyun		};
1226*4882a593Smuzhiyun	};
1227*4882a593Smuzhiyun};
1228*4882a593Smuzhiyun
1229*4882a593Smuzhiyun&video_phy {
1230*4882a593Smuzhiyun	status = "okay";
1231*4882a593Smuzhiyun};
1232*4882a593Smuzhiyun
1233*4882a593Smuzhiyun&vop {
1234*4882a593Smuzhiyun	status = "okay";
1235*4882a593Smuzhiyun};
1236*4882a593Smuzhiyun
1237*4882a593Smuzhiyun&vop_mmu {
1238*4882a593Smuzhiyun	status = "okay";
1239*4882a593Smuzhiyun};
1240*4882a593Smuzhiyun
1241*4882a593Smuzhiyun&wdt {
1242*4882a593Smuzhiyun	status = "okay";
1243*4882a593Smuzhiyun};
1244