1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun#include "rk3399.dtsi" 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/ { 7*4882a593Smuzhiyun compatible = "rockchip,rk3399pro"; 8*4882a593Smuzhiyun}; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/* Default to enabled since AP talk to NPU part over pcie */ 11*4882a593Smuzhiyun&pcie_phy { 12*4882a593Smuzhiyun status = "okay"; 13*4882a593Smuzhiyun}; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun/* Default to enabled since AP talk to NPU part over pcie */ 16*4882a593Smuzhiyun&pcie0 { 17*4882a593Smuzhiyun ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; 18*4882a593Smuzhiyun num-lanes = <4>; 19*4882a593Smuzhiyun pinctrl-names = "default"; 20*4882a593Smuzhiyun pinctrl-0 = <&pcie_clkreqn_cpm>; 21*4882a593Smuzhiyun status = "okay"; 22*4882a593Smuzhiyun}; 23