xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm64/rockchip/rk3399pro-evb-lp4-v11-linux.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun// Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun/dts-v1/;
5*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
6*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h>
7*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
8*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h>
9*4882a593Smuzhiyun#include <dt-bindings/sensor-dev.h>
10*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h>
11*4882a593Smuzhiyun#include "dt-bindings/usb/pd.h"
12*4882a593Smuzhiyun#include "rk3399pro.dtsi"
13*4882a593Smuzhiyun#include "rk3399-linux.dtsi"
14*4882a593Smuzhiyun#include "rk3399-opp.dtsi"
15*4882a593Smuzhiyun#include "rk3399-vop-clk-set.dtsi"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun/ {
18*4882a593Smuzhiyun	compatible = "rockchip,rk3399pro-evb-v11-linux", "rockchip,rk3399pro";
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun	adc-keys {
21*4882a593Smuzhiyun		compatible = "adc-keys";
22*4882a593Smuzhiyun		io-channels = <&saradc 2>;
23*4882a593Smuzhiyun		io-channel-names = "buttons";
24*4882a593Smuzhiyun		poll-interval = <100>;
25*4882a593Smuzhiyun		keyup-threshold-microvolt = <1800000>;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun		esc-key {
28*4882a593Smuzhiyun			linux,code = <KEY_ESC>;
29*4882a593Smuzhiyun			label = "esc";
30*4882a593Smuzhiyun			press-threshold-microvolt = <1310000>;
31*4882a593Smuzhiyun		};
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun		menu-key {
34*4882a593Smuzhiyun			linux,code = <KEY_MENU>;
35*4882a593Smuzhiyun			label = "menu";
36*4882a593Smuzhiyun			press-threshold-microvolt = <987000>;
37*4882a593Smuzhiyun		};
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun		home-key {
40*4882a593Smuzhiyun			linux,code = <KEY_HOME>;
41*4882a593Smuzhiyun			label = "home";
42*4882a593Smuzhiyun			press-threshold-microvolt = <624000>;
43*4882a593Smuzhiyun		};
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun		vol-down-key {
46*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEDOWN>;
47*4882a593Smuzhiyun			label = "volume down";
48*4882a593Smuzhiyun			press-threshold-microvolt = <300000>;
49*4882a593Smuzhiyun		};
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun		vol-up-key {
52*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
53*4882a593Smuzhiyun			label = "volume up";
54*4882a593Smuzhiyun			press-threshold-microvolt = <17000>;
55*4882a593Smuzhiyun		};
56*4882a593Smuzhiyun	};
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun	backlight: backlight {
59*4882a593Smuzhiyun		compatible = "pwm-backlight";
60*4882a593Smuzhiyun		pwms = <&pwm0 0 25000 0>;
61*4882a593Smuzhiyun		brightness-levels = <
62*4882a593Smuzhiyun			  0  20  20  21  21  22  22  23
63*4882a593Smuzhiyun			 23  24  24  25  25  26  26  27
64*4882a593Smuzhiyun			 27  28  28  29  29  30  30  31
65*4882a593Smuzhiyun			 31  32  32  33  33  34  34  35
66*4882a593Smuzhiyun			 35  36  36  37  37  38  38  39
67*4882a593Smuzhiyun			 40  41  42  43  44  45  46  47
68*4882a593Smuzhiyun			 48  49  50  51  52  53  54  55
69*4882a593Smuzhiyun			 56  57  58  59  60  61  62  63
70*4882a593Smuzhiyun			 64  65  66  67  68  69  70  71
71*4882a593Smuzhiyun			 72  73  74  75  76  77  78  79
72*4882a593Smuzhiyun			 80  81  82  83  84  85  86  87
73*4882a593Smuzhiyun			 88  89  90  91  92  93  94  95
74*4882a593Smuzhiyun			 96  97  98  99 100 101 102 103
75*4882a593Smuzhiyun			104 105 106 107 108 109 110 111
76*4882a593Smuzhiyun			112 113 114 115 116 117 118 119
77*4882a593Smuzhiyun			120 121 122 123 124 125 126 127
78*4882a593Smuzhiyun			128 129 130 131 132 133 134 135
79*4882a593Smuzhiyun			136 137 138 139 140 141 142 143
80*4882a593Smuzhiyun			144 145 146 147 148 149 150 151
81*4882a593Smuzhiyun			152 153 154 155 156 157 158 159
82*4882a593Smuzhiyun			160 161 162 163 164 165 166 167
83*4882a593Smuzhiyun			168 169 170 171 172 173 174 175
84*4882a593Smuzhiyun			176 177 178 179 180 181 182 183
85*4882a593Smuzhiyun			184 185 186 187 188 189 190 191
86*4882a593Smuzhiyun			192 193 194 195 196 197 198 199
87*4882a593Smuzhiyun			200 201 202 203 204 205 206 207
88*4882a593Smuzhiyun			208 209 210 211 212 213 214 215
89*4882a593Smuzhiyun			216 217 218 219 220 221 222 223
90*4882a593Smuzhiyun			224 225 226 227 228 229 230 231
91*4882a593Smuzhiyun			232 233 234 235 236 237 238 239
92*4882a593Smuzhiyun			240 241 242 243 244 245 246 247
93*4882a593Smuzhiyun			248 249 250 251 252 253 254 255
94*4882a593Smuzhiyun		>;
95*4882a593Smuzhiyun		default-brightness-level = <200>;
96*4882a593Smuzhiyun		enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
97*4882a593Smuzhiyun	};
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun	clkin_gmac: external-gmac-clock {
100*4882a593Smuzhiyun		compatible = "fixed-clock";
101*4882a593Smuzhiyun		clock-frequency = <125000000>;
102*4882a593Smuzhiyun		clock-output-names = "clkin_gmac";
103*4882a593Smuzhiyun		#clock-cells = <0>;
104*4882a593Smuzhiyun	};
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun	fiq_debugger: fiq-debugger {
107*4882a593Smuzhiyun		compatible = "rockchip,fiq-debugger";
108*4882a593Smuzhiyun		rockchip,serial-id = <2>;
109*4882a593Smuzhiyun		rockchip,wake-irq = <0>;
110*4882a593Smuzhiyun		rockchip,irq-mode-enable = <0>;  /* If enable uart uses irq instead of fiq */
111*4882a593Smuzhiyun		rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
112*4882a593Smuzhiyun		pinctrl-names = "default";
113*4882a593Smuzhiyun		pinctrl-0 = <&uart2c_xfer>;
114*4882a593Smuzhiyun		interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
115*4882a593Smuzhiyun	};
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun	hdmi_sound: hdmi-sound {
118*4882a593Smuzhiyun		status = "okay";
119*4882a593Smuzhiyun		compatible = "simple-audio-card";
120*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
121*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <256>;
122*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,hdmi";
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun		simple-audio-card,cpu {
125*4882a593Smuzhiyun			sound-dai = <&i2s2>;
126*4882a593Smuzhiyun		};
127*4882a593Smuzhiyun		simple-audio-card,codec {
128*4882a593Smuzhiyun			sound-dai = <&hdmi>;
129*4882a593Smuzhiyun		};
130*4882a593Smuzhiyun	};
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun	panel: panel {
133*4882a593Smuzhiyun		compatible = "simple-panel";
134*4882a593Smuzhiyun		backlight = <&backlight>;
135*4882a593Smuzhiyun		enable-gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>;
136*4882a593Smuzhiyun		prepare-delay-ms = <20>;
137*4882a593Smuzhiyun		enable-delay-ms = <20>;
138*4882a593Smuzhiyun		reset-delay-ms = <20>;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun		display-timings {
141*4882a593Smuzhiyun			native-mode = <&timing0>;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun			timing0: timing0 {
144*4882a593Smuzhiyun				clock-frequency = <200000000>;
145*4882a593Smuzhiyun				hactive = <1536>;
146*4882a593Smuzhiyun				vactive = <2048>;
147*4882a593Smuzhiyun				hfront-porch = <12>;
148*4882a593Smuzhiyun				hsync-len = <16>;
149*4882a593Smuzhiyun				hback-porch = <48>;
150*4882a593Smuzhiyun				vfront-porch = <8>;
151*4882a593Smuzhiyun				vsync-len = <4>;
152*4882a593Smuzhiyun				vback-porch = <8>;
153*4882a593Smuzhiyun				hsync-active = <0>;
154*4882a593Smuzhiyun				vsync-active = <0>;
155*4882a593Smuzhiyun				de-active = <0>;
156*4882a593Smuzhiyun				pixelclk-active = <0>;
157*4882a593Smuzhiyun			};
158*4882a593Smuzhiyun		};
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun		ports {
161*4882a593Smuzhiyun			panel_in: endpoint {
162*4882a593Smuzhiyun				remote-endpoint = <&edp_out>;
163*4882a593Smuzhiyun			};
164*4882a593Smuzhiyun		};
165*4882a593Smuzhiyun	};
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun	rk809_sound: rk809-sound {
168*4882a593Smuzhiyun		compatible = "rockchip,multicodecs-card";
169*4882a593Smuzhiyun		rockchip,card-name = "rockchip,rk809-codec";
170*4882a593Smuzhiyun		rockchip,codec-hp-det;
171*4882a593Smuzhiyun		rockchip,mclk-fs = <256>;
172*4882a593Smuzhiyun		rockchip,cpu = <&i2s1>;
173*4882a593Smuzhiyun		rockchip,codec = <&rk809_codec>;
174*4882a593Smuzhiyun	};
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun	rk_headset: rk-headset {
177*4882a593Smuzhiyun		compatible = "rockchip_headset";
178*4882a593Smuzhiyun		headset_gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
179*4882a593Smuzhiyun		pinctrl-names = "default";
180*4882a593Smuzhiyun		pinctrl-0 = <&hp_det>;
181*4882a593Smuzhiyun		io-channels = <&saradc 3>;
182*4882a593Smuzhiyun	};
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun	sdio_pwrseq: sdio-pwrseq {
185*4882a593Smuzhiyun		compatible = "mmc-pwrseq-simple";
186*4882a593Smuzhiyun		clocks = <&rk809 1>;
187*4882a593Smuzhiyun		clock-names = "ext_clock";
188*4882a593Smuzhiyun		pinctrl-names = "default";
189*4882a593Smuzhiyun		pinctrl-0 = <&wifi_enable_h>;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun		/*
192*4882a593Smuzhiyun		 * On the module itself this is one of these (depending
193*4882a593Smuzhiyun		 * on the actual card populated):
194*4882a593Smuzhiyun		 * - SDIO_RESET_L_WL_REG_ON
195*4882a593Smuzhiyun		 * - PDN (power down when low)
196*4882a593Smuzhiyun		 */
197*4882a593Smuzhiyun		reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
198*4882a593Smuzhiyun	};
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun	usbacm_video_control: usbacm-video-control {
201*4882a593Smuzhiyun		compatible = "rockchip,usbacm-video-control";
202*4882a593Smuzhiyun		status = "disabled";
203*4882a593Smuzhiyun	};
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun	vcc_phy: vcc-phy-regulator {
206*4882a593Smuzhiyun		compatible = "regulator-fixed";
207*4882a593Smuzhiyun		regulator-name = "vcc_phy";
208*4882a593Smuzhiyun		regulator-always-on;
209*4882a593Smuzhiyun		regulator-boot-on;
210*4882a593Smuzhiyun	};
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun	vbus_typec: vbus-typec-regulator {
213*4882a593Smuzhiyun		compatible = "regulator-fixed";
214*4882a593Smuzhiyun		enable-active-high;
215*4882a593Smuzhiyun		gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
216*4882a593Smuzhiyun		pinctrl-names = "default";
217*4882a593Smuzhiyun		pinctrl-0 = <&vcc5v0_typec0_en>;
218*4882a593Smuzhiyun		regulator-name = "vbus_typec";
219*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
220*4882a593Smuzhiyun	};
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun	vcc5v0_sys: vccsys {
223*4882a593Smuzhiyun		compatible = "regulator-fixed";
224*4882a593Smuzhiyun		regulator-name = "vcc5v0_sys";
225*4882a593Smuzhiyun		regulator-always-on;
226*4882a593Smuzhiyun		regulator-boot-on;
227*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
228*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
229*4882a593Smuzhiyun	};
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun	wireless-wlan {
232*4882a593Smuzhiyun		compatible = "wlan-platdata";
233*4882a593Smuzhiyun		rockchip,grf = <&grf>;
234*4882a593Smuzhiyun		wifi_chip_type = "ap6398s";
235*4882a593Smuzhiyun		sdio_vref = <1800>;
236*4882a593Smuzhiyun		WIFI,host_wake_irq = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
237*4882a593Smuzhiyun		status = "okay";
238*4882a593Smuzhiyun	};
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun	wireless-bluetooth {
241*4882a593Smuzhiyun		compatible = "bluetooth-platdata";
242*4882a593Smuzhiyun		clocks = <&rk809 1>;
243*4882a593Smuzhiyun		clock-names = "ext_clock";
244*4882a593Smuzhiyun		uart_rts_gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_LOW>;
245*4882a593Smuzhiyun		pinctrl-names = "default", "rts_gpio";
246*4882a593Smuzhiyun		pinctrl-0 = <&uart0_rts>, <&bt_irq_gpio>;
247*4882a593Smuzhiyun		pinctrl-1 = <&uart0_gpios>;
248*4882a593Smuzhiyun		BT,reset_gpio    = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
249*4882a593Smuzhiyun		BT,wake_gpio     = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
250*4882a593Smuzhiyun		BT,wake_host_irq = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
251*4882a593Smuzhiyun		status = "okay";
252*4882a593Smuzhiyun	};
253*4882a593Smuzhiyun};
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun&cdn_dp {
256*4882a593Smuzhiyun	status = "okay";
257*4882a593Smuzhiyun	phys = <&tcphy0_dp>;
258*4882a593Smuzhiyun};
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun&cpu_l0 {
261*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_l>;
262*4882a593Smuzhiyun};
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun&cpu_l1 {
265*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_l>;
266*4882a593Smuzhiyun};
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun&cpu_l2 {
269*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_l>;
270*4882a593Smuzhiyun};
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun&cpu_l3 {
273*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_l>;
274*4882a593Smuzhiyun};
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun&cpu_b0 {
277*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_b>;
278*4882a593Smuzhiyun};
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun&cpu_b1 {
281*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_b>;
282*4882a593Smuzhiyun};
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun&display_subsystem {
285*4882a593Smuzhiyun	status = "okay";
286*4882a593Smuzhiyun};
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun&dfi {
289*4882a593Smuzhiyun	status = "okay";
290*4882a593Smuzhiyun};
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun&dmc {
293*4882a593Smuzhiyun	status = "okay";
294*4882a593Smuzhiyun	center-supply = <&vdd_center>;
295*4882a593Smuzhiyun	upthreshold = <40>;
296*4882a593Smuzhiyun	downdifferential = <20>;
297*4882a593Smuzhiyun	system-status-freq = <
298*4882a593Smuzhiyun		/*system status         freq(KHz)*/
299*4882a593Smuzhiyun		SYS_STATUS_NORMAL       856000
300*4882a593Smuzhiyun		SYS_STATUS_REBOOT       856000
301*4882a593Smuzhiyun		SYS_STATUS_SUSPEND      328000
302*4882a593Smuzhiyun		SYS_STATUS_VIDEO_1080P  666000
303*4882a593Smuzhiyun		SYS_STATUS_VIDEO_4K     856000
304*4882a593Smuzhiyun		SYS_STATUS_VIDEO_4K_10B 856000
305*4882a593Smuzhiyun		SYS_STATUS_PERFORMANCE  856000
306*4882a593Smuzhiyun		SYS_STATUS_BOOST        856000
307*4882a593Smuzhiyun		SYS_STATUS_DUALVIEW     856000
308*4882a593Smuzhiyun		SYS_STATUS_ISP          856000
309*4882a593Smuzhiyun	>;
310*4882a593Smuzhiyun	vop-bw-dmc-freq = <
311*4882a593Smuzhiyun	/* min_bw(MB/s) max_bw(MB/s) freq(KHz) */
312*4882a593Smuzhiyun		0       762      416000
313*4882a593Smuzhiyun		763     3012     666000
314*4882a593Smuzhiyun		3013    99999    856000
315*4882a593Smuzhiyun	>;
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun	vop-pn-msch-readlatency = <
318*4882a593Smuzhiyun		0	0x20
319*4882a593Smuzhiyun		4	0x20
320*4882a593Smuzhiyun	>;
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun	auto-min-freq = <328000>;
323*4882a593Smuzhiyun	auto-freq-en = <0>;
324*4882a593Smuzhiyun};
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun&dmc_opp_table {
327*4882a593Smuzhiyun		compatible = "operating-points-v2";
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun		opp-200000000 {
330*4882a593Smuzhiyun			opp-hz = /bits/ 64 <200000000>;
331*4882a593Smuzhiyun			opp-microvolt = <900000>;
332*4882a593Smuzhiyun			status = "disabled";
333*4882a593Smuzhiyun		};
334*4882a593Smuzhiyun		opp-300000000 {
335*4882a593Smuzhiyun			opp-hz = /bits/ 64 <300000000>;
336*4882a593Smuzhiyun			opp-microvolt = <900000>;
337*4882a593Smuzhiyun			status = "disabled";
338*4882a593Smuzhiyun		};
339*4882a593Smuzhiyun		opp-328000000 {
340*4882a593Smuzhiyun			opp-hz = /bits/ 64 <328000000>;
341*4882a593Smuzhiyun			opp-microvolt = <900000>;
342*4882a593Smuzhiyun		};
343*4882a593Smuzhiyun		opp-400000000 {
344*4882a593Smuzhiyun			opp-hz = /bits/ 64 <400000000>;
345*4882a593Smuzhiyun			opp-microvolt = <900000>;
346*4882a593Smuzhiyun			status = "disabled";
347*4882a593Smuzhiyun		};
348*4882a593Smuzhiyun		opp-416000000 {
349*4882a593Smuzhiyun			opp-hz = /bits/ 64 <416000000>;
350*4882a593Smuzhiyun			opp-microvolt = <900000>;
351*4882a593Smuzhiyun		};
352*4882a593Smuzhiyun		opp-528000000 {
353*4882a593Smuzhiyun			opp-hz = /bits/ 64 <528000000>;
354*4882a593Smuzhiyun			opp-microvolt = <900000>;
355*4882a593Smuzhiyun			status = "disabled";
356*4882a593Smuzhiyun		};
357*4882a593Smuzhiyun		opp-600000000 {
358*4882a593Smuzhiyun			opp-hz = /bits/ 64 <600000000>;
359*4882a593Smuzhiyun			opp-microvolt = <900000>;
360*4882a593Smuzhiyun			status = "disabled";
361*4882a593Smuzhiyun		};
362*4882a593Smuzhiyun		opp-666000000 {
363*4882a593Smuzhiyun			opp-hz = /bits/ 64 <666000000>;
364*4882a593Smuzhiyun			opp-microvolt = <900000>;
365*4882a593Smuzhiyun		};
366*4882a593Smuzhiyun		opp-800000000 {
367*4882a593Smuzhiyun			opp-hz = /bits/ 64 <800000000>;
368*4882a593Smuzhiyun			opp-microvolt = <900000>;
369*4882a593Smuzhiyun			status = "disabled";
370*4882a593Smuzhiyun		};
371*4882a593Smuzhiyun		opp-856000000 {
372*4882a593Smuzhiyun			opp-hz = /bits/ 64 <856000000>;
373*4882a593Smuzhiyun			opp-microvolt = <900000>;
374*4882a593Smuzhiyun		};
375*4882a593Smuzhiyun		opp-928000000 {
376*4882a593Smuzhiyun			opp-hz = /bits/ 64 <928000000>;
377*4882a593Smuzhiyun			opp-microvolt = <900000>;
378*4882a593Smuzhiyun			status = "disabled";
379*4882a593Smuzhiyun		};
380*4882a593Smuzhiyun};
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun&dp_in_vopb {
383*4882a593Smuzhiyun	status = "disabled";
384*4882a593Smuzhiyun};
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun&edp {
387*4882a593Smuzhiyun	status = "okay";
388*4882a593Smuzhiyun	force-hpd;
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun	ports {
391*4882a593Smuzhiyun		port@1 {
392*4882a593Smuzhiyun			reg = <1>;
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun			edp_out: endpoint {
395*4882a593Smuzhiyun				remote-endpoint = <&panel_in>;
396*4882a593Smuzhiyun			};
397*4882a593Smuzhiyun		};
398*4882a593Smuzhiyun	};
399*4882a593Smuzhiyun};
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun&edp_in_vopb {
402*4882a593Smuzhiyun	status = "disabled";
403*4882a593Smuzhiyun};
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun&emmc_phy {
406*4882a593Smuzhiyun	status = "okay";
407*4882a593Smuzhiyun};
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun&fiq_debugger {
410*4882a593Smuzhiyun	pinctrl-0 = <&uart2a_xfer>;
411*4882a593Smuzhiyun};
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun&gmac {
414*4882a593Smuzhiyun	phy-supply = <&vcc_phy>;
415*4882a593Smuzhiyun	phy-mode = "rgmii";
416*4882a593Smuzhiyun	clock_in_out = "input";
417*4882a593Smuzhiyun	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
418*4882a593Smuzhiyun	snps,reset-active-low;
419*4882a593Smuzhiyun	snps,reset-delays-us = <0 10000 50000>;
420*4882a593Smuzhiyun	assigned-clocks = <&cru SCLK_RMII_SRC>;
421*4882a593Smuzhiyun	assigned-clock-parents = <&clkin_gmac>;
422*4882a593Smuzhiyun	pinctrl-names = "default";
423*4882a593Smuzhiyun	pinctrl-0 = <&rgmii_pins>;
424*4882a593Smuzhiyun	tx_delay = <0x28>;
425*4882a593Smuzhiyun	rx_delay = <0x11>;
426*4882a593Smuzhiyun	status = "okay";
427*4882a593Smuzhiyun};
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun&gpu {
430*4882a593Smuzhiyun	status = "okay";
431*4882a593Smuzhiyun	mali-supply = <&vdd_gpu>;
432*4882a593Smuzhiyun};
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun&hdmi {
435*4882a593Smuzhiyun	status = "okay";
436*4882a593Smuzhiyun	#sound-dai-cells = <0>;
437*4882a593Smuzhiyun	rockchip,phy-table =
438*4882a593Smuzhiyun		<74250000  0x8009 0x0004 0x0272>,
439*4882a593Smuzhiyun		<165000000 0x802b 0x0004 0x0209>,
440*4882a593Smuzhiyun		<297000000 0x8039 0x0005 0x028d>,
441*4882a593Smuzhiyun		<594000000 0x8039 0x0000 0x00f6>,
442*4882a593Smuzhiyun		<000000000 0x0000 0x0000 0x0000>;
443*4882a593Smuzhiyun};
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun&hdmi_in_vopl {
446*4882a593Smuzhiyun	status = "disabled";
447*4882a593Smuzhiyun};
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun&i2c0 {
450*4882a593Smuzhiyun	status = "okay";
451*4882a593Smuzhiyun	i2c-scl-rising-time-ns = <180>;
452*4882a593Smuzhiyun	i2c-scl-falling-time-ns = <30>;
453*4882a593Smuzhiyun	clock-frequency = <400000>;
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun	rk809: pmic@20 {
456*4882a593Smuzhiyun		compatible = "rockchip,rk809";
457*4882a593Smuzhiyun		reg = <0x20>;
458*4882a593Smuzhiyun		interrupt-parent = <&gpio1>;
459*4882a593Smuzhiyun		interrupts = <RK_PC2 IRQ_TYPE_LEVEL_LOW>;
460*4882a593Smuzhiyun		pinctrl-names = "default", "pmic-sleep",
461*4882a593Smuzhiyun				"pmic-power-off", "pmic-reset";
462*4882a593Smuzhiyun		pinctrl-0 = <&pmic_int_l>;
463*4882a593Smuzhiyun		pinctrl-1 = <&soc_slppin_slp>, <&rk809_slppin_slp>;
464*4882a593Smuzhiyun		pinctrl-2 = <&soc_slppin_gpio>, <&rk809_slppin_pwrdn>;
465*4882a593Smuzhiyun		pinctrl-3 = <&soc_slppin_gpio>, <&rk809_slppin_null>;
466*4882a593Smuzhiyun		rockchip,system-power-controller;
467*4882a593Smuzhiyun		pmic-reset-func = <0>;
468*4882a593Smuzhiyun		wakeup-source;
469*4882a593Smuzhiyun		#clock-cells = <1>;
470*4882a593Smuzhiyun		clock-output-names = "rk808-clkout1", "rk808-clkout2";
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun		vcc1-supply = <&vcc5v0_sys>;
473*4882a593Smuzhiyun		vcc2-supply = <&vcc5v0_sys>;
474*4882a593Smuzhiyun		vcc3-supply = <&vcc5v0_sys>;
475*4882a593Smuzhiyun		vcc4-supply = <&vcc5v0_sys>;
476*4882a593Smuzhiyun		vcc5-supply = <&vcc_buck5>;
477*4882a593Smuzhiyun		vcc6-supply = <&vcc_buck5>;
478*4882a593Smuzhiyun		vcc7-supply = <&vcc3v3_sys>;
479*4882a593Smuzhiyun		vcc8-supply = <&vcc3v3_sys>;
480*4882a593Smuzhiyun		vcc9-supply = <&vcc5v0_sys>;
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun		pwrkey {
483*4882a593Smuzhiyun			status = "okay";
484*4882a593Smuzhiyun		};
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun		rtc {
487*4882a593Smuzhiyun			status = "okay";
488*4882a593Smuzhiyun		};
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun		pinctrl_rk8xx: pinctrl_rk8xx {
491*4882a593Smuzhiyun			gpio-controller;
492*4882a593Smuzhiyun			#gpio-cells = <2>;
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun			rk809_slppin_null: rk809_slppin_null {
495*4882a593Smuzhiyun				pins = "gpio_slp";
496*4882a593Smuzhiyun				function = "pin_fun0";
497*4882a593Smuzhiyun			};
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun			rk809_slppin_slp: rk809_slppin_slp {
500*4882a593Smuzhiyun				pins = "gpio_slp";
501*4882a593Smuzhiyun				function = "pin_fun1";
502*4882a593Smuzhiyun			};
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun			rk809_slppin_pwrdn: rk809_slppin_pwrdn {
505*4882a593Smuzhiyun				pins = "gpio_slp";
506*4882a593Smuzhiyun				function = "pin_fun2";
507*4882a593Smuzhiyun			};
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun			rk809_slppin_rst: rk809_slppin_rst {
510*4882a593Smuzhiyun				pins = "gpio_slp";
511*4882a593Smuzhiyun				function = "pin_fun3";
512*4882a593Smuzhiyun			};
513*4882a593Smuzhiyun		};
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun		regulators {
516*4882a593Smuzhiyun			vdd_center: DCDC_REG1 {
517*4882a593Smuzhiyun				regulator-always-on;
518*4882a593Smuzhiyun				regulator-boot-on;
519*4882a593Smuzhiyun				regulator-min-microvolt = <750000>;
520*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
521*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
522*4882a593Smuzhiyun				regulator-name = "vdd_center";
523*4882a593Smuzhiyun				regulator-state-mem {
524*4882a593Smuzhiyun					regulator-off-in-suspend;
525*4882a593Smuzhiyun					regulator-suspend-microvolt = <900000>;
526*4882a593Smuzhiyun				};
527*4882a593Smuzhiyun			};
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun			vdd_cpu_l: DCDC_REG2 {
530*4882a593Smuzhiyun				regulator-always-on;
531*4882a593Smuzhiyun				regulator-boot-on;
532*4882a593Smuzhiyun				regulator-min-microvolt = <750000>;
533*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
534*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
535*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
536*4882a593Smuzhiyun				regulator-name = "vdd_cpu_l";
537*4882a593Smuzhiyun				regulator-state-mem {
538*4882a593Smuzhiyun					regulator-off-in-suspend;
539*4882a593Smuzhiyun				};
540*4882a593Smuzhiyun			};
541*4882a593Smuzhiyun
542*4882a593Smuzhiyun			vcc_ddr: DCDC_REG3 {
543*4882a593Smuzhiyun				regulator-always-on;
544*4882a593Smuzhiyun				regulator-boot-on;
545*4882a593Smuzhiyun				regulator-name = "vcc_ddr";
546*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
547*4882a593Smuzhiyun				regulator-state-mem {
548*4882a593Smuzhiyun					regulator-on-in-suspend;
549*4882a593Smuzhiyun				};
550*4882a593Smuzhiyun			};
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun			vcc3v3_sys: DCDC_REG4 {
553*4882a593Smuzhiyun				regulator-always-on;
554*4882a593Smuzhiyun				regulator-boot-on;
555*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
556*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
557*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
558*4882a593Smuzhiyun				regulator-name = "vcc3v3_sys";
559*4882a593Smuzhiyun				regulator-state-mem {
560*4882a593Smuzhiyun					regulator-on-in-suspend;
561*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
562*4882a593Smuzhiyun				};
563*4882a593Smuzhiyun			};
564*4882a593Smuzhiyun
565*4882a593Smuzhiyun			vcc_buck5: DCDC_REG5 {
566*4882a593Smuzhiyun				regulator-always-on;
567*4882a593Smuzhiyun				regulator-boot-on;
568*4882a593Smuzhiyun				regulator-min-microvolt = <2200000>;
569*4882a593Smuzhiyun				regulator-max-microvolt = <2200000>;
570*4882a593Smuzhiyun				regulator-name = "vcc_buck5";
571*4882a593Smuzhiyun				regulator-state-mem {
572*4882a593Smuzhiyun					regulator-on-in-suspend;
573*4882a593Smuzhiyun					regulator-suspend-microvolt = <2200000>;
574*4882a593Smuzhiyun				};
575*4882a593Smuzhiyun			};
576*4882a593Smuzhiyun
577*4882a593Smuzhiyun			vcca_0v9: LDO_REG1 {
578*4882a593Smuzhiyun				regulator-always-on;
579*4882a593Smuzhiyun				regulator-boot-on;
580*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
581*4882a593Smuzhiyun				regulator-max-microvolt = <900000>;
582*4882a593Smuzhiyun				regulator-name = "vcca_0v9";
583*4882a593Smuzhiyun				regulator-state-mem {
584*4882a593Smuzhiyun					regulator-off-in-suspend;
585*4882a593Smuzhiyun				};
586*4882a593Smuzhiyun			};
587*4882a593Smuzhiyun
588*4882a593Smuzhiyun			vcc_1v8: LDO_REG2 {
589*4882a593Smuzhiyun				regulator-always-on;
590*4882a593Smuzhiyun				regulator-boot-on;
591*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
592*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
593*4882a593Smuzhiyun
594*4882a593Smuzhiyun				regulator-name = "vcc_1v8";
595*4882a593Smuzhiyun				regulator-state-mem {
596*4882a593Smuzhiyun					regulator-on-in-suspend;
597*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
598*4882a593Smuzhiyun				};
599*4882a593Smuzhiyun			};
600*4882a593Smuzhiyun
601*4882a593Smuzhiyun			vcc0v9_soc: LDO_REG3 {
602*4882a593Smuzhiyun				regulator-always-on;
603*4882a593Smuzhiyun				regulator-boot-on;
604*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
605*4882a593Smuzhiyun				regulator-max-microvolt = <900000>;
606*4882a593Smuzhiyun
607*4882a593Smuzhiyun				regulator-name = "vcc0v9_soc";
608*4882a593Smuzhiyun				regulator-state-mem {
609*4882a593Smuzhiyun					regulator-on-in-suspend;
610*4882a593Smuzhiyun					regulator-suspend-microvolt = <900000>;
611*4882a593Smuzhiyun				};
612*4882a593Smuzhiyun			};
613*4882a593Smuzhiyun
614*4882a593Smuzhiyun			vcca_1v8: LDO_REG4 {
615*4882a593Smuzhiyun				regulator-always-on;
616*4882a593Smuzhiyun				regulator-boot-on;
617*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
618*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun				regulator-name = "vcca_1v8";
621*4882a593Smuzhiyun				regulator-state-mem {
622*4882a593Smuzhiyun					regulator-off-in-suspend;
623*4882a593Smuzhiyun				};
624*4882a593Smuzhiyun			};
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun			vdd1v5_dvp: LDO_REG5 {
627*4882a593Smuzhiyun				regulator-always-on;
628*4882a593Smuzhiyun				regulator-boot-on;
629*4882a593Smuzhiyun				regulator-min-microvolt = <1500000>;
630*4882a593Smuzhiyun				regulator-max-microvolt = <1500000>;
631*4882a593Smuzhiyun
632*4882a593Smuzhiyun				regulator-name = "vdd1v5_dvp";
633*4882a593Smuzhiyun				regulator-state-mem {
634*4882a593Smuzhiyun					regulator-off-in-suspend;
635*4882a593Smuzhiyun				};
636*4882a593Smuzhiyun			};
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun			vcc_1v5: LDO_REG6 {
639*4882a593Smuzhiyun				regulator-always-on;
640*4882a593Smuzhiyun				regulator-boot-on;
641*4882a593Smuzhiyun				regulator-min-microvolt = <1500000>;
642*4882a593Smuzhiyun				regulator-max-microvolt = <1500000>;
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun				regulator-name = "vcc_1v5";
645*4882a593Smuzhiyun				regulator-state-mem {
646*4882a593Smuzhiyun					regulator-off-in-suspend;
647*4882a593Smuzhiyun				};
648*4882a593Smuzhiyun			};
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun			vcc_3v0: LDO_REG7 {
651*4882a593Smuzhiyun				regulator-always-on;
652*4882a593Smuzhiyun				regulator-boot-on;
653*4882a593Smuzhiyun				regulator-min-microvolt = <3000000>;
654*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun				regulator-name = "vcc_3v0";
657*4882a593Smuzhiyun				regulator-state-mem {
658*4882a593Smuzhiyun					regulator-off-in-suspend;
659*4882a593Smuzhiyun				};
660*4882a593Smuzhiyun			};
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun			vccio_sd: LDO_REG8 {
663*4882a593Smuzhiyun				regulator-always-on;
664*4882a593Smuzhiyun				regulator-boot-on;
665*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
666*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
667*4882a593Smuzhiyun
668*4882a593Smuzhiyun				regulator-name = "vccio_sd";
669*4882a593Smuzhiyun				regulator-state-mem {
670*4882a593Smuzhiyun					regulator-off-in-suspend;
671*4882a593Smuzhiyun				};
672*4882a593Smuzhiyun			};
673*4882a593Smuzhiyun
674*4882a593Smuzhiyun			vcc_sd: LDO_REG9 {
675*4882a593Smuzhiyun				regulator-always-on;
676*4882a593Smuzhiyun				regulator-boot-on;
677*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
678*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
679*4882a593Smuzhiyun
680*4882a593Smuzhiyun				regulator-name = "vcc_sd";
681*4882a593Smuzhiyun				regulator-state-mem {
682*4882a593Smuzhiyun					regulator-off-in-suspend;
683*4882a593Smuzhiyun				};
684*4882a593Smuzhiyun			};
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun			vcc5v0_usb: SWITCH_REG1 {
687*4882a593Smuzhiyun				regulator-name = "vcc5v0_usb";
688*4882a593Smuzhiyun				regulator-state-mem {
689*4882a593Smuzhiyun					regulator-on-in-suspend;
690*4882a593Smuzhiyun				};
691*4882a593Smuzhiyun			};
692*4882a593Smuzhiyun
693*4882a593Smuzhiyun			vccio_3v3: SWITCH_REG2 {
694*4882a593Smuzhiyun				regulator-always-on;
695*4882a593Smuzhiyun				regulator-boot-on;
696*4882a593Smuzhiyun				regulator-name = "vccio_3v3";
697*4882a593Smuzhiyun				regulator-state-mem {
698*4882a593Smuzhiyun					regulator-off-in-suspend;
699*4882a593Smuzhiyun				};
700*4882a593Smuzhiyun			};
701*4882a593Smuzhiyun		};
702*4882a593Smuzhiyun
703*4882a593Smuzhiyun		rk809_codec: codec {
704*4882a593Smuzhiyun			#sound-dai-cells = <0>;
705*4882a593Smuzhiyun			compatible = "rockchip,rk809-codec", "rockchip,rk817-codec";
706*4882a593Smuzhiyun			clocks = <&cru SCLK_I2S_8CH_OUT>;
707*4882a593Smuzhiyun			clock-names = "mclk";
708*4882a593Smuzhiyun			pinctrl-names = "default";
709*4882a593Smuzhiyun			pinctrl-0 = <&i2s_8ch_mclk>;
710*4882a593Smuzhiyun			hp-volume = <20>;
711*4882a593Smuzhiyun			spk-volume = <3>;
712*4882a593Smuzhiyun			status = "okay";
713*4882a593Smuzhiyun		};
714*4882a593Smuzhiyun	};
715*4882a593Smuzhiyun
716*4882a593Smuzhiyun	vdd_cpu_b: tcs4525@1c {
717*4882a593Smuzhiyun		compatible = "tcs,tcs4525";
718*4882a593Smuzhiyun		reg = <0x1c>;
719*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
720*4882a593Smuzhiyun		regulator-compatible = "fan53555-reg";
721*4882a593Smuzhiyun		pinctrl-0 = <&vsel1_gpio>;
722*4882a593Smuzhiyun		vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
723*4882a593Smuzhiyun		regulator-name = "vdd_cpu_b";
724*4882a593Smuzhiyun		regulator-min-microvolt = <712500>;
725*4882a593Smuzhiyun		regulator-max-microvolt = <1500000>;
726*4882a593Smuzhiyun		regulator-ramp-delay = <2300>;
727*4882a593Smuzhiyun		fcs,suspend-voltage-selector = <1>;
728*4882a593Smuzhiyun		regulator-always-on;
729*4882a593Smuzhiyun		regulator-boot-on;
730*4882a593Smuzhiyun		regulator-initial-state = <3>;
731*4882a593Smuzhiyun		regulator-state-mem {
732*4882a593Smuzhiyun			regulator-off-in-suspend;
733*4882a593Smuzhiyun		};
734*4882a593Smuzhiyun	};
735*4882a593Smuzhiyun
736*4882a593Smuzhiyun	vdd_gpu: tcs4526@10 {
737*4882a593Smuzhiyun		compatible = "tcs,tcs4526";
738*4882a593Smuzhiyun		reg = <0x10>;
739*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
740*4882a593Smuzhiyun		regulator-compatible = "fan53555-reg";
741*4882a593Smuzhiyun		pinctrl-0 = <&vsel2_gpio>;
742*4882a593Smuzhiyun		vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>;
743*4882a593Smuzhiyun		regulator-name = "vdd_gpu";
744*4882a593Smuzhiyun		regulator-min-microvolt = <735000>;
745*4882a593Smuzhiyun		regulator-max-microvolt = <1400000>;
746*4882a593Smuzhiyun		regulator-ramp-delay = <1000>;
747*4882a593Smuzhiyun		fcs,suspend-voltage-selector = <1>;
748*4882a593Smuzhiyun		regulator-always-on;
749*4882a593Smuzhiyun		regulator-boot-on;
750*4882a593Smuzhiyun		regulator-initial-state = <3>;
751*4882a593Smuzhiyun		regulator-state-mem {
752*4882a593Smuzhiyun			regulator-off-in-suspend;
753*4882a593Smuzhiyun		};
754*4882a593Smuzhiyun	};
755*4882a593Smuzhiyun
756*4882a593Smuzhiyun	bq25700: bq25700@6b {
757*4882a593Smuzhiyun		compatible = "ti,bq25703";
758*4882a593Smuzhiyun		reg = <0x6b>;
759*4882a593Smuzhiyun		interrupt-parent = <&gpio1>;
760*4882a593Smuzhiyun		interrupts = <RK_PA1 IRQ_TYPE_LEVEL_LOW>;
761*4882a593Smuzhiyun		pinctrl-names = "default";
762*4882a593Smuzhiyun		pinctrl-0 = <&charger_ok_int>;
763*4882a593Smuzhiyun		ti,charge-current = <1500000>;
764*4882a593Smuzhiyun		ti,max-charge-voltage = <8704000>;
765*4882a593Smuzhiyun		ti,max-input-voltage = <20000000>;
766*4882a593Smuzhiyun		ti,max-input-current = <6000000>;
767*4882a593Smuzhiyun		ti,input-current-sdp = <500000>;
768*4882a593Smuzhiyun		ti,input-current-dcp = <2000000>;
769*4882a593Smuzhiyun		ti,input-current-cdp = <2000000>;
770*4882a593Smuzhiyun		ti,input-current-dc = <2000000>;
771*4882a593Smuzhiyun		ti,minimum-sys-voltage = <6700000>;
772*4882a593Smuzhiyun		ti,otg-voltage = <5000000>;
773*4882a593Smuzhiyun		ti,otg-current = <500000>;
774*4882a593Smuzhiyun		ti,input-current = <500000>;
775*4882a593Smuzhiyun		pd-charge-only = <0>;
776*4882a593Smuzhiyun		status = "disabled";
777*4882a593Smuzhiyun	};
778*4882a593Smuzhiyun};
779*4882a593Smuzhiyun
780*4882a593Smuzhiyun&i2c1 {
781*4882a593Smuzhiyun	status = "okay";
782*4882a593Smuzhiyun	i2c-scl-rising-time-ns = <140>;
783*4882a593Smuzhiyun	i2c-scl-falling-time-ns = <30>;
784*4882a593Smuzhiyun
785*4882a593Smuzhiyun	mpu6500@68 {
786*4882a593Smuzhiyun		status = "okay";
787*4882a593Smuzhiyun		compatible = "invensense,mpu6500";
788*4882a593Smuzhiyun		reg = <0x68>;
789*4882a593Smuzhiyun		irq-gpio = <&gpio3 RK_PD2 IRQ_TYPE_EDGE_RISING>;
790*4882a593Smuzhiyun		mpu-int_config = <0x10>;
791*4882a593Smuzhiyun		mpu-level_shifter = <0>;
792*4882a593Smuzhiyun		mpu-orientation = <0 1 0 1 0 0 0 0 1>;
793*4882a593Smuzhiyun		orientation-x= <1>;
794*4882a593Smuzhiyun		orientation-y= <0>;
795*4882a593Smuzhiyun		orientation-z= <0>;
796*4882a593Smuzhiyun		mpu-debug = <1>;
797*4882a593Smuzhiyun	};
798*4882a593Smuzhiyun
799*4882a593Smuzhiyun	sensor@d {
800*4882a593Smuzhiyun		status = "okay";
801*4882a593Smuzhiyun		compatible = "ak8963";
802*4882a593Smuzhiyun		reg = <0x0d>;
803*4882a593Smuzhiyun		type = <SENSOR_TYPE_COMPASS>;
804*4882a593Smuzhiyun		irq-gpio = <&gpio3 RK_PD7 IRQ_TYPE_EDGE_RISING>;
805*4882a593Smuzhiyun		irq_enable = <0>;
806*4882a593Smuzhiyun		poll_delay_ms = <30>;
807*4882a593Smuzhiyun		layout = <3>;
808*4882a593Smuzhiyun	};
809*4882a593Smuzhiyun
810*4882a593Smuzhiyun	ov13850: ov13850@10 {
811*4882a593Smuzhiyun		compatible = "ovti,ov13850";
812*4882a593Smuzhiyun		status = "okay";
813*4882a593Smuzhiyun		reg = <0x10>;
814*4882a593Smuzhiyun		clocks = <&cru SCLK_CIF_OUT>;
815*4882a593Smuzhiyun		clock-names = "xvclk";
816*4882a593Smuzhiyun
817*4882a593Smuzhiyun		/* conflict with csi-ctl-gpios */
818*4882a593Smuzhiyun		reset-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
819*4882a593Smuzhiyun		pwdn-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>;
820*4882a593Smuzhiyun		pinctrl-names = "rockchip,camera_default";
821*4882a593Smuzhiyun		pinctrl-0 = <&cif_clkout>;
822*4882a593Smuzhiyun
823*4882a593Smuzhiyun		port {
824*4882a593Smuzhiyun			ucam_out0: endpoint {
825*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ucam0>;
826*4882a593Smuzhiyun				data-lanes = <1 2>;
827*4882a593Smuzhiyun			};
828*4882a593Smuzhiyun		};
829*4882a593Smuzhiyun	};
830*4882a593Smuzhiyun
831*4882a593Smuzhiyun	imx327: imx327@1a {
832*4882a593Smuzhiyun		compatible = "sony,imx327";
833*4882a593Smuzhiyun		status = "okay";
834*4882a593Smuzhiyun		reg = <0x1a>;
835*4882a593Smuzhiyun		clocks = <&cru SCLK_CIF_OUT>;
836*4882a593Smuzhiyun		clock-names = "xvclk";
837*4882a593Smuzhiyun		/* conflict with csi-ctl-gpios */
838*4882a593Smuzhiyun		reset-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
839*4882a593Smuzhiyun		pwdn-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>;
840*4882a593Smuzhiyun		pinctrl-names = "default";
841*4882a593Smuzhiyun		pinctrl-0 = <&cif_clkout>;
842*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
843*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
844*4882a593Smuzhiyun		rockchip,camera-module-name = "TongJu";
845*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "CHT842-MD";
846*4882a593Smuzhiyun		port {
847*4882a593Smuzhiyun			ucam_out2: endpoint {
848*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ucam2>;
849*4882a593Smuzhiyun				data-lanes = <1 2>;
850*4882a593Smuzhiyun			};
851*4882a593Smuzhiyun		};
852*4882a593Smuzhiyun	};
853*4882a593Smuzhiyun
854*4882a593Smuzhiyun};
855*4882a593Smuzhiyun
856*4882a593Smuzhiyun&i2c4 {
857*4882a593Smuzhiyun	status = "okay";
858*4882a593Smuzhiyun	i2c-scl-rising-time-ns = <345>;
859*4882a593Smuzhiyun	i2c-scl-falling-time-ns = <11>;
860*4882a593Smuzhiyun
861*4882a593Smuzhiyun	gsl3673: gsl3673@40 {
862*4882a593Smuzhiyun		compatible = "GSL,GSL3673";
863*4882a593Smuzhiyun		reg = <0x40>;
864*4882a593Smuzhiyun		screen_max_x = <1536>;
865*4882a593Smuzhiyun		screen_max_y = <2048>;
866*4882a593Smuzhiyun		irq_gpio_number = <&gpio4 RK_PC3 IRQ_TYPE_LEVEL_LOW>;
867*4882a593Smuzhiyun		rst_gpio_number = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
868*4882a593Smuzhiyun	};
869*4882a593Smuzhiyun};
870*4882a593Smuzhiyun
871*4882a593Smuzhiyun&i2c8 {
872*4882a593Smuzhiyun	status = "okay";
873*4882a593Smuzhiyun	i2c-scl-rising-time-ns = <345>;
874*4882a593Smuzhiyun	i2c-scl-falling-time-ns = <11>;
875*4882a593Smuzhiyun	clock-frequency = <100000>;
876*4882a593Smuzhiyun
877*4882a593Smuzhiyun	fusb0: fusb30x@22 {
878*4882a593Smuzhiyun		compatible = "fairchild,fusb302";
879*4882a593Smuzhiyun		reg = <0x22>;
880*4882a593Smuzhiyun		pinctrl-names = "default";
881*4882a593Smuzhiyun		pinctrl-0 = <&fusb0_int>;
882*4882a593Smuzhiyun		int-n-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
883*4882a593Smuzhiyun		vbus-5v-gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_LOW>;
884*4882a593Smuzhiyun		status = "okay";
885*4882a593Smuzhiyun	};
886*4882a593Smuzhiyun
887*4882a593Smuzhiyun};
888*4882a593Smuzhiyun
889*4882a593Smuzhiyun&i2s1 {
890*4882a593Smuzhiyun	status = "okay";
891*4882a593Smuzhiyun	#sound-dai-cells = <0>;
892*4882a593Smuzhiyun};
893*4882a593Smuzhiyun
894*4882a593Smuzhiyun&i2s2 {
895*4882a593Smuzhiyun	#sound-dai-cells = <0>;
896*4882a593Smuzhiyun	status = "okay";
897*4882a593Smuzhiyun};
898*4882a593Smuzhiyun
899*4882a593Smuzhiyun&io_domains {
900*4882a593Smuzhiyun	status = "okay";
901*4882a593Smuzhiyun	bt656-supply = <&vcca_1v8>;
902*4882a593Smuzhiyun	audio-supply = <&vcca_1v8>;
903*4882a593Smuzhiyun	sdmmc-supply = <&vccio_sd>;
904*4882a593Smuzhiyun	gpio1830-supply = <&vcc_3v0>;
905*4882a593Smuzhiyun};
906*4882a593Smuzhiyun
907*4882a593Smuzhiyun&isp0_mmu {
908*4882a593Smuzhiyun	status = "okay";
909*4882a593Smuzhiyun};
910*4882a593Smuzhiyun
911*4882a593Smuzhiyun&isp1_mmu {
912*4882a593Smuzhiyun	status = "okay";
913*4882a593Smuzhiyun};
914*4882a593Smuzhiyun
915*4882a593Smuzhiyun&mipi_dphy_tx1rx1 {
916*4882a593Smuzhiyun	status = "okay";
917*4882a593Smuzhiyun
918*4882a593Smuzhiyun	ports {
919*4882a593Smuzhiyun		#address-cells = <1>;
920*4882a593Smuzhiyun		#size-cells = <0>;
921*4882a593Smuzhiyun
922*4882a593Smuzhiyun		port@0 {
923*4882a593Smuzhiyun			reg = <0>;
924*4882a593Smuzhiyun			#address-cells = <1>;
925*4882a593Smuzhiyun			#size-cells = <0>;
926*4882a593Smuzhiyun
927*4882a593Smuzhiyun			mipi_in_ucam1: endpoint@1 {
928*4882a593Smuzhiyun				reg = <1>;
929*4882a593Smuzhiyun				/* Unlinked camera */
930*4882a593Smuzhiyun				//remote-endpoint = <&ucam_out1>;
931*4882a593Smuzhiyun				data-lanes = <1 2>;
932*4882a593Smuzhiyun			};
933*4882a593Smuzhiyun		};
934*4882a593Smuzhiyun
935*4882a593Smuzhiyun		port@1 {
936*4882a593Smuzhiyun			reg = <1>;
937*4882a593Smuzhiyun			#address-cells = <1>;
938*4882a593Smuzhiyun			#size-cells = <0>;
939*4882a593Smuzhiyun
940*4882a593Smuzhiyun			dphy_tx1rx1_out: endpoint@0 {
941*4882a593Smuzhiyun				reg = <0>;
942*4882a593Smuzhiyun				remote-endpoint = <&isp1_mipi_in>;
943*4882a593Smuzhiyun			};
944*4882a593Smuzhiyun		};
945*4882a593Smuzhiyun	};
946*4882a593Smuzhiyun};
947*4882a593Smuzhiyun
948*4882a593Smuzhiyun&mipi_dphy_rx0 {
949*4882a593Smuzhiyun	status = "okay";
950*4882a593Smuzhiyun
951*4882a593Smuzhiyun	ports {
952*4882a593Smuzhiyun		#address-cells = <1>;
953*4882a593Smuzhiyun		#size-cells = <0>;
954*4882a593Smuzhiyun
955*4882a593Smuzhiyun		port@0 {
956*4882a593Smuzhiyun			reg = <0>;
957*4882a593Smuzhiyun			#address-cells = <1>;
958*4882a593Smuzhiyun			#size-cells = <0>;
959*4882a593Smuzhiyun
960*4882a593Smuzhiyun			mipi_in_ucam0: endpoint@1 {
961*4882a593Smuzhiyun				reg = <1>;
962*4882a593Smuzhiyun				remote-endpoint = <&ucam_out0>;
963*4882a593Smuzhiyun				data-lanes = <1 2>;
964*4882a593Smuzhiyun			};
965*4882a593Smuzhiyun			mipi_in_ucam2: endpoint@2 {
966*4882a593Smuzhiyun				reg = <2>;
967*4882a593Smuzhiyun				remote-endpoint = <&ucam_out2>;
968*4882a593Smuzhiyun				data-lanes = <1 2>;
969*4882a593Smuzhiyun			};
970*4882a593Smuzhiyun		};
971*4882a593Smuzhiyun
972*4882a593Smuzhiyun		port@1 {
973*4882a593Smuzhiyun			reg = <1>;
974*4882a593Smuzhiyun			#address-cells = <1>;
975*4882a593Smuzhiyun			#size-cells = <0>;
976*4882a593Smuzhiyun
977*4882a593Smuzhiyun			dphy_rx0_out: endpoint@0 {
978*4882a593Smuzhiyun				reg = <0>;
979*4882a593Smuzhiyun				remote-endpoint = <&isp0_mipi_in>;
980*4882a593Smuzhiyun			};
981*4882a593Smuzhiyun		};
982*4882a593Smuzhiyun	};
983*4882a593Smuzhiyun};
984*4882a593Smuzhiyun
985*4882a593Smuzhiyun&pcie_phy {
986*4882a593Smuzhiyun	status = "okay";
987*4882a593Smuzhiyun};
988*4882a593Smuzhiyun
989*4882a593Smuzhiyun&pcie0 {
990*4882a593Smuzhiyun	status = "okay";
991*4882a593Smuzhiyun};
992*4882a593Smuzhiyun
993*4882a593Smuzhiyun&pmu_io_domains {
994*4882a593Smuzhiyun	status = "okay";
995*4882a593Smuzhiyun	pmu1830-supply = <&vcc_1v8>;
996*4882a593Smuzhiyun};
997*4882a593Smuzhiyun
998*4882a593Smuzhiyun&pwm0 {
999*4882a593Smuzhiyun	status = "okay";
1000*4882a593Smuzhiyun};
1001*4882a593Smuzhiyun
1002*4882a593Smuzhiyun&pwm2 {
1003*4882a593Smuzhiyun	status = "okay";
1004*4882a593Smuzhiyun};
1005*4882a593Smuzhiyun
1006*4882a593Smuzhiyun&rkisp1_0 {
1007*4882a593Smuzhiyun	status = "okay";
1008*4882a593Smuzhiyun	assigned-clocks = <&cru PLL_NPLL>, <&cru SCLK_CIF_OUT_SRC>, <&cru SCLK_CIF_OUT>;
1009*4882a593Smuzhiyun	assigned-clock-rates = <594000000>, <594000000>, <37125000>;
1010*4882a593Smuzhiyun	port {
1011*4882a593Smuzhiyun		#address-cells = <1>;
1012*4882a593Smuzhiyun		#size-cells = <0>;
1013*4882a593Smuzhiyun
1014*4882a593Smuzhiyun		isp0_mipi_in: endpoint@0 {
1015*4882a593Smuzhiyun			reg = <0>;
1016*4882a593Smuzhiyun			remote-endpoint = <&dphy_rx0_out>;
1017*4882a593Smuzhiyun		};
1018*4882a593Smuzhiyun	};
1019*4882a593Smuzhiyun};
1020*4882a593Smuzhiyun
1021*4882a593Smuzhiyun&rkisp1_1 {
1022*4882a593Smuzhiyun	status = "okay";
1023*4882a593Smuzhiyun
1024*4882a593Smuzhiyun	port {
1025*4882a593Smuzhiyun		#address-cells = <1>;
1026*4882a593Smuzhiyun		#size-cells = <0>;
1027*4882a593Smuzhiyun
1028*4882a593Smuzhiyun		isp1_mipi_in: endpoint@0 {
1029*4882a593Smuzhiyun			reg = <0>;
1030*4882a593Smuzhiyun			remote-endpoint = <&dphy_tx1rx1_out>;
1031*4882a593Smuzhiyun		};
1032*4882a593Smuzhiyun	};
1033*4882a593Smuzhiyun};
1034*4882a593Smuzhiyun
1035*4882a593Smuzhiyun&rockchip_suspend {
1036*4882a593Smuzhiyun	status = "okay";
1037*4882a593Smuzhiyun	rockchip,sleep-debug-en = <1>;
1038*4882a593Smuzhiyun	rockchip,sleep-mode-config = <
1039*4882a593Smuzhiyun		(0
1040*4882a593Smuzhiyun		| RKPM_SLP_ARMPD
1041*4882a593Smuzhiyun		| RKPM_SLP_PERILPPD
1042*4882a593Smuzhiyun		| RKPM_SLP_DDR_RET
1043*4882a593Smuzhiyun		| RKPM_SLP_PLLPD
1044*4882a593Smuzhiyun		| RKPM_SLP_CENTER_PD
1045*4882a593Smuzhiyun		| RKPM_SLP_OSC_DIS
1046*4882a593Smuzhiyun		| RKPM_SLP_AP_PWROFF
1047*4882a593Smuzhiyun		)
1048*4882a593Smuzhiyun	>;
1049*4882a593Smuzhiyun	rockchip,wakeup-config = <RKPM_GPIO_WKUP_EN>;
1050*4882a593Smuzhiyun	rockchip,pwm-regulator-config = <PWM2_REGULATOR_EN>;
1051*4882a593Smuzhiyun	rockchip,power-ctrl =
1052*4882a593Smuzhiyun		<&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>,
1053*4882a593Smuzhiyun		<&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>;
1054*4882a593Smuzhiyun};
1055*4882a593Smuzhiyun
1056*4882a593Smuzhiyun&route_edp {
1057*4882a593Smuzhiyun	status = "okay";
1058*4882a593Smuzhiyun};
1059*4882a593Smuzhiyun
1060*4882a593Smuzhiyun&saradc {
1061*4882a593Smuzhiyun	status = "okay";
1062*4882a593Smuzhiyun	vref-supply = <&vcc_1v8>;
1063*4882a593Smuzhiyun};
1064*4882a593Smuzhiyun
1065*4882a593Smuzhiyun&sdmmc {
1066*4882a593Smuzhiyun	sd-uhs-sdr12;
1067*4882a593Smuzhiyun	sd-uhs-sdr25;
1068*4882a593Smuzhiyun	sd-uhs-sdr50;
1069*4882a593Smuzhiyun	sd-uhs-sdr104;
1070*4882a593Smuzhiyun};
1071*4882a593Smuzhiyun
1072*4882a593Smuzhiyun&spi1 {
1073*4882a593Smuzhiyun	status = "okay";
1074*4882a593Smuzhiyun	max-freq = <48000000>; /* spi internal clk, don't modify */
1075*4882a593Smuzhiyun	spi_dev@0 {
1076*4882a593Smuzhiyun		compatible = "rockchip,spidev";
1077*4882a593Smuzhiyun		reg = <0>;
1078*4882a593Smuzhiyun		spi-max-frequency = <12000000>;
1079*4882a593Smuzhiyun		spi-lsb-first;
1080*4882a593Smuzhiyun	};
1081*4882a593Smuzhiyun};
1082*4882a593Smuzhiyun
1083*4882a593Smuzhiyun&tcphy0 {
1084*4882a593Smuzhiyun	status = "okay";
1085*4882a593Smuzhiyun	orientation-switch;
1086*4882a593Smuzhiyun	port {
1087*4882a593Smuzhiyun		#address-cells = <1>;
1088*4882a593Smuzhiyun		#size-cells = <0>;
1089*4882a593Smuzhiyun		tcphy0_orientation_switch: endpoint@0 {
1090*4882a593Smuzhiyun			reg = <0>;
1091*4882a593Smuzhiyun			remote-endpoint = <&usbc0_orien_sw>;
1092*4882a593Smuzhiyun		};
1093*4882a593Smuzhiyun	};
1094*4882a593Smuzhiyun};
1095*4882a593Smuzhiyun
1096*4882a593Smuzhiyun&tcphy1 {
1097*4882a593Smuzhiyun	status = "okay";
1098*4882a593Smuzhiyun};
1099*4882a593Smuzhiyun
1100*4882a593Smuzhiyun&tsadc {
1101*4882a593Smuzhiyun	rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
1102*4882a593Smuzhiyun	rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
1103*4882a593Smuzhiyun	status = "okay";
1104*4882a593Smuzhiyun};
1105*4882a593Smuzhiyun
1106*4882a593Smuzhiyun&u2phy0 {
1107*4882a593Smuzhiyun	status = "okay";
1108*4882a593Smuzhiyun	extcon = <&fusb0>;
1109*4882a593Smuzhiyun
1110*4882a593Smuzhiyun	u2phy0_otg: otg-port {
1111*4882a593Smuzhiyun		status = "okay";
1112*4882a593Smuzhiyun	};
1113*4882a593Smuzhiyun
1114*4882a593Smuzhiyun	u2phy0_host: host-port {
1115*4882a593Smuzhiyun		phy-supply = <&vcc5v0_usb>;
1116*4882a593Smuzhiyun		status = "okay";
1117*4882a593Smuzhiyun	};
1118*4882a593Smuzhiyun};
1119*4882a593Smuzhiyun
1120*4882a593Smuzhiyun&u2phy1 {
1121*4882a593Smuzhiyun	status = "okay";
1122*4882a593Smuzhiyun
1123*4882a593Smuzhiyun	u2phy1_otg: otg-port {
1124*4882a593Smuzhiyun		status = "okay";
1125*4882a593Smuzhiyun	};
1126*4882a593Smuzhiyun
1127*4882a593Smuzhiyun	u2phy1_host: host-port {
1128*4882a593Smuzhiyun		phy-supply = <&vcc5v0_usb>;
1129*4882a593Smuzhiyun		status = "okay";
1130*4882a593Smuzhiyun	};
1131*4882a593Smuzhiyun};
1132*4882a593Smuzhiyun
1133*4882a593Smuzhiyun&uart0 {
1134*4882a593Smuzhiyun	pinctrl-names = "default";
1135*4882a593Smuzhiyun	pinctrl-0 = <&uart0_xfer &uart0_cts>;
1136*4882a593Smuzhiyun	status = "okay";
1137*4882a593Smuzhiyun};
1138*4882a593Smuzhiyun
1139*4882a593Smuzhiyun&usb_host0_ehci {
1140*4882a593Smuzhiyun	status = "okay";
1141*4882a593Smuzhiyun};
1142*4882a593Smuzhiyun
1143*4882a593Smuzhiyun&usb_host1_ehci {
1144*4882a593Smuzhiyun	status = "okay";
1145*4882a593Smuzhiyun};
1146*4882a593Smuzhiyun&usb_host0_ohci {
1147*4882a593Smuzhiyun	status = "okay";
1148*4882a593Smuzhiyun};
1149*4882a593Smuzhiyun
1150*4882a593Smuzhiyun&usb_host1_ohci {
1151*4882a593Smuzhiyun	status = "okay";
1152*4882a593Smuzhiyun};
1153*4882a593Smuzhiyun
1154*4882a593Smuzhiyun&usbdrd3_0 {
1155*4882a593Smuzhiyun	status = "okay";
1156*4882a593Smuzhiyun};
1157*4882a593Smuzhiyun
1158*4882a593Smuzhiyun&usbdrd3_1 {
1159*4882a593Smuzhiyun	status = "okay";
1160*4882a593Smuzhiyun};
1161*4882a593Smuzhiyun
1162*4882a593Smuzhiyun&usbdrd_dwc3_0 {
1163*4882a593Smuzhiyun	status = "okay";
1164*4882a593Smuzhiyun	usb-role-switch;
1165*4882a593Smuzhiyun	port {
1166*4882a593Smuzhiyun		#address-cells = <1>;
1167*4882a593Smuzhiyun		#size-cells = <0>;
1168*4882a593Smuzhiyun		dwc3_0_role_switch: endpoint@0 {
1169*4882a593Smuzhiyun			reg = <0>;
1170*4882a593Smuzhiyun			remote-endpoint = <&usbc0_role_sw>;
1171*4882a593Smuzhiyun		};
1172*4882a593Smuzhiyun	};
1173*4882a593Smuzhiyun};
1174*4882a593Smuzhiyun
1175*4882a593Smuzhiyun&usbdrd_dwc3_1 {
1176*4882a593Smuzhiyun	status = "okay";
1177*4882a593Smuzhiyun};
1178*4882a593Smuzhiyun
1179*4882a593Smuzhiyun&vopb {
1180*4882a593Smuzhiyun	status = "okay";
1181*4882a593Smuzhiyun};
1182*4882a593Smuzhiyun
1183*4882a593Smuzhiyun&vopb_mmu {
1184*4882a593Smuzhiyun	status = "okay";
1185*4882a593Smuzhiyun};
1186*4882a593Smuzhiyun
1187*4882a593Smuzhiyun&vopl {
1188*4882a593Smuzhiyun	status = "okay";
1189*4882a593Smuzhiyun};
1190*4882a593Smuzhiyun
1191*4882a593Smuzhiyun&vopl_mmu {
1192*4882a593Smuzhiyun	status = "okay";
1193*4882a593Smuzhiyun};
1194*4882a593Smuzhiyun
1195*4882a593Smuzhiyun&pinctrl {
1196*4882a593Smuzhiyun	pinctrl-names = "default";
1197*4882a593Smuzhiyun	pinctrl-0 = <&npu_ref_clk>;
1198*4882a593Smuzhiyun
1199*4882a593Smuzhiyun	bq2570 {
1200*4882a593Smuzhiyun		charger_ok_int: charger-ok-int {
1201*4882a593Smuzhiyun			rockchip,pins =
1202*4882a593Smuzhiyun				<1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
1203*4882a593Smuzhiyun			};
1204*4882a593Smuzhiyun	};
1205*4882a593Smuzhiyun
1206*4882a593Smuzhiyun	headphone {
1207*4882a593Smuzhiyun		hp_det: hp-det {
1208*4882a593Smuzhiyun			rockchip,pins =
1209*4882a593Smuzhiyun				<0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
1210*4882a593Smuzhiyun		};
1211*4882a593Smuzhiyun	};
1212*4882a593Smuzhiyun
1213*4882a593Smuzhiyun	lcd_rst {
1214*4882a593Smuzhiyun		lcd_rst_gpio: lcd-rst-gpio {
1215*4882a593Smuzhiyun			rockchip,pins =
1216*4882a593Smuzhiyun				<3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
1217*4882a593Smuzhiyun		};
1218*4882a593Smuzhiyun	};
1219*4882a593Smuzhiyun
1220*4882a593Smuzhiyun	npu_clk {
1221*4882a593Smuzhiyun		npu_ref_clk: npu-ref-clk {
1222*4882a593Smuzhiyun		     rockchip,pins =
1223*4882a593Smuzhiyun			     <0 RK_PA2 1 &pcfg_pull_none>;
1224*4882a593Smuzhiyun	     };
1225*4882a593Smuzhiyun	};
1226*4882a593Smuzhiyun
1227*4882a593Smuzhiyun	pmic {
1228*4882a593Smuzhiyun		pmic_int_l: pmic-int-l {
1229*4882a593Smuzhiyun			rockchip,pins =
1230*4882a593Smuzhiyun				<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
1231*4882a593Smuzhiyun		};
1232*4882a593Smuzhiyun		vsel1_gpio: vsel1-gpio {
1233*4882a593Smuzhiyun			rockchip,pins =
1234*4882a593Smuzhiyun				<1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
1235*4882a593Smuzhiyun		};
1236*4882a593Smuzhiyun		vsel2_gpio: vsel2-gpio {
1237*4882a593Smuzhiyun			rockchip,pins =
1238*4882a593Smuzhiyun				<1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
1239*4882a593Smuzhiyun		};
1240*4882a593Smuzhiyun
1241*4882a593Smuzhiyun		soc_slppin_gpio: soc-slppin-gpio {
1242*4882a593Smuzhiyun			rockchip,pins =
1243*4882a593Smuzhiyun				<1 RK_PA5 RK_FUNC_GPIO &pcfg_output_low>;
1244*4882a593Smuzhiyun		};
1245*4882a593Smuzhiyun
1246*4882a593Smuzhiyun		soc_slppin_slp: soc-slppin-slp {
1247*4882a593Smuzhiyun			rockchip,pins =
1248*4882a593Smuzhiyun				<1 RK_PA5 1 &pcfg_pull_down>;
1249*4882a593Smuzhiyun		};
1250*4882a593Smuzhiyun
1251*4882a593Smuzhiyun		soc_slppin_rst: soc-slppin-rst {
1252*4882a593Smuzhiyun			rockchip,pins =
1253*4882a593Smuzhiyun				<1 RK_PA5 2 &pcfg_pull_none>;
1254*4882a593Smuzhiyun		};
1255*4882a593Smuzhiyun	};
1256*4882a593Smuzhiyun
1257*4882a593Smuzhiyun	sdio-pwrseq {
1258*4882a593Smuzhiyun		wifi_enable_h: wifi-enable-h {
1259*4882a593Smuzhiyun			rockchip,pins =
1260*4882a593Smuzhiyun				<2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
1261*4882a593Smuzhiyun		};
1262*4882a593Smuzhiyun	};
1263*4882a593Smuzhiyun
1264*4882a593Smuzhiyun	sdmmc {
1265*4882a593Smuzhiyun		sdmmc_bus1: sdmmc-bus1 {
1266*4882a593Smuzhiyun			rockchip,pins =
1267*4882a593Smuzhiyun				<4 RK_PB0 1 &pcfg_pull_up_10ma>;
1268*4882a593Smuzhiyun		};
1269*4882a593Smuzhiyun
1270*4882a593Smuzhiyun		sdmmc_bus4: sdmmc-bus4 {
1271*4882a593Smuzhiyun			rockchip,pins =
1272*4882a593Smuzhiyun				<4 RK_PB0 1 &pcfg_pull_up_10ma>,
1273*4882a593Smuzhiyun				<4 RK_PB1 1 &pcfg_pull_up_10ma>,
1274*4882a593Smuzhiyun				<4 RK_PB2 1 &pcfg_pull_up_10ma>,
1275*4882a593Smuzhiyun				<4 RK_PB3 1 &pcfg_pull_up_10ma>;
1276*4882a593Smuzhiyun		};
1277*4882a593Smuzhiyun
1278*4882a593Smuzhiyun		sdmmc_clk: sdmmc-clk {
1279*4882a593Smuzhiyun			rockchip,pins =
1280*4882a593Smuzhiyun				<4 RK_PB4 1 &pcfg_pull_none_10ma>;
1281*4882a593Smuzhiyun		};
1282*4882a593Smuzhiyun
1283*4882a593Smuzhiyun		sdmmc_cmd: sdmmc-cmd {
1284*4882a593Smuzhiyun			rockchip,pins =
1285*4882a593Smuzhiyun				<4 RK_PB5 1 &pcfg_pull_up_10ma>;
1286*4882a593Smuzhiyun		};
1287*4882a593Smuzhiyun	};
1288*4882a593Smuzhiyun
1289*4882a593Smuzhiyun	tp_irq {
1290*4882a593Smuzhiyun		tp_irq_gpio: tp-irq-gpio {
1291*4882a593Smuzhiyun			rockchip,pins =
1292*4882a593Smuzhiyun				<3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
1293*4882a593Smuzhiyun		};
1294*4882a593Smuzhiyun	};
1295*4882a593Smuzhiyun
1296*4882a593Smuzhiyun	usb-typec {
1297*4882a593Smuzhiyun		usbc0_int: usbc0-int {
1298*4882a593Smuzhiyun			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
1299*4882a593Smuzhiyun		};
1300*4882a593Smuzhiyun
1301*4882a593Smuzhiyun	vcc5v0_typec0_en: vcc5v0-typec0-en {
1302*4882a593Smuzhiyun		rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
1303*4882a593Smuzhiyun		};
1304*4882a593Smuzhiyun	};
1305*4882a593Smuzhiyun
1306*4882a593Smuzhiyun	wireless-bluetooth {
1307*4882a593Smuzhiyun		bt_irq_gpio: bt-irq-gpio {
1308*4882a593Smuzhiyun			rockchip,pins =
1309*4882a593Smuzhiyun				<0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>;
1310*4882a593Smuzhiyun		};
1311*4882a593Smuzhiyun
1312*4882a593Smuzhiyun		uart0_gpios: uart0-gpios {
1313*4882a593Smuzhiyun			rockchip,pins =
1314*4882a593Smuzhiyun				<2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
1315*4882a593Smuzhiyun		};
1316*4882a593Smuzhiyun	};
1317*4882a593Smuzhiyun};
1318*4882a593Smuzhiyun
1319*4882a593Smuzhiyun/* DON'T PUT ANYTHING BELOW HERE.  PUT IT ABOVE PINCTRL */
1320*4882a593Smuzhiyun/* DON'T PUT ANYTHING BELOW HERE.  PUT IT ABOVE PINCTRL */
1321*4882a593Smuzhiyun/* DON'T PUT ANYTHING BELOW HERE.  PUT IT ABOVE PINCTRL */
1322