xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-tve1030g.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun/dts-v1/;
8*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h>
9*4882a593Smuzhiyun#include <dt-bindings/sensor-dev.h>
10*4882a593Smuzhiyun#include "rk3399.dtsi"
11*4882a593Smuzhiyun#include "rk3399-android.dtsi"
12*4882a593Smuzhiyun#include "rk3399-opp.dtsi"
13*4882a593Smuzhiyun#include "rk3399-vop-clk-set.dtsi"
14*4882a593Smuzhiyun#include <dt-bindings/display/mipi_dsi.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun/ {
17*4882a593Smuzhiyun	adc_keys {
18*4882a593Smuzhiyun		compatible = "adc-keys";
19*4882a593Smuzhiyun		io-channels = <&saradc 1>;
20*4882a593Smuzhiyun		io-channel-names = "buttons";
21*4882a593Smuzhiyun		keyup-threshold-microvolt = <1800000>;
22*4882a593Smuzhiyun		poll-interval = <100>;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun		vol-up-key {
25*4882a593Smuzhiyun			label = "volume up";
26*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
27*4882a593Smuzhiyun			press-threshold-microvolt = <1000>;
28*4882a593Smuzhiyun		};
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun		vol-down-key {
31*4882a593Smuzhiyun			label = "volume down";
32*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEDOWN>;
33*4882a593Smuzhiyun			press-threshold-microvolt = <170000>;
34*4882a593Smuzhiyun		};
35*4882a593Smuzhiyun	};
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun	backlight: backlight {
38*4882a593Smuzhiyun		compatible = "pwm-backlight";
39*4882a593Smuzhiyun		pwms = <&pwm0 0 25000 0>;
40*4882a593Smuzhiyun		brightness-levels = <
41*4882a593Smuzhiyun			  0  20  20  21  21  22  22  23
42*4882a593Smuzhiyun			 23  24  24  25  25  26  26  27
43*4882a593Smuzhiyun			 27  28  28  29  29  30  30  31
44*4882a593Smuzhiyun			 31  32  32  33  33  34  34  35
45*4882a593Smuzhiyun			 35  36  36  37  37  38  38  39
46*4882a593Smuzhiyun			 40  41  42  43  44  45  46  47
47*4882a593Smuzhiyun			 48  49  50  51  52  53  54  55
48*4882a593Smuzhiyun			 56  57  58  59  60  61  62  63
49*4882a593Smuzhiyun			 64  65  66  67  68  69  70  71
50*4882a593Smuzhiyun			 72  73  74  75  76  77  78  79
51*4882a593Smuzhiyun			 80  81  82  83  84  85  86  87
52*4882a593Smuzhiyun			 88  89  90  91  92  93  94  95
53*4882a593Smuzhiyun			 96  97  98  99 100 101 102 103
54*4882a593Smuzhiyun			104 105 106 107 108 109 110 111
55*4882a593Smuzhiyun			112 113 114 115 116 117 118 119
56*4882a593Smuzhiyun			120 121 122 123 124 125 126 127
57*4882a593Smuzhiyun			128 129 130 131 132 133 134 135
58*4882a593Smuzhiyun			136 137 138 139 140 141 142 143
59*4882a593Smuzhiyun			144 145 146 147 148 149 150 151
60*4882a593Smuzhiyun			152 153 154 155 156 157 158 159
61*4882a593Smuzhiyun			160 161 162 163 164 165 166 167
62*4882a593Smuzhiyun			168 169 170 171 172 173 174 175
63*4882a593Smuzhiyun			176 177 178 179 180 181 182 183
64*4882a593Smuzhiyun			184 185 186 187 188 189 190 191
65*4882a593Smuzhiyun			192 193 194 195 196 197 198 199
66*4882a593Smuzhiyun			200 201 202 203 204 205 206 207
67*4882a593Smuzhiyun			208 209 210 211 212 213 214 215
68*4882a593Smuzhiyun			216 217 218 219 220 221 222 223
69*4882a593Smuzhiyun			224 225 226 227 228 229 230 231
70*4882a593Smuzhiyun			232 233 234 235 236 237 238 239
71*4882a593Smuzhiyun			240 241 242 243 244 245 246 247
72*4882a593Smuzhiyun			248 249 250 251 252 253 254 255
73*4882a593Smuzhiyun		>;
74*4882a593Smuzhiyun		default-brightness-level = <200>;
75*4882a593Smuzhiyun	};
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun	es8316-sound {
78*4882a593Smuzhiyun		compatible = "simple-audio-card";
79*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
80*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,es8316-codec";
81*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <256>;
82*4882a593Smuzhiyun		simple-audio-card,widgets =
83*4882a593Smuzhiyun			"Microphone", "Mic Jack",
84*4882a593Smuzhiyun			"Headphone", "Headphone Jack";
85*4882a593Smuzhiyun		simple-audio-card,routing =
86*4882a593Smuzhiyun			"Mic Jack", "MICBIAS1",
87*4882a593Smuzhiyun			"IN1P", "Mic Jack",
88*4882a593Smuzhiyun			"Headphone Jack", "HPOL",
89*4882a593Smuzhiyun			"Headphone Jack", "HPOR";
90*4882a593Smuzhiyun		simple-audio-card,cpu {
91*4882a593Smuzhiyun			sound-dai = <&i2s0>;
92*4882a593Smuzhiyun			system-clock-frequency = <11289600>;
93*4882a593Smuzhiyun		};
94*4882a593Smuzhiyun		simple-audio-card,codec {
95*4882a593Smuzhiyun			sound-dai = <&es8316>;
96*4882a593Smuzhiyun			system-clock-frequency = <11289600>;
97*4882a593Smuzhiyun		};
98*4882a593Smuzhiyun	};
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun	rk_headset: rk-headset {
101*4882a593Smuzhiyun		compatible = "rockchip_headset";
102*4882a593Smuzhiyun		headset_gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
103*4882a593Smuzhiyun		pinctrl-names = "default";
104*4882a593Smuzhiyun		pinctrl-0 = <&hp_det>;
105*4882a593Smuzhiyun		io-channels = <&saradc 2>;
106*4882a593Smuzhiyun	};
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun	charge-animation {
109*4882a593Smuzhiyun		compatible = "rockchip,uboot-charge";
110*4882a593Smuzhiyun		rockchip,uboot-charge-on = <1>;
111*4882a593Smuzhiyun		rockchip,android-charge-on = <0>;
112*4882a593Smuzhiyun		rockchip,uboot-low-power-voltage = <6700>;
113*4882a593Smuzhiyun		rockchip,screen-on-voltage = <6800>;
114*4882a593Smuzhiyun		status = "okay";
115*4882a593Smuzhiyun	};
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun	sdio_pwrseq: sdio-pwrseq {
118*4882a593Smuzhiyun		compatible = "mmc-pwrseq-simple";
119*4882a593Smuzhiyun		clocks = <&rk808 1>;
120*4882a593Smuzhiyun		clock-names = "ext_clock";
121*4882a593Smuzhiyun		pinctrl-names = "default";
122*4882a593Smuzhiyun		pinctrl-0 = <&wifi_enable_h>;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun		/*
125*4882a593Smuzhiyun		 * On the module itself this is one of these (depending
126*4882a593Smuzhiyun		 * on the actual card populated):
127*4882a593Smuzhiyun		 * - SDIO_RESET_L_WL_REG_ON
128*4882a593Smuzhiyun		 * - PDN (power down when low)
129*4882a593Smuzhiyun		 */
130*4882a593Smuzhiyun		reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
131*4882a593Smuzhiyun	};
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun	vcc_sys: vcc-sys {
134*4882a593Smuzhiyun		compatible = "regulator-fixed";
135*4882a593Smuzhiyun		regulator-name = "vcc_sys";
136*4882a593Smuzhiyun		regulator-always-on;
137*4882a593Smuzhiyun		regulator-boot-on;
138*4882a593Smuzhiyun		regulator-min-microvolt = <3900000>;
139*4882a593Smuzhiyun		regulator-max-microvolt = <3900000>;
140*4882a593Smuzhiyun	};
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun	vcc3v3_sys: vcc3v3-sys {
143*4882a593Smuzhiyun		compatible = "regulator-fixed";
144*4882a593Smuzhiyun		regulator-name = "vcc3v3_sys";
145*4882a593Smuzhiyun		regulator-always-on;
146*4882a593Smuzhiyun		regulator-boot-on;
147*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
148*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
149*4882a593Smuzhiyun	};
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun	vcc5v0_host: vcc5v0-host-regulator {
152*4882a593Smuzhiyun		compatible = "regulator-fixed";
153*4882a593Smuzhiyun		gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
154*4882a593Smuzhiyun		pinctrl-names = "default";
155*4882a593Smuzhiyun		pinctrl-0 = <&host_vbus_drv>;
156*4882a593Smuzhiyun		regulator-name = "vcc5v0_host";
157*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
158*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
159*4882a593Smuzhiyun		regulator-always-on;
160*4882a593Smuzhiyun		enable-active-high;
161*4882a593Smuzhiyun	};
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun	vdd_log: vdd-log {
164*4882a593Smuzhiyun		compatible = "pwm-regulator";
165*4882a593Smuzhiyun		pwms = <&pwm2 0 25000 1>;
166*4882a593Smuzhiyun		rockchip,pwm_id= <2>;
167*4882a593Smuzhiyun		rockchip,pwm_voltage = <900000>;
168*4882a593Smuzhiyun		regulator-name = "vdd_log";
169*4882a593Smuzhiyun		regulator-min-microvolt = <750000>;
170*4882a593Smuzhiyun		regulator-max-microvolt = <1350000>;
171*4882a593Smuzhiyun		regulator-always-on;
172*4882a593Smuzhiyun		regulator-boot-on;
173*4882a593Smuzhiyun	};
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun	xin32k: xin32k {
176*4882a593Smuzhiyun		compatible = "fixed-clock";
177*4882a593Smuzhiyun		clock-frequency = <32768>;
178*4882a593Smuzhiyun		clock-output-names = "xin32k";
179*4882a593Smuzhiyun		#clock-cells = <0>;
180*4882a593Smuzhiyun	};
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun	wireless-wlan {
183*4882a593Smuzhiyun		compatible = "wlan-platdata";
184*4882a593Smuzhiyun		rockchip,grf = <&grf>;
185*4882a593Smuzhiyun		wifi_chip_type = "ap6255";
186*4882a593Smuzhiyun		sdio_vref = <1800>;
187*4882a593Smuzhiyun		WIFI,host_wake_irq = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
188*4882a593Smuzhiyun		status = "okay";
189*4882a593Smuzhiyun	};
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun	wireless-bluetooth {
192*4882a593Smuzhiyun		compatible = "bluetooth-platdata";
193*4882a593Smuzhiyun		clocks = <&rk808 1>;
194*4882a593Smuzhiyun		clock-names = "ext_clock";
195*4882a593Smuzhiyun		uart_rts_gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_LOW>;
196*4882a593Smuzhiyun		pinctrl-names = "default", "rts_gpio";
197*4882a593Smuzhiyun		pinctrl-0 = <&uart0_rts>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>;
198*4882a593Smuzhiyun		pinctrl-1 = <&uart0_gpios>;
199*4882a593Smuzhiyun		BT,reset_gpio    = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
200*4882a593Smuzhiyun		BT,wake_gpio     = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
201*4882a593Smuzhiyun		BT,wake_host_irq = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
202*4882a593Smuzhiyun		status = "okay";
203*4882a593Smuzhiyun	};
204*4882a593Smuzhiyun};
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun&cdn_dp {
207*4882a593Smuzhiyun	status = "okay";
208*4882a593Smuzhiyun	extcon = <&fusb0>;
209*4882a593Smuzhiyun	phys = <&tcphy0_dp>;
210*4882a593Smuzhiyun};
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun&cpu_l0 {
213*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_l>;
214*4882a593Smuzhiyun};
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun&cpu_l1 {
217*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_l>;
218*4882a593Smuzhiyun};
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun&cpu_l2 {
221*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_l>;
222*4882a593Smuzhiyun};
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun&cpu_l3 {
225*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_l>;
226*4882a593Smuzhiyun};
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun&cpu_b0 {
229*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_b>;
230*4882a593Smuzhiyun};
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun&cpu_b1 {
233*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_b>;
234*4882a593Smuzhiyun};
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun&dfi {
237*4882a593Smuzhiyun	status = "okay";
238*4882a593Smuzhiyun};
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun&dmc {
241*4882a593Smuzhiyun	status = "okay";
242*4882a593Smuzhiyun	center-supply = <&vdd_center>;
243*4882a593Smuzhiyun	upthreshold = <20>;
244*4882a593Smuzhiyun	downdifferential = <10>;
245*4882a593Smuzhiyun	system-status-freq = <
246*4882a593Smuzhiyun		/*system status         freq(KHz)*/
247*4882a593Smuzhiyun		SYS_STATUS_NORMAL       856000
248*4882a593Smuzhiyun		SYS_STATUS_REBOOT       856000
249*4882a593Smuzhiyun		SYS_STATUS_SUSPEND      416000
250*4882a593Smuzhiyun		SYS_STATUS_VIDEO_1080P  416000
251*4882a593Smuzhiyun		SYS_STATUS_VIDEO_4K     666000
252*4882a593Smuzhiyun		SYS_STATUS_VIDEO_4K_10B 856000
253*4882a593Smuzhiyun		SYS_STATUS_PERFORMANCE  856000
254*4882a593Smuzhiyun		SYS_STATUS_BOOST        856000
255*4882a593Smuzhiyun		SYS_STATUS_DUALVIEW     856000
256*4882a593Smuzhiyun		SYS_STATUS_ISP          856000
257*4882a593Smuzhiyun	>;
258*4882a593Smuzhiyun	vop-bw-dmc-freq = <
259*4882a593Smuzhiyun	/* min_bw(MB/s) max_bw(MB/s) freq(KHz) */
260*4882a593Smuzhiyun		0       762      328000
261*4882a593Smuzhiyun		763     3012     666000
262*4882a593Smuzhiyun		3013    99999    856000
263*4882a593Smuzhiyun	>;
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun	auto-min-freq = <328000>;
266*4882a593Smuzhiyun	auto-freq-en = <1>;
267*4882a593Smuzhiyun};
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun&dmc_opp_table {
270*4882a593Smuzhiyun		compatible = "operating-points-v2";
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun		opp-200000000 {
273*4882a593Smuzhiyun			opp-hz = /bits/ 64 <200000000>;
274*4882a593Smuzhiyun			opp-microvolt = <900000>;
275*4882a593Smuzhiyun			status = "disabled";
276*4882a593Smuzhiyun		};
277*4882a593Smuzhiyun		opp-300000000 {
278*4882a593Smuzhiyun			opp-hz = /bits/ 64 <300000000>;
279*4882a593Smuzhiyun			opp-microvolt = <900000>;
280*4882a593Smuzhiyun			status = "disabled";
281*4882a593Smuzhiyun		};
282*4882a593Smuzhiyun		opp-328000000 {
283*4882a593Smuzhiyun			opp-hz = /bits/ 64 <328000000>;
284*4882a593Smuzhiyun			opp-microvolt = <900000>;
285*4882a593Smuzhiyun		};
286*4882a593Smuzhiyun		opp-400000000 {
287*4882a593Smuzhiyun			opp-hz = /bits/ 64 <400000000>;
288*4882a593Smuzhiyun			opp-microvolt = <900000>;
289*4882a593Smuzhiyun			status = "disabled";
290*4882a593Smuzhiyun		};
291*4882a593Smuzhiyun		opp-416000000 {
292*4882a593Smuzhiyun			opp-hz = /bits/ 64 <416000000>;
293*4882a593Smuzhiyun			opp-microvolt = <900000>;
294*4882a593Smuzhiyun		};
295*4882a593Smuzhiyun		opp-528000000 {
296*4882a593Smuzhiyun			opp-hz = /bits/ 64 <528000000>;
297*4882a593Smuzhiyun			opp-microvolt = <900000>;
298*4882a593Smuzhiyun			status = "disabled";
299*4882a593Smuzhiyun		};
300*4882a593Smuzhiyun		opp-600000000 {
301*4882a593Smuzhiyun			opp-hz = /bits/ 64 <600000000>;
302*4882a593Smuzhiyun			opp-microvolt = <900000>;
303*4882a593Smuzhiyun			status = "disabled";
304*4882a593Smuzhiyun		};
305*4882a593Smuzhiyun		opp-666000000 {
306*4882a593Smuzhiyun			opp-hz = /bits/ 64 <666000000>;
307*4882a593Smuzhiyun			opp-microvolt = <900000>;
308*4882a593Smuzhiyun		};
309*4882a593Smuzhiyun		opp-800000000 {
310*4882a593Smuzhiyun			opp-hz = /bits/ 64 <800000000>;
311*4882a593Smuzhiyun			opp-microvolt = <900000>;
312*4882a593Smuzhiyun			status = "disabled";
313*4882a593Smuzhiyun		};
314*4882a593Smuzhiyun		opp-856000000 {
315*4882a593Smuzhiyun			opp-hz = /bits/ 64 <856000000>;
316*4882a593Smuzhiyun			opp-microvolt = <900000>;
317*4882a593Smuzhiyun		};
318*4882a593Smuzhiyun		opp-928000000 {
319*4882a593Smuzhiyun			opp-hz = /bits/ 64 <928000000>;
320*4882a593Smuzhiyun			opp-microvolt = <900000>;
321*4882a593Smuzhiyun			status = "disabled";
322*4882a593Smuzhiyun		};
323*4882a593Smuzhiyun};
324*4882a593Smuzhiyun&dp_in_vopb {
325*4882a593Smuzhiyun	status = "disabled";
326*4882a593Smuzhiyun};
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun&dsi {
329*4882a593Smuzhiyun	status = "okay";
330*4882a593Smuzhiyun	rockchip,lane-rate = <1000>;
331*4882a593Smuzhiyun	dsi_panel: panel@0 {
332*4882a593Smuzhiyun		status = "okay";
333*4882a593Smuzhiyun		compatible = "simple-panel-dsi";
334*4882a593Smuzhiyun		reg = <0>;
335*4882a593Smuzhiyun		backlight = <&backlight>;
336*4882a593Smuzhiyun		reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>;
337*4882a593Smuzhiyun		pinctrl-names = "default";
338*4882a593Smuzhiyun		pinctrl-0 = <&lcd_rst_gpio>;
339*4882a593Smuzhiyun		reset-delay-ms = <60>;
340*4882a593Smuzhiyun		enable-delay-ms = <60>;
341*4882a593Smuzhiyun		prepare-delay-ms = <60>;
342*4882a593Smuzhiyun		unprepare-delay-ms = <60>;
343*4882a593Smuzhiyun		disable-delay-ms = <60>;
344*4882a593Smuzhiyun		dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
345*4882a593Smuzhiyun			MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
346*4882a593Smuzhiyun		dsi,format = <MIPI_DSI_FMT_RGB888>;
347*4882a593Smuzhiyun		dsi,lanes  = <4>;
348*4882a593Smuzhiyun		panel-init-sequence = [
349*4882a593Smuzhiyun			15 05 02 8F A5
350*4882a593Smuzhiyun			15 14 02 01 00
351*4882a593Smuzhiyun			15 05 02 8F A5
352*4882a593Smuzhiyun			15 00 02 83 AA
353*4882a593Smuzhiyun			15 00 02 84 11
354*4882a593Smuzhiyun			15 00 02 A9 4B
355*4882a593Smuzhiyun			15 00 02 83 00
356*4882a593Smuzhiyun			15 00 02 84 00
357*4882a593Smuzhiyun			15 00 02 8F 00
358*4882a593Smuzhiyun		];
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun		disp_timings: display-timings {
361*4882a593Smuzhiyun			native-mode = <&timing0>;
362*4882a593Smuzhiyun			timing0: timing0 {
363*4882a593Smuzhiyun				clock-frequency = <150000000>;
364*4882a593Smuzhiyun				hactive = <1200>;
365*4882a593Smuzhiyun				hfront-porch = <80>;
366*4882a593Smuzhiyun				hback-porch = <60>;
367*4882a593Smuzhiyun				hsync-len = <1>;
368*4882a593Smuzhiyun				vactive = <1920>;
369*4882a593Smuzhiyun				vfront-porch = <35>;
370*4882a593Smuzhiyun				vback-porch = <25>;
371*4882a593Smuzhiyun				vsync-len = <1>;
372*4882a593Smuzhiyun				hsync-active = <0>;
373*4882a593Smuzhiyun				vsync-active = <0>;
374*4882a593Smuzhiyun				de-active = <0>;
375*4882a593Smuzhiyun				pixelclk-active = <0>;
376*4882a593Smuzhiyun			};
377*4882a593Smuzhiyun		};
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun		ports {
380*4882a593Smuzhiyun			#address-cells = <1>;
381*4882a593Smuzhiyun			#size-cells = <0>;
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun			port@0 {
384*4882a593Smuzhiyun				reg = <0>;
385*4882a593Smuzhiyun				panel_in_dsi: endpoint {
386*4882a593Smuzhiyun					remote-endpoint = <&dsi_out_panel>;
387*4882a593Smuzhiyun				};
388*4882a593Smuzhiyun			};
389*4882a593Smuzhiyun		};
390*4882a593Smuzhiyun	};
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun	ports {
393*4882a593Smuzhiyun		#address-cells = <1>;
394*4882a593Smuzhiyun		#size-cells = <0>;
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun		port@1 {
397*4882a593Smuzhiyun			reg = <1>;
398*4882a593Smuzhiyun			dsi_out_panel: endpoint {
399*4882a593Smuzhiyun				remote-endpoint = <&panel_in_dsi>;
400*4882a593Smuzhiyun			};
401*4882a593Smuzhiyun		};
402*4882a593Smuzhiyun	};
403*4882a593Smuzhiyun};
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun&dsi_in_vopl {
406*4882a593Smuzhiyun	status = "disabled";
407*4882a593Smuzhiyun};
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun&emmc_phy {
410*4882a593Smuzhiyun	status = "okay";
411*4882a593Smuzhiyun};
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun&gpu {
414*4882a593Smuzhiyun	status = "okay";
415*4882a593Smuzhiyun	mali-supply = <&vdd_gpu>;
416*4882a593Smuzhiyun};
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun&hdmi {
419*4882a593Smuzhiyun	status = "okay";
420*4882a593Smuzhiyun};
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun&hdmi_dp_sound {
423*4882a593Smuzhiyun	status = "okay";
424*4882a593Smuzhiyun};
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun&hdmi_in_vopb {
427*4882a593Smuzhiyun	status = "disabled";
428*4882a593Smuzhiyun};
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun&i2c0 {
431*4882a593Smuzhiyun	status = "okay";
432*4882a593Smuzhiyun	i2c-scl-rising-time-ns = <180>;
433*4882a593Smuzhiyun	i2c-scl-falling-time-ns = <30>;
434*4882a593Smuzhiyun	clock-frequency = <400000>;
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun	vdd_cpu_b: syr837@40 {
437*4882a593Smuzhiyun		compatible = "silergy,syr827";
438*4882a593Smuzhiyun		reg = <0x40>;
439*4882a593Smuzhiyun		vin-supply = <&vcc_sys>;
440*4882a593Smuzhiyun		regulator-compatible = "fan53555-reg";
441*4882a593Smuzhiyun		pinctrl-0 = <&vsel1_gpio>;
442*4882a593Smuzhiyun		vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
443*4882a593Smuzhiyun		regulator-name = "vdd_cpu_b";
444*4882a593Smuzhiyun		regulator-min-microvolt = <712500>;
445*4882a593Smuzhiyun		regulator-max-microvolt = <1500000>;
446*4882a593Smuzhiyun		regulator-ramp-delay = <1000>;
447*4882a593Smuzhiyun		fcs,suspend-voltage-selector = <1>;
448*4882a593Smuzhiyun		regulator-always-on;
449*4882a593Smuzhiyun		regulator-initial-state = <3>;
450*4882a593Smuzhiyun		regulator-state-mem {
451*4882a593Smuzhiyun			regulator-off-in-suspend;
452*4882a593Smuzhiyun		};
453*4882a593Smuzhiyun	};
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun	vdd_gpu: syr828@41 {
456*4882a593Smuzhiyun		compatible = "silergy,syr828";
457*4882a593Smuzhiyun		status = "okay";
458*4882a593Smuzhiyun		reg = <0x41>;
459*4882a593Smuzhiyun		vin-supply = <&vcc_sys>;
460*4882a593Smuzhiyun		regulator-compatible = "fan53555-reg";
461*4882a593Smuzhiyun		pinctrl-0 = <&vsel2_gpio>;
462*4882a593Smuzhiyun		vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>;
463*4882a593Smuzhiyun		regulator-name = "vdd_gpu";
464*4882a593Smuzhiyun		regulator-min-microvolt = <735000>;
465*4882a593Smuzhiyun		regulator-max-microvolt = <1400000>;
466*4882a593Smuzhiyun		regulator-ramp-delay = <1000>;
467*4882a593Smuzhiyun		fcs,suspend-voltage-selector = <1>;
468*4882a593Smuzhiyun		regulator-always-on;
469*4882a593Smuzhiyun		regulator-boot-on;
470*4882a593Smuzhiyun		regulator-state-mem {
471*4882a593Smuzhiyun			regulator-off-in-suspend;
472*4882a593Smuzhiyun		};
473*4882a593Smuzhiyun	};
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun	rk808: pmic@1b {
476*4882a593Smuzhiyun		compatible = "rockchip,rk808";
477*4882a593Smuzhiyun		reg = <0x1b>;
478*4882a593Smuzhiyun		interrupt-parent = <&gpio1>;
479*4882a593Smuzhiyun		interrupts = <RK_PC5 IRQ_TYPE_LEVEL_LOW>;
480*4882a593Smuzhiyun		pinctrl-0 = <&pmic_int_l>;
481*4882a593Smuzhiyun		rockchip,system-power-controller;
482*4882a593Smuzhiyun		wakeup-source;
483*4882a593Smuzhiyun		#clock-cells = <1>;
484*4882a593Smuzhiyun		clock-output-names = "rk808-clkout1", "rk808-clkout2";
485*4882a593Smuzhiyun		vcc1-supply = <&vcc3v3_sys>;
486*4882a593Smuzhiyun		vcc2-supply = <&vcc3v3_sys>;
487*4882a593Smuzhiyun		vcc3-supply = <&vcc3v3_sys>;
488*4882a593Smuzhiyun		vcc4-supply = <&vcc3v3_sys>;
489*4882a593Smuzhiyun		vcc6-supply = <&vcc3v3_sys>;
490*4882a593Smuzhiyun		vcc7-supply = <&vcc3v3_sys>;
491*4882a593Smuzhiyun		vcc8-supply = <&vcc3v3_sys>;
492*4882a593Smuzhiyun		vcc9-supply = <&vcc3v3_sys>;
493*4882a593Smuzhiyun		vcc10-supply = <&vcc3v3_sys>;
494*4882a593Smuzhiyun		vcc11-supply = <&vcc3v3_sys>;
495*4882a593Smuzhiyun		vcc12-supply = <&vcc3v3_sys>;
496*4882a593Smuzhiyun		vddio-supply = <&vcc1v8_pmu>;
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun		regulators {
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun			vdd_center: DCDC_REG1 {
501*4882a593Smuzhiyun				regulator-always-on;
502*4882a593Smuzhiyun				regulator-boot-on;
503*4882a593Smuzhiyun				regulator-min-microvolt = <750000>;
504*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
505*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
506*4882a593Smuzhiyun				regulator-name = "vdd_center";
507*4882a593Smuzhiyun				regulator-state-mem {
508*4882a593Smuzhiyun					regulator-off-in-suspend;
509*4882a593Smuzhiyun				};
510*4882a593Smuzhiyun			};
511*4882a593Smuzhiyun			vdd_cpu_l: DCDC_REG2 {
512*4882a593Smuzhiyun				regulator-always-on;
513*4882a593Smuzhiyun				regulator-boot-on;
514*4882a593Smuzhiyun				regulator-min-microvolt = <750000>;
515*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
516*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
517*4882a593Smuzhiyun				regulator-name = "vdd_cpu_l";
518*4882a593Smuzhiyun				regulator-state-mem {
519*4882a593Smuzhiyun					regulator-off-in-suspend;
520*4882a593Smuzhiyun				};
521*4882a593Smuzhiyun			};
522*4882a593Smuzhiyun			vcc_ddr: DCDC_REG3 {
523*4882a593Smuzhiyun				regulator-always-on;
524*4882a593Smuzhiyun				regulator-boot-on;
525*4882a593Smuzhiyun				regulator-name = "vcc_ddr";
526*4882a593Smuzhiyun				regulator-state-mem {
527*4882a593Smuzhiyun					regulator-on-in-suspend;
528*4882a593Smuzhiyun				};
529*4882a593Smuzhiyun			};
530*4882a593Smuzhiyun			vcc_1v8: DCDC_REG4 {
531*4882a593Smuzhiyun				regulator-always-on;
532*4882a593Smuzhiyun				regulator-boot-on;
533*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
534*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
535*4882a593Smuzhiyun				regulator-name = "vcc_1v8";
536*4882a593Smuzhiyun				regulator-state-mem {
537*4882a593Smuzhiyun				regulator-on-in-suspend;
538*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
539*4882a593Smuzhiyun				};
540*4882a593Smuzhiyun			};
541*4882a593Smuzhiyun			vcc1v8_dvp: LDO_REG1 {
542*4882a593Smuzhiyun				regulator-always-on;
543*4882a593Smuzhiyun				regulator-boot-on;
544*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
545*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
546*4882a593Smuzhiyun				regulator-name = "vcc1v8_dvp";
547*4882a593Smuzhiyun				regulator-state-mem {
548*4882a593Smuzhiyun					regulator-off-in-suspend;
549*4882a593Smuzhiyun				};
550*4882a593Smuzhiyun			};
551*4882a593Smuzhiyun			vcc3v0_tp: LDO_REG2 {
552*4882a593Smuzhiyun				regulator-always-on;
553*4882a593Smuzhiyun				regulator-boot-on;
554*4882a593Smuzhiyun				regulator-min-microvolt = <3000000>;
555*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
556*4882a593Smuzhiyun				regulator-name = "vcc3v0_tp";
557*4882a593Smuzhiyun				regulator-state-mem {
558*4882a593Smuzhiyun					regulator-on-in-suspend;
559*4882a593Smuzhiyun				};
560*4882a593Smuzhiyun			};
561*4882a593Smuzhiyun			vcc1v8_pmu: LDO_REG3 {
562*4882a593Smuzhiyun				regulator-always-on;
563*4882a593Smuzhiyun				regulator-boot-on;
564*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
565*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
566*4882a593Smuzhiyun				regulator-name = "vcc1v8_pmu";
567*4882a593Smuzhiyun				regulator-state-mem {
568*4882a593Smuzhiyun					regulator-on-in-suspend;
569*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
570*4882a593Smuzhiyun				};
571*4882a593Smuzhiyun			};
572*4882a593Smuzhiyun			vcc_sd: LDO_REG4 {
573*4882a593Smuzhiyun				regulator-always-on;
574*4882a593Smuzhiyun				regulator-boot-on;
575*4882a593Smuzhiyun				regulator-min-microvolt = <3000000>;
576*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
577*4882a593Smuzhiyun				regulator-name = "vcc_sd";
578*4882a593Smuzhiyun				regulator-state-mem {
579*4882a593Smuzhiyun					regulator-on-in-suspend;
580*4882a593Smuzhiyun					regulator-suspend-microvolt = <3000000>;
581*4882a593Smuzhiyun				};
582*4882a593Smuzhiyun			};
583*4882a593Smuzhiyun			vcca3v0_codec: LDO_REG5 {
584*4882a593Smuzhiyun				regulator-always-on;
585*4882a593Smuzhiyun				regulator-boot-on;
586*4882a593Smuzhiyun				regulator-min-microvolt = <3000000>;
587*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
588*4882a593Smuzhiyun				regulator-name = "vcca3v0_codec";
589*4882a593Smuzhiyun				regulator-state-mem {
590*4882a593Smuzhiyun					regulator-off-in-suspend;
591*4882a593Smuzhiyun				};
592*4882a593Smuzhiyun			};
593*4882a593Smuzhiyun			vcc_1v5: LDO_REG6 {
594*4882a593Smuzhiyun				regulator-always-on;
595*4882a593Smuzhiyun				regulator-boot-on;
596*4882a593Smuzhiyun				regulator-min-microvolt = <1500000>;
597*4882a593Smuzhiyun				regulator-max-microvolt = <1500000>;
598*4882a593Smuzhiyun				regulator-name = "vcc_1v5";
599*4882a593Smuzhiyun				regulator-state-mem {
600*4882a593Smuzhiyun					regulator-on-in-suspend;
601*4882a593Smuzhiyun					regulator-suspend-microvolt = <1500000>;
602*4882a593Smuzhiyun				};
603*4882a593Smuzhiyun			};
604*4882a593Smuzhiyun			vcca1v8_codec: LDO_REG7 {
605*4882a593Smuzhiyun				regulator-always-on;
606*4882a593Smuzhiyun				regulator-boot-on;
607*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
608*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
609*4882a593Smuzhiyun				regulator-name = "vcca1v8_codec";
610*4882a593Smuzhiyun				regulator-state-mem {
611*4882a593Smuzhiyun					regulator-off-in-suspend;
612*4882a593Smuzhiyun				};
613*4882a593Smuzhiyun			};
614*4882a593Smuzhiyun			vcc_3v0: LDO_REG8 {
615*4882a593Smuzhiyun				regulator-always-on;
616*4882a593Smuzhiyun				regulator-boot-on;
617*4882a593Smuzhiyun				regulator-min-microvolt = <3000000>;
618*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
619*4882a593Smuzhiyun				regulator-name = "vcc_3v0";
620*4882a593Smuzhiyun				regulator-state-mem {
621*4882a593Smuzhiyun					regulator-on-in-suspend;
622*4882a593Smuzhiyun					regulator-suspend-microvolt = <3000000>;
623*4882a593Smuzhiyun				};
624*4882a593Smuzhiyun			};
625*4882a593Smuzhiyun			vcc3v3_s3: SWITCH_REG1 {
626*4882a593Smuzhiyun				regulator-always-on;
627*4882a593Smuzhiyun				regulator-boot-on;
628*4882a593Smuzhiyun				regulator-name = "vcc3v3_s3";
629*4882a593Smuzhiyun				regulator-state-mem {
630*4882a593Smuzhiyun					regulator-off-in-suspend;
631*4882a593Smuzhiyun				};
632*4882a593Smuzhiyun			};
633*4882a593Smuzhiyun			vcc3v3_s0: SWITCH_REG2 {
634*4882a593Smuzhiyun				regulator-boot-on;
635*4882a593Smuzhiyun				regulator-always-on;
636*4882a593Smuzhiyun				regulator-name = "vcc3v3_s0";
637*4882a593Smuzhiyun				regulator-state-mem {
638*4882a593Smuzhiyun					regulator-off-in-suspend;
639*4882a593Smuzhiyun				};
640*4882a593Smuzhiyun			};
641*4882a593Smuzhiyun		};
642*4882a593Smuzhiyun	};
643*4882a593Smuzhiyun};
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun&i2c1 {
646*4882a593Smuzhiyun	status = "okay";
647*4882a593Smuzhiyun	i2c-scl-rising-time-ns = <140>;
648*4882a593Smuzhiyun	i2c-scl-falling-time-ns = <30>;
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun	es8316: es8316@11 {
651*4882a593Smuzhiyun		#sound-dai-cells = <0>;
652*4882a593Smuzhiyun		compatible = "everest,es8316";
653*4882a593Smuzhiyun		reg = <0x11>;
654*4882a593Smuzhiyun		clocks = <&cru SCLK_I2S_8CH_OUT>;
655*4882a593Smuzhiyun		clock-names = "mclk";
656*4882a593Smuzhiyun		pinctrl-names = "default";
657*4882a593Smuzhiyun		pinctrl-0 = <&i2s_8ch_mclk>;
658*4882a593Smuzhiyun		spk-con-gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
659*4882a593Smuzhiyun		extcon = <&rk_headset>;
660*4882a593Smuzhiyun	};
661*4882a593Smuzhiyun};
662*4882a593Smuzhiyun
663*4882a593Smuzhiyun&i2c4 {
664*4882a593Smuzhiyun	status = "okay";
665*4882a593Smuzhiyun	i2c-scl-rising-time-ns = <345>;
666*4882a593Smuzhiyun	i2c-scl-falling-time-ns = <11>;
667*4882a593Smuzhiyun	clock-frequency = <100000>;
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun	bq25700: bq25700@6b {
670*4882a593Smuzhiyun		compatible = "ti,bq25703";
671*4882a593Smuzhiyun		reg = <0x6b>;
672*4882a593Smuzhiyun		extcon = <&fusb0>;
673*4882a593Smuzhiyun		interrupt-parent = <&gpio1>;
674*4882a593Smuzhiyun		interrupts = <RK_PC7 IRQ_TYPE_LEVEL_LOW>;
675*4882a593Smuzhiyun		pinctrl-names = "default";
676*4882a593Smuzhiyun		pinctrl-0 = <&charger_ok>;
677*4882a593Smuzhiyun		ti,charge-current = <1500000>;
678*4882a593Smuzhiyun		ti,max-charge-voltage = <8704000>;
679*4882a593Smuzhiyun		ti,max-input-voltage = <20000000>;
680*4882a593Smuzhiyun		ti,max-input-current = <6000000>;
681*4882a593Smuzhiyun		ti,input-current-sdp = <500000>;
682*4882a593Smuzhiyun		ti,input-current-dcp = <2000000>;
683*4882a593Smuzhiyun		ti,input-current-cdp = <2000000>;
684*4882a593Smuzhiyun		ti,input-current-dc = <2000000>;
685*4882a593Smuzhiyun		ti,minimum-sys-voltage = <6700000>;
686*4882a593Smuzhiyun		ti,otg-voltage = <5000000>;
687*4882a593Smuzhiyun		ti,otg-current = <500000>;
688*4882a593Smuzhiyun		ti,input-current = <500000>;
689*4882a593Smuzhiyun		pd-charge-only = <0>;
690*4882a593Smuzhiyun		typec0-enable-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_LOW>;
691*4882a593Smuzhiyun		status = "okay";
692*4882a593Smuzhiyun	};
693*4882a593Smuzhiyun
694*4882a593Smuzhiyun	cw2015: cw2015@62 {
695*4882a593Smuzhiyun		status = "okay";
696*4882a593Smuzhiyun		compatible = "cw201x";
697*4882a593Smuzhiyun		reg = <0x62>;
698*4882a593Smuzhiyun		bat_config_info = <0x15 0xA8 0x5D 0x5D 0x59 0x55 0x57 0x50
699*4882a593Smuzhiyun				   0x4B 0x4F 0x55 0x53 0x43 0x37 0x2F 0x28
700*4882a593Smuzhiyun				   0x21 0x18 0x15 0x17 0x27 0x43 0x57 0x4F
701*4882a593Smuzhiyun				   0x13 0x5E 0x0A 0xE1 0x19 0x31 0x3C 0x46
702*4882a593Smuzhiyun				   0x4C 0x52 0x50 0x54 0x44 0x1E 0x7E 0x4C
703*4882a593Smuzhiyun				   0x1C 0x4A 0x52 0x87 0x8F 0x91 0x94 0x52
704*4882a593Smuzhiyun				   0x82 0x8C 0x92 0x96 0x00 0xAD 0xFB 0xCB
705*4882a593Smuzhiyun				   0x2F 0x7D 0x72 0xA5 0xB5 0xC1 0x1C 0x09>;
706*4882a593Smuzhiyun		monitor_sec = <2>;
707*4882a593Smuzhiyun		virtual_power = <0>;
708*4882a593Smuzhiyun		divider_res1 = <200>;
709*4882a593Smuzhiyun		divider_res2 = <200>;
710*4882a593Smuzhiyun	};
711*4882a593Smuzhiyun
712*4882a593Smuzhiyun	fusb0: fusb30x@22 {
713*4882a593Smuzhiyun		compatible = "fairchild,fusb302";
714*4882a593Smuzhiyun		reg = <0x22>;
715*4882a593Smuzhiyun		pinctrl-names = "default";
716*4882a593Smuzhiyun		pinctrl-0 = <&fusb0_int>;
717*4882a593Smuzhiyun		vbus-5v-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
718*4882a593Smuzhiyun		int-n-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
719*4882a593Smuzhiyun		discharge-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
720*4882a593Smuzhiyun		charge-dev = <&bq25700>;
721*4882a593Smuzhiyun		support-uboot-charge = <1>;
722*4882a593Smuzhiyun		port-num = <0>;
723*4882a593Smuzhiyun		status = "okay";
724*4882a593Smuzhiyun	};
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun	kxtj: kxtj2@0e {
727*4882a593Smuzhiyun		status = "okay";
728*4882a593Smuzhiyun		compatible = "gs_kxtj9";
729*4882a593Smuzhiyun		pinctrl-names = "default";
730*4882a593Smuzhiyun		pinctrl-0 = <&kxtj2_irq_gpio>;
731*4882a593Smuzhiyun		reg = <0x0e>;
732*4882a593Smuzhiyun		irq-gpio = <&gpio1 RK_PC6 IRQ_TYPE_EDGE_RISING>;
733*4882a593Smuzhiyun		type = <SENSOR_TYPE_ACCEL>;
734*4882a593Smuzhiyun		irq_enable = <0>;
735*4882a593Smuzhiyun		poll_delay_ms = <30>;
736*4882a593Smuzhiyun		power-off-in-suspend = <1>;
737*4882a593Smuzhiyun		layout = <5>;
738*4882a593Smuzhiyun	};
739*4882a593Smuzhiyun};
740*4882a593Smuzhiyun
741*4882a593Smuzhiyun&i2c5 {
742*4882a593Smuzhiyun	status = "okay";
743*4882a593Smuzhiyun	i2c-scl-rising-time-ns = <150>;
744*4882a593Smuzhiyun	i2c-scl-falling-time-ns = <30>;
745*4882a593Smuzhiyun	clock-frequency = <100000>;
746*4882a593Smuzhiyun
747*4882a593Smuzhiyun	gslx680: gslx680@40 {
748*4882a593Smuzhiyun		compatible = "gslX680_tve";
749*4882a593Smuzhiyun		reg = <0x40>;
750*4882a593Smuzhiyun		pinctrl-names = "default";
751*4882a593Smuzhiyun		pinctrl-0 = <&tp_irq_gpio>;
752*4882a593Smuzhiyun		touch-gpio = <&gpio3 RK_PB0 IRQ_TYPE_EDGE_RISING>;
753*4882a593Smuzhiyun		reset-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>;
754*4882a593Smuzhiyun		max-x = <1200>;
755*4882a593Smuzhiyun		max-y = <1920>;
756*4882a593Smuzhiyun		tp-size = <80>;
757*4882a593Smuzhiyun		tp-supply = <&vcc3v0_tp>;
758*4882a593Smuzhiyun		status = "okay";
759*4882a593Smuzhiyun	};
760*4882a593Smuzhiyun};
761*4882a593Smuzhiyun
762*4882a593Smuzhiyun&i2s0 {
763*4882a593Smuzhiyun	status = "okay";
764*4882a593Smuzhiyun	rockchip,i2s-broken-burst-len;
765*4882a593Smuzhiyun	rockchip,playback-channels = <8>;
766*4882a593Smuzhiyun	rockchip,capture-channels = <8>;
767*4882a593Smuzhiyun	#sound-dai-cells = <0>;
768*4882a593Smuzhiyun};
769*4882a593Smuzhiyun
770*4882a593Smuzhiyun&i2s2 {
771*4882a593Smuzhiyun	#sound-dai-cells = <0>;
772*4882a593Smuzhiyun	status = "okay";
773*4882a593Smuzhiyun};
774*4882a593Smuzhiyun
775*4882a593Smuzhiyun&io_domains {
776*4882a593Smuzhiyun	status = "okay";
777*4882a593Smuzhiyun	bt656-supply = <&vcc1v8_dvp>;
778*4882a593Smuzhiyun	audio-supply = <&vcca1v8_codec>;
779*4882a593Smuzhiyun	sdmmc-supply = <&vcc_sd>;
780*4882a593Smuzhiyun	gpio1830-supply = <&vcc_3v0>;
781*4882a593Smuzhiyun};
782*4882a593Smuzhiyun
783*4882a593Smuzhiyun&isp0_mmu {
784*4882a593Smuzhiyun	status = "okay";
785*4882a593Smuzhiyun};
786*4882a593Smuzhiyun
787*4882a593Smuzhiyun&isp1_mmu {
788*4882a593Smuzhiyun	status = "okay";
789*4882a593Smuzhiyun};
790*4882a593Smuzhiyun
791*4882a593Smuzhiyun&pinctrl {
792*4882a593Smuzhiyun
793*4882a593Smuzhiyun	charger {
794*4882a593Smuzhiyun		charger_ok: charge-ok {
795*4882a593Smuzhiyun			rockchip,pins =
796*4882a593Smuzhiyun				<1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
797*4882a593Smuzhiyun		};
798*4882a593Smuzhiyun	};
799*4882a593Smuzhiyun
800*4882a593Smuzhiyun	fusb30x {
801*4882a593Smuzhiyun		fusb0_int: fusb0-int {
802*4882a593Smuzhiyun			rockchip,pins =
803*4882a593Smuzhiyun				<1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
804*4882a593Smuzhiyun				<0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
805*4882a593Smuzhiyun			};
806*4882a593Smuzhiyun	};
807*4882a593Smuzhiyun
808*4882a593Smuzhiyun	headphone {
809*4882a593Smuzhiyun		hp_det: hp-det {
810*4882a593Smuzhiyun			rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
811*4882a593Smuzhiyun		};
812*4882a593Smuzhiyun	};
813*4882a593Smuzhiyun
814*4882a593Smuzhiyun	kxtj2 {
815*4882a593Smuzhiyun		kxtj2_irq_gpio: kxtj2-irq-gpio {
816*4882a593Smuzhiyun			rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
817*4882a593Smuzhiyun		};
818*4882a593Smuzhiyun	};
819*4882a593Smuzhiyun
820*4882a593Smuzhiyun	lcd_rst {
821*4882a593Smuzhiyun		lcd_rst_gpio: lcd-rst-gpio {
822*4882a593Smuzhiyun			rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
823*4882a593Smuzhiyun		};
824*4882a593Smuzhiyun	};
825*4882a593Smuzhiyun
826*4882a593Smuzhiyun	pmic {
827*4882a593Smuzhiyun		pmic_int_l: pmic-int-l {
828*4882a593Smuzhiyun			rockchip,pins =
829*4882a593Smuzhiyun				<1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
830*4882a593Smuzhiyun		};
831*4882a593Smuzhiyun		vsel1_gpio: vsel1-gpio {
832*4882a593Smuzhiyun			rockchip,pins =
833*4882a593Smuzhiyun				<1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
834*4882a593Smuzhiyun		};
835*4882a593Smuzhiyun		vsel2_gpio: vsel2-gpio {
836*4882a593Smuzhiyun			rockchip,pins =
837*4882a593Smuzhiyun				<1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
838*4882a593Smuzhiyun		};
839*4882a593Smuzhiyun	};
840*4882a593Smuzhiyun
841*4882a593Smuzhiyun	sdio-pwrseq {
842*4882a593Smuzhiyun		wifi_enable_h: wifi-enable-h {
843*4882a593Smuzhiyun			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
844*4882a593Smuzhiyun		};
845*4882a593Smuzhiyun	};
846*4882a593Smuzhiyun
847*4882a593Smuzhiyun	tp_irq {
848*4882a593Smuzhiyun		tp_irq_gpio: tp-irq-gpio {
849*4882a593Smuzhiyun			rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
850*4882a593Smuzhiyun		};
851*4882a593Smuzhiyun	};
852*4882a593Smuzhiyun
853*4882a593Smuzhiyun	usb2 {
854*4882a593Smuzhiyun		host_vbus_drv: host-vbus-drv {
855*4882a593Smuzhiyun			rockchip,pins =
856*4882a593Smuzhiyun				<4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
857*4882a593Smuzhiyun		};
858*4882a593Smuzhiyun	};
859*4882a593Smuzhiyun
860*4882a593Smuzhiyun	wireless-bluetooth {
861*4882a593Smuzhiyun		uart0_gpios: uart0-gpios {
862*4882a593Smuzhiyun			rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
863*4882a593Smuzhiyun		};
864*4882a593Smuzhiyun
865*4882a593Smuzhiyun		bt_reset_gpio: bt-reset-gpio {
866*4882a593Smuzhiyun			rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
867*4882a593Smuzhiyun		};
868*4882a593Smuzhiyun
869*4882a593Smuzhiyun		bt_wake_gpio: bt-wake-gpio {
870*4882a593Smuzhiyun			rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
871*4882a593Smuzhiyun		};
872*4882a593Smuzhiyun
873*4882a593Smuzhiyun		bt_irq_gpio: bt-irq-gpio {
874*4882a593Smuzhiyun			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>;
875*4882a593Smuzhiyun		};
876*4882a593Smuzhiyun	};
877*4882a593Smuzhiyun};
878*4882a593Smuzhiyun
879*4882a593Smuzhiyun&pmu_io_domains {
880*4882a593Smuzhiyun	status = "okay";
881*4882a593Smuzhiyun	pmu1830-supply = <&vcc_1v8>;
882*4882a593Smuzhiyun};
883*4882a593Smuzhiyun
884*4882a593Smuzhiyun&pwm0 {
885*4882a593Smuzhiyun	status = "okay";
886*4882a593Smuzhiyun};
887*4882a593Smuzhiyun
888*4882a593Smuzhiyun&pwm2 {
889*4882a593Smuzhiyun	status = "okay";
890*4882a593Smuzhiyun	pinctrl-names = "active";
891*4882a593Smuzhiyun	pinctrl-0 = <&pwm2_pin_pull_down>;
892*4882a593Smuzhiyun};
893*4882a593Smuzhiyun
894*4882a593Smuzhiyun&rockchip_suspend {
895*4882a593Smuzhiyun	status = "okay";
896*4882a593Smuzhiyun	rockchip,sleep-debug-en = <1>;
897*4882a593Smuzhiyun	rockchip,sleep-mode-config = <
898*4882a593Smuzhiyun		(0
899*4882a593Smuzhiyun		| RKPM_SLP_ARMPD
900*4882a593Smuzhiyun		| RKPM_SLP_PERILPPD
901*4882a593Smuzhiyun		| RKPM_SLP_DDR_RET
902*4882a593Smuzhiyun		| RKPM_SLP_PLLPD
903*4882a593Smuzhiyun		| RKPM_SLP_CENTER_PD
904*4882a593Smuzhiyun		| RKPM_SLP_OSC_DIS
905*4882a593Smuzhiyun		| RKPM_SLP_AP_PWROFF
906*4882a593Smuzhiyun		)
907*4882a593Smuzhiyun	>;
908*4882a593Smuzhiyun	rockchip,wakeup-config = <
909*4882a593Smuzhiyun		(0
910*4882a593Smuzhiyun		| RKPM_GPIO_WKUP_EN
911*4882a593Smuzhiyun		)
912*4882a593Smuzhiyun	>;
913*4882a593Smuzhiyun	rockchip,pwm-regulator-config = <
914*4882a593Smuzhiyun		(0
915*4882a593Smuzhiyun		| PWM2_REGULATOR_EN
916*4882a593Smuzhiyun		)
917*4882a593Smuzhiyun	>;
918*4882a593Smuzhiyun	rockchip,power-ctrl =
919*4882a593Smuzhiyun		<&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>,
920*4882a593Smuzhiyun		<&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>;
921*4882a593Smuzhiyun};
922*4882a593Smuzhiyun
923*4882a593Smuzhiyun&route_dsi {
924*4882a593Smuzhiyun	status = "okay";
925*4882a593Smuzhiyun	logo,mode = "center";
926*4882a593Smuzhiyun};
927*4882a593Smuzhiyun
928*4882a593Smuzhiyun&saradc {
929*4882a593Smuzhiyun	status = "okay";
930*4882a593Smuzhiyun};
931*4882a593Smuzhiyun
932*4882a593Smuzhiyun&sdhci {
933*4882a593Smuzhiyun	bus-width = <8>;
934*4882a593Smuzhiyun	mmc-hs400-1_8v;
935*4882a593Smuzhiyun	no-sdio;
936*4882a593Smuzhiyun	no-sd;
937*4882a593Smuzhiyun	non-removable;
938*4882a593Smuzhiyun	keep-power-in-suspend;
939*4882a593Smuzhiyun	mmc-hs400-enhanced-strobe;
940*4882a593Smuzhiyun	status = "okay";
941*4882a593Smuzhiyun};
942*4882a593Smuzhiyun
943*4882a593Smuzhiyun&sdio0 {
944*4882a593Smuzhiyun	clock-frequency = <100000000>;
945*4882a593Smuzhiyun	clock-freq-min-max = <200000 100000000>;
946*4882a593Smuzhiyun	no-sd;
947*4882a593Smuzhiyun	no-mmc;
948*4882a593Smuzhiyun	bus-width = <4>;
949*4882a593Smuzhiyun	disable-wp;
950*4882a593Smuzhiyun	cap-sd-highspeed;
951*4882a593Smuzhiyun	cap-sdio-irq;
952*4882a593Smuzhiyun	keep-power-in-suspend;
953*4882a593Smuzhiyun	mmc-pwrseq = <&sdio_pwrseq>;
954*4882a593Smuzhiyun	non-removable;
955*4882a593Smuzhiyun	num-slots = <1>;
956*4882a593Smuzhiyun	pinctrl-names = "default";
957*4882a593Smuzhiyun	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
958*4882a593Smuzhiyun	sd-uhs-sdr104;
959*4882a593Smuzhiyun	status = "okay";
960*4882a593Smuzhiyun};
961*4882a593Smuzhiyun
962*4882a593Smuzhiyun&sdmmc {
963*4882a593Smuzhiyun	clock-frequency = <50000000>;
964*4882a593Smuzhiyun	clock-freq-min-max = <400000 150000000>;
965*4882a593Smuzhiyun	no-sdio;
966*4882a593Smuzhiyun	no-mmc;
967*4882a593Smuzhiyun	bus-width = <4>;
968*4882a593Smuzhiyun	cap-mmc-highspeed;
969*4882a593Smuzhiyun	cap-sd-highspeed;
970*4882a593Smuzhiyun	disable-wp;
971*4882a593Smuzhiyun	num-slots = <1>;
972*4882a593Smuzhiyun	//sd-uhs-sdr104;
973*4882a593Smuzhiyun	vqmmc-supply = <&vcc_sd>;
974*4882a593Smuzhiyun	pinctrl-names = "default";
975*4882a593Smuzhiyun	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
976*4882a593Smuzhiyun	status = "okay";
977*4882a593Smuzhiyun};
978*4882a593Smuzhiyun
979*4882a593Smuzhiyun&tcphy0 {
980*4882a593Smuzhiyun	extcon = <&fusb0>;
981*4882a593Smuzhiyun	status = "okay";
982*4882a593Smuzhiyun};
983*4882a593Smuzhiyun
984*4882a593Smuzhiyun&tsadc {
985*4882a593Smuzhiyun	rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
986*4882a593Smuzhiyun	rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
987*4882a593Smuzhiyun	status = "okay";
988*4882a593Smuzhiyun};
989*4882a593Smuzhiyun
990*4882a593Smuzhiyun&u2phy0 {
991*4882a593Smuzhiyun	status = "okay";
992*4882a593Smuzhiyun	extcon = <&fusb0>;
993*4882a593Smuzhiyun
994*4882a593Smuzhiyun	u2phy0_otg: otg-port {
995*4882a593Smuzhiyun		status = "okay";
996*4882a593Smuzhiyun	};
997*4882a593Smuzhiyun
998*4882a593Smuzhiyun	u2phy0_host: host-port {
999*4882a593Smuzhiyun		phy-supply = <&vcc5v0_host>;
1000*4882a593Smuzhiyun		status = "okay";
1001*4882a593Smuzhiyun	};
1002*4882a593Smuzhiyun};
1003*4882a593Smuzhiyun
1004*4882a593Smuzhiyun&uart0 {
1005*4882a593Smuzhiyun	pinctrl-names = "default";
1006*4882a593Smuzhiyun	pinctrl-0 = <&uart0_xfer &uart0_cts>;
1007*4882a593Smuzhiyun	status = "okay";
1008*4882a593Smuzhiyun};
1009*4882a593Smuzhiyun
1010*4882a593Smuzhiyun&uart2 {
1011*4882a593Smuzhiyun	status = "disabled";
1012*4882a593Smuzhiyun};
1013*4882a593Smuzhiyun
1014*4882a593Smuzhiyun&usb_host0_ehci {
1015*4882a593Smuzhiyun	status = "okay";
1016*4882a593Smuzhiyun};
1017*4882a593Smuzhiyun
1018*4882a593Smuzhiyun&usb_host0_ohci {
1019*4882a593Smuzhiyun	status = "okay";
1020*4882a593Smuzhiyun};
1021*4882a593Smuzhiyun
1022*4882a593Smuzhiyun&usbdrd3_0 {
1023*4882a593Smuzhiyun	status = "okay";
1024*4882a593Smuzhiyun};
1025*4882a593Smuzhiyun
1026*4882a593Smuzhiyun&usbdrd_dwc3_0 {
1027*4882a593Smuzhiyun	status = "okay";
1028*4882a593Smuzhiyun	extcon = <&fusb0>;
1029*4882a593Smuzhiyun};
1030*4882a593Smuzhiyun
1031*4882a593Smuzhiyun&vopb {
1032*4882a593Smuzhiyun	assigned-clocks = <&cru DCLK_VOP0_DIV>;
1033*4882a593Smuzhiyun	assigned-clock-parents = <&cru PLL_CPLL>;
1034*4882a593Smuzhiyun};
1035*4882a593Smuzhiyun
1036*4882a593Smuzhiyun&vopl {
1037*4882a593Smuzhiyun	assigned-clocks = <&cru DCLK_VOP1_DIV>;
1038*4882a593Smuzhiyun	assigned-clock-parents = <&cru PLL_VPLL>;
1039*4882a593Smuzhiyun};
1040