1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h> 9*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 10*4882a593Smuzhiyun#include "rk3399.dtsi" 11*4882a593Smuzhiyun#include "rk3399-linux.dtsi" 12*4882a593Smuzhiyun#include "rk3399-opp.dtsi" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun/ { 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun model = "ROCK960 - 96boards based on Rockchip RK3399"; 17*4882a593Smuzhiyun compatible = "rockchip,rock960","rockchip,rk3399"; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun fiq_debugger: fiq-debugger { 20*4882a593Smuzhiyun compatible = "rockchip,fiq-debugger"; 21*4882a593Smuzhiyun rockchip,serial-id = <2>; 22*4882a593Smuzhiyun rockchip,signal-irq = <182>; 23*4882a593Smuzhiyun rockchip,wake-irq = <0>; 24*4882a593Smuzhiyun rockchip,irq-mode-enable = <1>; 25*4882a593Smuzhiyun rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ 26*4882a593Smuzhiyun pinctrl-names = "default"; 27*4882a593Smuzhiyun pinctrl-0 = <&uart2c_xfer>; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun vcc1v8_s0: vcc1v8-s0 { 31*4882a593Smuzhiyun compatible = "regulator-fixed"; 32*4882a593Smuzhiyun regulator-name = "vcc1v8_s0"; 33*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 34*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 35*4882a593Smuzhiyun regulator-always-on; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun vcc_sys: vcc-sys { 39*4882a593Smuzhiyun compatible = "regulator-fixed"; 40*4882a593Smuzhiyun regulator-name = "vcc_sys"; 41*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 42*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 43*4882a593Smuzhiyun regulator-always-on; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun vcc_phy: vcc-phy-regulator { 47*4882a593Smuzhiyun compatible = "regulator-fixed"; 48*4882a593Smuzhiyun regulator-name = "vcc_phy"; 49*4882a593Smuzhiyun regulator-always-on; 50*4882a593Smuzhiyun regulator-boot-on; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun vcc3v3_sys: vcc3v3-sys { 54*4882a593Smuzhiyun compatible = "regulator-fixed"; 55*4882a593Smuzhiyun regulator-name = "vcc3v3_sys"; 56*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 57*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 58*4882a593Smuzhiyun regulator-always-on; 59*4882a593Smuzhiyun vin-supply = <&vcc_sys>; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun vcc3v3_pcie: vcc3v3-pcie-regulator { 63*4882a593Smuzhiyun compatible = "regulator-fixed"; 64*4882a593Smuzhiyun gpio = <&gpio3 11 GPIO_ACTIVE_LOW>; 65*4882a593Smuzhiyun pinctrl-names = "default"; 66*4882a593Smuzhiyun pinctrl-0 = <&pcie_drv>; 67*4882a593Smuzhiyun regulator-boot-on; 68*4882a593Smuzhiyun regulator-always-on; 69*4882a593Smuzhiyun regulator-name = "vcc3v3_pcie"; 70*4882a593Smuzhiyun vin-supply = <&vcc3v3_sys>; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun vcc5v0_host: vcc5v0-host-regulator { 74*4882a593Smuzhiyun compatible = "regulator-fixed"; 75*4882a593Smuzhiyun enable-active-high; 76*4882a593Smuzhiyun gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; 77*4882a593Smuzhiyun pinctrl-names = "default"; 78*4882a593Smuzhiyun pinctrl-0 = <&host_vbus_drv>; 79*4882a593Smuzhiyun regulator-name = "vcc5v0_host"; 80*4882a593Smuzhiyun regulator-always-on; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun vdd_log: vdd-log { 84*4882a593Smuzhiyun compatible = "pwm-regulator"; 85*4882a593Smuzhiyun pwms = <&pwm2 0 25000 1>; 86*4882a593Smuzhiyun regulator-name = "vdd_log"; 87*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 88*4882a593Smuzhiyun regulator-max-microvolt = <1400000>; 89*4882a593Smuzhiyun regulator-always-on; 90*4882a593Smuzhiyun regulator-boot-on; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* for rockchip boot on */ 93*4882a593Smuzhiyun rockchip,pwm_id= <2>; 94*4882a593Smuzhiyun rockchip,pwm_voltage = <900000>; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun vin-supply = <&vcc_sys>; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun clkin_gmac: external-gmac-clock { 100*4882a593Smuzhiyun compatible = "fixed-clock"; 101*4882a593Smuzhiyun clock-frequency = <125000000>; 102*4882a593Smuzhiyun clock-output-names = "clkin_gmac"; 103*4882a593Smuzhiyun #clock-cells = <0>; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun hdmi_codec: hdmi-codec { 107*4882a593Smuzhiyun compatible = "simple-audio-card"; 108*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 109*4882a593Smuzhiyun simple-audio-card,mclk-fs = <256>; 110*4882a593Smuzhiyun simple-audio-card,name = "HDMI-CODEC"; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun simple-audio-card,cpu { 113*4882a593Smuzhiyun sound-dai = <&i2s2>; 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun simple-audio-card,codec { 117*4882a593Smuzhiyun sound-dai = <&hdmi>; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun spdif-sound { 122*4882a593Smuzhiyun status = "okay"; 123*4882a593Smuzhiyun compatible = "simple-audio-card"; 124*4882a593Smuzhiyun simple-audio-card,name = "ROCKCHIP,SPDIF"; 125*4882a593Smuzhiyun simple-audio-card,mclk-fs = <128>; 126*4882a593Smuzhiyun simple-audio-card,cpu { 127*4882a593Smuzhiyun sound-dai = <&spdif>; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun simple-audio-card,codec { 130*4882a593Smuzhiyun sound-dai = <&spdif_out>; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun spdif_out: spdif-out { 135*4882a593Smuzhiyun status = "okay"; 136*4882a593Smuzhiyun compatible = "linux,spdif-dit"; 137*4882a593Smuzhiyun #sound-dai-cells = <0>; 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun sdio_pwrseq: sdio-pwrseq { 141*4882a593Smuzhiyun compatible = "mmc-pwrseq-simple"; 142*4882a593Smuzhiyun clocks = <&rk808 1>; 143*4882a593Smuzhiyun clock-names = "ext_clock"; 144*4882a593Smuzhiyun pinctrl-names = "default"; 145*4882a593Smuzhiyun pinctrl-0 = <&wifi_enable_h>; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun /* 148*4882a593Smuzhiyun * On the module itself this is one of these (depending 149*4882a593Smuzhiyun * on the actual card populated): 150*4882a593Smuzhiyun * - SDIO_RESET_L_WL_REG_ON 151*4882a593Smuzhiyun * - PDN (power down when low) 152*4882a593Smuzhiyun */ 153*4882a593Smuzhiyun reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun wireless-wlan { 157*4882a593Smuzhiyun compatible = "wlan-platdata"; 158*4882a593Smuzhiyun rockchip,grf = <&grf>; 159*4882a593Smuzhiyun wifi_chip_type = "ap6354"; 160*4882a593Smuzhiyun sdio_vref = <1800>; 161*4882a593Smuzhiyun WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; 162*4882a593Smuzhiyun status = "okay"; 163*4882a593Smuzhiyun }; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun wireless-bluetooth { 166*4882a593Smuzhiyun compatible = "bluetooth-platdata"; 167*4882a593Smuzhiyun clocks = <&rk808 1>; 168*4882a593Smuzhiyun clock-names = "ext_clock"; 169*4882a593Smuzhiyun /* wifi-bt-power-toggle; */ 170*4882a593Smuzhiyun uart_rts_gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; 171*4882a593Smuzhiyun pinctrl-names = "default", "rts_gpio"; 172*4882a593Smuzhiyun pinctrl-0 = <&uart0_rts>; 173*4882a593Smuzhiyun pinctrl-1 = <&uart0_gpios>; 174*4882a593Smuzhiyun /* BT,power_gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; */ 175*4882a593Smuzhiyun BT,reset_gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; 176*4882a593Smuzhiyun BT,wake_gpio = <&gpio2 27 GPIO_ACTIVE_HIGH>; 177*4882a593Smuzhiyun BT,wake_host_irq = <&gpio0 4 GPIO_ACTIVE_HIGH>; 178*4882a593Smuzhiyun status = "okay"; 179*4882a593Smuzhiyun }; 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun test-power { 182*4882a593Smuzhiyun status = "okay"; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun}; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun&hdmi { 187*4882a593Smuzhiyun #address-cells = <1>; 188*4882a593Smuzhiyun #size-cells = <0>; 189*4882a593Smuzhiyun #sound-dai-cells = <0>; 190*4882a593Smuzhiyun status = "okay"; 191*4882a593Smuzhiyun}; 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun&sdmmc { 194*4882a593Smuzhiyun clock-frequency = <100000000>; 195*4882a593Smuzhiyun clock-freq-min-max = <100000 100000000>; 196*4882a593Smuzhiyun no-sdio; 197*4882a593Smuzhiyun no-mmc; 198*4882a593Smuzhiyun bus-width = <4>; 199*4882a593Smuzhiyun cap-mmc-highspeed; 200*4882a593Smuzhiyun cap-sd-highspeed; 201*4882a593Smuzhiyun disable-wp; 202*4882a593Smuzhiyun num-slots = <1>; 203*4882a593Smuzhiyun //sd-uhs-sdr104; 204*4882a593Smuzhiyun vqmmc-supply = <&vcc_sd>; 205*4882a593Smuzhiyun pinctrl-names = "default"; 206*4882a593Smuzhiyun pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; 207*4882a593Smuzhiyun card-detect-delay = <800>; 208*4882a593Smuzhiyun status = "okay"; 209*4882a593Smuzhiyun}; 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun&sdio0 { 212*4882a593Smuzhiyun clock-frequency = <100000000>; 213*4882a593Smuzhiyun clock-freq-min-max = <200000 100000000>; 214*4882a593Smuzhiyun no-sd; 215*4882a593Smuzhiyun no-mmc; 216*4882a593Smuzhiyun bus-width = <4>; 217*4882a593Smuzhiyun disable-wp; 218*4882a593Smuzhiyun cap-sd-highspeed; 219*4882a593Smuzhiyun cap-sdio-irq; 220*4882a593Smuzhiyun keep-power-in-suspend; 221*4882a593Smuzhiyun mmc-pwrseq = <&sdio_pwrseq>; 222*4882a593Smuzhiyun non-removable; 223*4882a593Smuzhiyun num-slots = <1>; 224*4882a593Smuzhiyun pinctrl-names = "default"; 225*4882a593Smuzhiyun pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; 226*4882a593Smuzhiyun sd-uhs-sdr104; 227*4882a593Smuzhiyun status = "okay"; 228*4882a593Smuzhiyun}; 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun&emmc_phy { 231*4882a593Smuzhiyun status = "okay"; 232*4882a593Smuzhiyun}; 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun&sdhci { 235*4882a593Smuzhiyun bus-width = <8>; 236*4882a593Smuzhiyun mmc-hs400-1_8v; 237*4882a593Smuzhiyun no-sdio; 238*4882a593Smuzhiyun no-sd; 239*4882a593Smuzhiyun non-removable; 240*4882a593Smuzhiyun mmc-hs400-enhanced-strobe; 241*4882a593Smuzhiyun status = "okay"; 242*4882a593Smuzhiyun}; 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun&i2s0 { 245*4882a593Smuzhiyun status = "okay"; 246*4882a593Smuzhiyun rockchip,i2s-broken-burst-len; 247*4882a593Smuzhiyun rockchip,playback-channels = <8>; 248*4882a593Smuzhiyun rockchip,capture-channels = <8>; 249*4882a593Smuzhiyun #sound-dai-cells = <0>; 250*4882a593Smuzhiyun}; 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun&i2s2 { 253*4882a593Smuzhiyun status = "okay"; 254*4882a593Smuzhiyun #sound-dai-cells = <0>; 255*4882a593Smuzhiyun}; 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun&spdif { 258*4882a593Smuzhiyun pinctrl-0 = <&spdif_bus_1>; 259*4882a593Smuzhiyun status = "okay"; 260*4882a593Smuzhiyun #sound-dai-cells = <0>; 261*4882a593Smuzhiyun}; 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun&i2c0 { 264*4882a593Smuzhiyun status = "okay"; 265*4882a593Smuzhiyun i2c-scl-rising-time-ns = <168>; 266*4882a593Smuzhiyun i2c-scl-falling-time-ns = <4>; 267*4882a593Smuzhiyun clock-frequency = <400000>; 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun vdd_cpu_b: syr827@40 { 270*4882a593Smuzhiyun compatible = "silergy,syr827"; 271*4882a593Smuzhiyun reg = <0x40>; 272*4882a593Smuzhiyun regulator-compatible = "fan53555-reg"; 273*4882a593Smuzhiyun pinctrl-0 = <&vsel1_gpio>; 274*4882a593Smuzhiyun vsel-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; 275*4882a593Smuzhiyun regulator-name = "vdd_cpu_b"; 276*4882a593Smuzhiyun regulator-min-microvolt = <712500>; 277*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 278*4882a593Smuzhiyun regulator-ramp-delay = <1000>; 279*4882a593Smuzhiyun fcs,suspend-voltage-selector = <1>; 280*4882a593Smuzhiyun regulator-always-on; 281*4882a593Smuzhiyun regulator-boot-on; 282*4882a593Smuzhiyun vin-supply = <&vcc_sys>; 283*4882a593Smuzhiyun regulator-state-mem { 284*4882a593Smuzhiyun regulator-off-in-suspend; 285*4882a593Smuzhiyun }; 286*4882a593Smuzhiyun }; 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun vdd_gpu: syr828@41 { 289*4882a593Smuzhiyun compatible = "silergy,syr828"; 290*4882a593Smuzhiyun reg = <0x41>; 291*4882a593Smuzhiyun regulator-compatible = "fan53555-reg"; 292*4882a593Smuzhiyun pinctrl-0 = <&vsel2_gpio>; 293*4882a593Smuzhiyun vsel-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; 294*4882a593Smuzhiyun regulator-name = "vdd_gpu"; 295*4882a593Smuzhiyun regulator-min-microvolt = <712500>; 296*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 297*4882a593Smuzhiyun regulator-ramp-delay = <1000>; 298*4882a593Smuzhiyun fcs,suspend-voltage-selector = <1>; 299*4882a593Smuzhiyun regulator-always-on; 300*4882a593Smuzhiyun regulator-boot-on; 301*4882a593Smuzhiyun vin-supply = <&vcc_sys>; 302*4882a593Smuzhiyun regulator-initial-mode = <1>; /* 1:force PWM 2:auto */ 303*4882a593Smuzhiyun regulator-state-mem { 304*4882a593Smuzhiyun regulator-off-in-suspend; 305*4882a593Smuzhiyun }; 306*4882a593Smuzhiyun }; 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun rk808: pmic@1b { 309*4882a593Smuzhiyun compatible = "rockchip,rk808"; 310*4882a593Smuzhiyun reg = <0x1b>; 311*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 312*4882a593Smuzhiyun interrupts = <21 IRQ_TYPE_LEVEL_LOW>; 313*4882a593Smuzhiyun pinctrl-names = "default"; 314*4882a593Smuzhiyun pinctrl-0 = <&pmic_int_l>; 315*4882a593Smuzhiyun rockchip,system-power-controller; 316*4882a593Smuzhiyun wakeup-source; 317*4882a593Smuzhiyun #clock-cells = <1>; 318*4882a593Smuzhiyun clock-output-names = "xin32k", "rk808-clkout2"; 319*4882a593Smuzhiyun 320*4882a593Smuzhiyun vcc1-supply = <&vcc_sys>; 321*4882a593Smuzhiyun vcc2-supply = <&vcc_sys>; 322*4882a593Smuzhiyun vcc3-supply = <&vcc_sys>; 323*4882a593Smuzhiyun vcc4-supply = <&vcc_sys>; 324*4882a593Smuzhiyun vcc6-supply = <&vcc_sys>; 325*4882a593Smuzhiyun vcc7-supply = <&vcc_sys>; 326*4882a593Smuzhiyun vcc8-supply = <&vcc3v3_sys>; 327*4882a593Smuzhiyun vcc9-supply = <&vcc_sys>; 328*4882a593Smuzhiyun vcc10-supply = <&vcc_sys>; 329*4882a593Smuzhiyun vcc11-supply = <&vcc_sys>; 330*4882a593Smuzhiyun vcc12-supply = <&vcc3v3_sys>; 331*4882a593Smuzhiyun vddio-supply = <&vcc_1v8>; 332*4882a593Smuzhiyun 333*4882a593Smuzhiyun regulators { 334*4882a593Smuzhiyun vdd_center: DCDC_REG1 { 335*4882a593Smuzhiyun regulator-name = "vdd_center"; 336*4882a593Smuzhiyun regulator-min-microvolt = <750000>; 337*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 338*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 339*4882a593Smuzhiyun regulator-always-on; 340*4882a593Smuzhiyun regulator-boot-on; 341*4882a593Smuzhiyun regulator-state-mem { 342*4882a593Smuzhiyun regulator-off-in-suspend; 343*4882a593Smuzhiyun }; 344*4882a593Smuzhiyun }; 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun vdd_cpu_l: DCDC_REG2 { 347*4882a593Smuzhiyun regulator-name = "vdd_cpu_l"; 348*4882a593Smuzhiyun regulator-min-microvolt = <750000>; 349*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 350*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 351*4882a593Smuzhiyun regulator-always-on; 352*4882a593Smuzhiyun regulator-boot-on; 353*4882a593Smuzhiyun regulator-state-mem { 354*4882a593Smuzhiyun regulator-off-in-suspend; 355*4882a593Smuzhiyun }; 356*4882a593Smuzhiyun }; 357*4882a593Smuzhiyun 358*4882a593Smuzhiyun vcc_ddr: DCDC_REG3 { 359*4882a593Smuzhiyun regulator-name = "vcc_ddr"; 360*4882a593Smuzhiyun regulator-always-on; 361*4882a593Smuzhiyun regulator-boot-on; 362*4882a593Smuzhiyun regulator-state-mem { 363*4882a593Smuzhiyun regulator-on-in-suspend; 364*4882a593Smuzhiyun }; 365*4882a593Smuzhiyun }; 366*4882a593Smuzhiyun 367*4882a593Smuzhiyun vcc_1v8: DCDC_REG4 { 368*4882a593Smuzhiyun regulator-name = "vcc_1v8"; 369*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 370*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 371*4882a593Smuzhiyun regulator-always-on; 372*4882a593Smuzhiyun regulator-boot-on; 373*4882a593Smuzhiyun regulator-state-mem { 374*4882a593Smuzhiyun regulator-on-in-suspend; 375*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 376*4882a593Smuzhiyun }; 377*4882a593Smuzhiyun }; 378*4882a593Smuzhiyun 379*4882a593Smuzhiyun vcc1v8_dvp: LDO_REG1 { 380*4882a593Smuzhiyun regulator-name = "vcc1v8_dvp"; 381*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 382*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 383*4882a593Smuzhiyun regulator-always-on; 384*4882a593Smuzhiyun regulator-boot-on; 385*4882a593Smuzhiyun regulator-state-mem { 386*4882a593Smuzhiyun regulator-on-in-suspend; 387*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 388*4882a593Smuzhiyun }; 389*4882a593Smuzhiyun }; 390*4882a593Smuzhiyun 391*4882a593Smuzhiyun vcca1v8_hdmi: LDO_REG2 { 392*4882a593Smuzhiyun regulator-name = "vcca1v8_hdmi"; 393*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 394*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 395*4882a593Smuzhiyun regulator-always-on; 396*4882a593Smuzhiyun regulator-boot-on; 397*4882a593Smuzhiyun regulator-state-mem { 398*4882a593Smuzhiyun regulator-on-in-suspend; 399*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 400*4882a593Smuzhiyun }; 401*4882a593Smuzhiyun }; 402*4882a593Smuzhiyun 403*4882a593Smuzhiyun vcca_1v8: LDO_REG3 { 404*4882a593Smuzhiyun regulator-name = "vcca_1v8"; 405*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 406*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 407*4882a593Smuzhiyun regulator-always-on; 408*4882a593Smuzhiyun regulator-boot-on; 409*4882a593Smuzhiyun regulator-state-mem { 410*4882a593Smuzhiyun regulator-on-in-suspend; 411*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 412*4882a593Smuzhiyun }; 413*4882a593Smuzhiyun }; 414*4882a593Smuzhiyun 415*4882a593Smuzhiyun vcc_sd: LDO_REG4 { 416*4882a593Smuzhiyun regulator-name = "vcc_sd"; 417*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 418*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 419*4882a593Smuzhiyun regulator-always-on; 420*4882a593Smuzhiyun regulator-boot-on; 421*4882a593Smuzhiyun regulator-state-mem { 422*4882a593Smuzhiyun regulator-on-in-suspend; 423*4882a593Smuzhiyun regulator-suspend-microvolt = <3000000>; 424*4882a593Smuzhiyun }; 425*4882a593Smuzhiyun }; 426*4882a593Smuzhiyun 427*4882a593Smuzhiyun vcc3v0_sd: LDO_REG5 { 428*4882a593Smuzhiyun regulator-name = "vcc3v0_sd"; 429*4882a593Smuzhiyun regulator-min-microvolt = <3000000>; 430*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 431*4882a593Smuzhiyun regulator-always-on; 432*4882a593Smuzhiyun regulator-boot-on; 433*4882a593Smuzhiyun regulator-state-mem { 434*4882a593Smuzhiyun regulator-on-in-suspend; 435*4882a593Smuzhiyun regulator-suspend-microvolt = <3000000>; 436*4882a593Smuzhiyun }; 437*4882a593Smuzhiyun }; 438*4882a593Smuzhiyun 439*4882a593Smuzhiyun vcc_1v5: LDO_REG6 { 440*4882a593Smuzhiyun regulator-name = "vcc_1v5"; 441*4882a593Smuzhiyun regulator-min-microvolt = <1500000>; 442*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 443*4882a593Smuzhiyun regulator-always-on; 444*4882a593Smuzhiyun regulator-boot-on; 445*4882a593Smuzhiyun regulator-state-mem { 446*4882a593Smuzhiyun regulator-on-in-suspend; 447*4882a593Smuzhiyun regulator-suspend-microvolt = <1500000>; 448*4882a593Smuzhiyun }; 449*4882a593Smuzhiyun }; 450*4882a593Smuzhiyun 451*4882a593Smuzhiyun vcca0v9_hdmi: LDO_REG7 { 452*4882a593Smuzhiyun regulator-name = "vcca0v9_hdmi"; 453*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 454*4882a593Smuzhiyun regulator-max-microvolt = <900000>; 455*4882a593Smuzhiyun regulator-always-on; 456*4882a593Smuzhiyun regulator-boot-on; 457*4882a593Smuzhiyun regulator-state-mem { 458*4882a593Smuzhiyun regulator-on-in-suspend; 459*4882a593Smuzhiyun regulator-suspend-microvolt = <900000>; 460*4882a593Smuzhiyun }; 461*4882a593Smuzhiyun }; 462*4882a593Smuzhiyun 463*4882a593Smuzhiyun vcc_3v0: LDO_REG8 { 464*4882a593Smuzhiyun regulator-name = "vcc_3v0"; 465*4882a593Smuzhiyun regulator-min-microvolt = <3000000>; 466*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 467*4882a593Smuzhiyun regulator-always-on; 468*4882a593Smuzhiyun regulator-boot-on; 469*4882a593Smuzhiyun regulator-state-mem { 470*4882a593Smuzhiyun regulator-on-in-suspend; 471*4882a593Smuzhiyun regulator-suspend-microvolt = <3000000>; 472*4882a593Smuzhiyun }; 473*4882a593Smuzhiyun }; 474*4882a593Smuzhiyun 475*4882a593Smuzhiyun vcc3v3_s3: SWITCH_REG1 { 476*4882a593Smuzhiyun regulator-name = "vcc3v3_s3"; 477*4882a593Smuzhiyun regulator-always-on; 478*4882a593Smuzhiyun regulator-boot-on; 479*4882a593Smuzhiyun regulator-state-mem { 480*4882a593Smuzhiyun regulator-on-in-suspend; 481*4882a593Smuzhiyun }; 482*4882a593Smuzhiyun }; 483*4882a593Smuzhiyun 484*4882a593Smuzhiyun vcc3v3_s0: SWITCH_REG2 { 485*4882a593Smuzhiyun regulator-name = "vcc3v3_s0"; 486*4882a593Smuzhiyun regulator-always-on; 487*4882a593Smuzhiyun regulator-boot-on; 488*4882a593Smuzhiyun regulator-state-mem { 489*4882a593Smuzhiyun regulator-on-in-suspend; 490*4882a593Smuzhiyun }; 491*4882a593Smuzhiyun }; 492*4882a593Smuzhiyun }; 493*4882a593Smuzhiyun }; 494*4882a593Smuzhiyun}; 495*4882a593Smuzhiyun 496*4882a593Smuzhiyun&i2c1 { 497*4882a593Smuzhiyun status = "okay"; 498*4882a593Smuzhiyun}; 499*4882a593Smuzhiyun 500*4882a593Smuzhiyun&i2c6 { 501*4882a593Smuzhiyun status = "okay"; 502*4882a593Smuzhiyun}; 503*4882a593Smuzhiyun 504*4882a593Smuzhiyun&i2c4 { 505*4882a593Smuzhiyun status = "okay"; 506*4882a593Smuzhiyun fusb0: fusb30x@22 { 507*4882a593Smuzhiyun compatible = "fairchild,fusb302"; 508*4882a593Smuzhiyun reg = <0x22>; 509*4882a593Smuzhiyun pinctrl-names = "default"; 510*4882a593Smuzhiyun pinctrl-0 = <&fusb0_int>; 511*4882a593Smuzhiyun vbus-5v-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; 512*4882a593Smuzhiyun int-n-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 513*4882a593Smuzhiyun status = "okay"; 514*4882a593Smuzhiyun }; 515*4882a593Smuzhiyun}; 516*4882a593Smuzhiyun 517*4882a593Smuzhiyun&i2c2 { 518*4882a593Smuzhiyun status = "okay"; 519*4882a593Smuzhiyun camera0: camera-module@10 { 520*4882a593Smuzhiyun status = "disabled"; 521*4882a593Smuzhiyun compatible = "omnivision,ov13850-v4l2-i2c-subdev"; 522*4882a593Smuzhiyun reg = < 0x10 >; 523*4882a593Smuzhiyun device_type = "v4l2-i2c-subdev"; 524*4882a593Smuzhiyun clocks = <&cru SCLK_CIF_OUT>; 525*4882a593Smuzhiyun clock-names = "clk_cif_out"; 526*4882a593Smuzhiyun pinctrl-names = "rockchip,camera_default", 527*4882a593Smuzhiyun "rockchip,camera_sleep"; 528*4882a593Smuzhiyun pinctrl-0 = <&cam0_default_pins>; 529*4882a593Smuzhiyun pinctrl-1 = <&cam0_sleep_pins>; 530*4882a593Smuzhiyun //rockchip,pd-gpio = <&gpio4 4 GPIO_ACTIVE_LOW>; 531*4882a593Smuzhiyun rockchip,pwr-gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; 532*4882a593Smuzhiyun rockchip,rst-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>; 533*4882a593Smuzhiyun rockchip,camera-module-mclk-name = "clk_cif_out"; 534*4882a593Smuzhiyun rockchip,camera-module-facing = "back"; 535*4882a593Smuzhiyun rockchip,camera-module-name = "cmk-cb0695-fv1"; 536*4882a593Smuzhiyun rockchip,camera-module-len-name = "lg9569a2"; 537*4882a593Smuzhiyun rockchip,camera-module-fov-h = "66.0"; 538*4882a593Smuzhiyun rockchip,camera-module-fov-v = "50.1"; 539*4882a593Smuzhiyun rockchip,camera-module-orientation = <0>; 540*4882a593Smuzhiyun rockchip,camera-module-iq-flip = <0>; 541*4882a593Smuzhiyun rockchip,camera-module-iq-mirror = <0>; 542*4882a593Smuzhiyun rockchip,camera-module-flip = <1>; 543*4882a593Smuzhiyun rockchip,camera-module-mirror = <0>; 544*4882a593Smuzhiyun 545*4882a593Smuzhiyun rockchip,camera-module-defrect0 = <2112 1568 0 0 2112 1568>; 546*4882a593Smuzhiyun rockchip,camera-module-defrect1 = <4224 3136 0 0 4224 3136>; 547*4882a593Smuzhiyun rockchip,camera-module-defrect3 = <3264 2448 0 0 3264 2448>; 548*4882a593Smuzhiyun rockchip,camera-module-flash-support = <1>; 549*4882a593Smuzhiyun rockchip,camera-module-mipi-dphy-index = <0>; 550*4882a593Smuzhiyun }; 551*4882a593Smuzhiyun 552*4882a593Smuzhiyun camera1: camera-module@36 { 553*4882a593Smuzhiyun status = "disabled"; 554*4882a593Smuzhiyun compatible = "omnivision,ov4690-v4l2-i2c-subdev"; 555*4882a593Smuzhiyun reg = <0x36>; 556*4882a593Smuzhiyun device_type = "v4l2-i2c-subdev"; 557*4882a593Smuzhiyun clocks = <&cru SCLK_CIF_OUT>; 558*4882a593Smuzhiyun clock-names = "clk_cif_out"; 559*4882a593Smuzhiyun pinctrl-names = "rockchip,camera_default", 560*4882a593Smuzhiyun "rockchip,camera_sleep"; 561*4882a593Smuzhiyun pinctrl-0 = <&cam0_default_pins>; 562*4882a593Smuzhiyun pinctrl-1 = <&cam0_sleep_pins>; 563*4882a593Smuzhiyun rockchip,pd-gpio = <&gpio3 4 GPIO_ACTIVE_LOW>; 564*4882a593Smuzhiyun //rockchip,pwr-gpio = <&gpio3 13 0>; 565*4882a593Smuzhiyun rockchip,rst-gpio = <&gpio2 10 GPIO_ACTIVE_LOW>; 566*4882a593Smuzhiyun rockchip,camera-module-mclk-name = "clk_cif_out"; 567*4882a593Smuzhiyun rockchip,camera-module-facing = "back"; 568*4882a593Smuzhiyun rockchip,camera-module-name = "LA6111PA"; 569*4882a593Smuzhiyun rockchip,camera-module-len-name = "YM6011P"; 570*4882a593Smuzhiyun rockchip,camera-module-fov-h = "116"; 571*4882a593Smuzhiyun rockchip,camera-module-fov-v = "61"; 572*4882a593Smuzhiyun rockchip,camera-module-orientation = <0>; 573*4882a593Smuzhiyun rockchip,camera-module-iq-flip = <0>; 574*4882a593Smuzhiyun rockchip,camera-module-iq-mirror = <0>; 575*4882a593Smuzhiyun rockchip,camera-module-flip = <0>; 576*4882a593Smuzhiyun rockchip,camera-module-mirror = <1>; 577*4882a593Smuzhiyun 578*4882a593Smuzhiyun rockchip,camera-module-defrect0 = <2688 1520 0 0 2688 1520>; 579*4882a593Smuzhiyun rockchip,camera-module-flash-support = <0>; 580*4882a593Smuzhiyun rockchip,camera-module-mipi-dphy-index = <0>; 581*4882a593Smuzhiyun }; 582*4882a593Smuzhiyun 583*4882a593Smuzhiyun}; 584*4882a593Smuzhiyun 585*4882a593Smuzhiyun&cpu_l0 { 586*4882a593Smuzhiyun cpu-supply = <&vdd_cpu_l>; 587*4882a593Smuzhiyun}; 588*4882a593Smuzhiyun 589*4882a593Smuzhiyun&cpu_l1 { 590*4882a593Smuzhiyun cpu-supply = <&vdd_cpu_l>; 591*4882a593Smuzhiyun}; 592*4882a593Smuzhiyun 593*4882a593Smuzhiyun&cpu_l2 { 594*4882a593Smuzhiyun cpu-supply = <&vdd_cpu_l>; 595*4882a593Smuzhiyun}; 596*4882a593Smuzhiyun 597*4882a593Smuzhiyun&cpu_l3 { 598*4882a593Smuzhiyun cpu-supply = <&vdd_cpu_l>; 599*4882a593Smuzhiyun}; 600*4882a593Smuzhiyun 601*4882a593Smuzhiyun&cpu_b0 { 602*4882a593Smuzhiyun cpu-supply = <&vdd_cpu_b>; 603*4882a593Smuzhiyun}; 604*4882a593Smuzhiyun 605*4882a593Smuzhiyun&cpu_b1 { 606*4882a593Smuzhiyun cpu-supply = <&vdd_cpu_b>; 607*4882a593Smuzhiyun}; 608*4882a593Smuzhiyun 609*4882a593Smuzhiyun&gpu { 610*4882a593Smuzhiyun status = "okay"; 611*4882a593Smuzhiyun mali-supply = <&vdd_gpu>; 612*4882a593Smuzhiyun}; 613*4882a593Smuzhiyun 614*4882a593Smuzhiyun&threshold { 615*4882a593Smuzhiyun temperature = <85000>; 616*4882a593Smuzhiyun}; 617*4882a593Smuzhiyun 618*4882a593Smuzhiyun&target { 619*4882a593Smuzhiyun temperature = <100000>; 620*4882a593Smuzhiyun}; 621*4882a593Smuzhiyun 622*4882a593Smuzhiyun&soc_crit { 623*4882a593Smuzhiyun temperature = <105000>; 624*4882a593Smuzhiyun}; 625*4882a593Smuzhiyun 626*4882a593Smuzhiyun&tcphy0 { 627*4882a593Smuzhiyun extcon = <&fusb0>; 628*4882a593Smuzhiyun status = "okay"; 629*4882a593Smuzhiyun}; 630*4882a593Smuzhiyun 631*4882a593Smuzhiyun&tcphy1 { 632*4882a593Smuzhiyun status = "okay"; 633*4882a593Smuzhiyun}; 634*4882a593Smuzhiyun 635*4882a593Smuzhiyun&tsadc { 636*4882a593Smuzhiyun /* tshut mode 0:CRU 1:GPIO */ 637*4882a593Smuzhiyun rockchip,hw-tshut-mode = <1>; 638*4882a593Smuzhiyun /* tshut polarity 0:LOW 1:HIGH */ 639*4882a593Smuzhiyun rockchip,hw-tshut-polarity = <1>; 640*4882a593Smuzhiyun rockchip,hw-tshut-temp = <110000>; 641*4882a593Smuzhiyun status = "okay"; 642*4882a593Smuzhiyun}; 643*4882a593Smuzhiyun 644*4882a593Smuzhiyun&u2phy0 { 645*4882a593Smuzhiyun status = "okay"; 646*4882a593Smuzhiyun extcon = <&fusb0>; 647*4882a593Smuzhiyun 648*4882a593Smuzhiyun u2phy0_otg: otg-port { 649*4882a593Smuzhiyun status = "okay"; 650*4882a593Smuzhiyun }; 651*4882a593Smuzhiyun 652*4882a593Smuzhiyun u2phy0_host: host-port { 653*4882a593Smuzhiyun phy-supply = <&vcc5v0_host>; 654*4882a593Smuzhiyun status = "okay"; 655*4882a593Smuzhiyun }; 656*4882a593Smuzhiyun}; 657*4882a593Smuzhiyun 658*4882a593Smuzhiyun&u2phy1 { 659*4882a593Smuzhiyun status = "okay"; 660*4882a593Smuzhiyun 661*4882a593Smuzhiyun u2phy1_otg: otg-port { 662*4882a593Smuzhiyun status = "okay"; 663*4882a593Smuzhiyun }; 664*4882a593Smuzhiyun 665*4882a593Smuzhiyun u2phy1_host: host-port { 666*4882a593Smuzhiyun phy-supply = <&vcc5v0_host>; 667*4882a593Smuzhiyun status = "okay"; 668*4882a593Smuzhiyun }; 669*4882a593Smuzhiyun}; 670*4882a593Smuzhiyun 671*4882a593Smuzhiyun&uart0 { 672*4882a593Smuzhiyun pinctrl-names = "default"; 673*4882a593Smuzhiyun pinctrl-0 = <&uart0_xfer &uart0_cts>; 674*4882a593Smuzhiyun dmas = <&dmac_peri 0>, <&dmac_peri 1>; 675*4882a593Smuzhiyun dma-names = "tx", "rx"; 676*4882a593Smuzhiyun status = "okay"; 677*4882a593Smuzhiyun}; 678*4882a593Smuzhiyun 679*4882a593Smuzhiyun&uart3 { 680*4882a593Smuzhiyun compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 681*4882a593Smuzhiyun reg = <0x0 0xff1b0000 0x0 0x100>; 682*4882a593Smuzhiyun clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 683*4882a593Smuzhiyun clock-names = "baudclk", "apb_pclk"; 684*4882a593Smuzhiyun interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 685*4882a593Smuzhiyun dmas = <&dmac_peri 6>, <&dmac_peri 7>; 686*4882a593Smuzhiyun dma-names = "tx", "rx"; 687*4882a593Smuzhiyun reg-shift = <2>; 688*4882a593Smuzhiyun reg-io-width = <4>; 689*4882a593Smuzhiyun pinctrl-names = "default"; 690*4882a593Smuzhiyun pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>; 691*4882a593Smuzhiyun status = "okay"; 692*4882a593Smuzhiyun}; 693*4882a593Smuzhiyun 694*4882a593Smuzhiyun&uart4 { 695*4882a593Smuzhiyun status = "okay"; 696*4882a593Smuzhiyun dmas = <&dmac_peri 8>, <&dmac_peri 9>; 697*4882a593Smuzhiyun dma-names = "tx", "rx"; 698*4882a593Smuzhiyun}; 699*4882a593Smuzhiyun 700*4882a593Smuzhiyun&usb_host0_ehci { 701*4882a593Smuzhiyun status = "okay"; 702*4882a593Smuzhiyun}; 703*4882a593Smuzhiyun 704*4882a593Smuzhiyun&usb_host0_ohci { 705*4882a593Smuzhiyun status = "okay"; 706*4882a593Smuzhiyun}; 707*4882a593Smuzhiyun 708*4882a593Smuzhiyun&usb_host1_ehci { 709*4882a593Smuzhiyun status = "okay"; 710*4882a593Smuzhiyun}; 711*4882a593Smuzhiyun 712*4882a593Smuzhiyun&usb_host1_ohci { 713*4882a593Smuzhiyun status = "okay"; 714*4882a593Smuzhiyun}; 715*4882a593Smuzhiyun 716*4882a593Smuzhiyun&usbdrd3_0 { 717*4882a593Smuzhiyun status = "okay"; 718*4882a593Smuzhiyun}; 719*4882a593Smuzhiyun 720*4882a593Smuzhiyun&usbdrd_dwc3_0 { 721*4882a593Smuzhiyun dr_mode = "otg"; 722*4882a593Smuzhiyun status = "okay"; 723*4882a593Smuzhiyun extcon = <&fusb0>; 724*4882a593Smuzhiyun}; 725*4882a593Smuzhiyun 726*4882a593Smuzhiyun&usbdrd3_1 { 727*4882a593Smuzhiyun status = "okay"; 728*4882a593Smuzhiyun}; 729*4882a593Smuzhiyun 730*4882a593Smuzhiyun&usbdrd_dwc3_1 { 731*4882a593Smuzhiyun dr_mode = "host"; 732*4882a593Smuzhiyun status = "okay"; 733*4882a593Smuzhiyun}; 734*4882a593Smuzhiyun 735*4882a593Smuzhiyun&pwm2 { 736*4882a593Smuzhiyun status = "okay"; 737*4882a593Smuzhiyun pinctrl-names = "active"; 738*4882a593Smuzhiyun pinctrl-0 = <&pwm2_pin_pull_down>; 739*4882a593Smuzhiyun}; 740*4882a593Smuzhiyun 741*4882a593Smuzhiyun&pwm3 { 742*4882a593Smuzhiyun status = "okay"; 743*4882a593Smuzhiyun 744*4882a593Smuzhiyun interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH 0>; 745*4882a593Smuzhiyun compatible = "rockchip,remotectl-pwm"; 746*4882a593Smuzhiyun remote_pwm_id = <3>; 747*4882a593Smuzhiyun handle_cpu_id = <1>; 748*4882a593Smuzhiyun remote_support_psci = <1>; 749*4882a593Smuzhiyun 750*4882a593Smuzhiyun ir_key1 { 751*4882a593Smuzhiyun rockchip,usercode = <0x4040>; 752*4882a593Smuzhiyun rockchip,key_table = 753*4882a593Smuzhiyun <0xf2 KEY_REPLY>, 754*4882a593Smuzhiyun <0xba KEY_BACK>, 755*4882a593Smuzhiyun <0xf4 KEY_UP>, 756*4882a593Smuzhiyun <0xf1 KEY_DOWN>, 757*4882a593Smuzhiyun <0xef KEY_LEFT>, 758*4882a593Smuzhiyun <0xee KEY_RIGHT>, 759*4882a593Smuzhiyun <0xbd KEY_HOME>, 760*4882a593Smuzhiyun <0xea KEY_VOLUMEUP>, 761*4882a593Smuzhiyun <0xe3 KEY_VOLUMEDOWN>, 762*4882a593Smuzhiyun <0xe2 KEY_SEARCH>, 763*4882a593Smuzhiyun <0xb2 KEY_POWER>, 764*4882a593Smuzhiyun <0xbc KEY_MUTE>, 765*4882a593Smuzhiyun <0xec KEY_MENU>, 766*4882a593Smuzhiyun <0xbf 0x190>, 767*4882a593Smuzhiyun <0xe0 0x191>, 768*4882a593Smuzhiyun <0xe1 0x192>, 769*4882a593Smuzhiyun <0xe9 183>, 770*4882a593Smuzhiyun <0xe6 248>, 771*4882a593Smuzhiyun <0xe8 185>, 772*4882a593Smuzhiyun <0xe7 186>, 773*4882a593Smuzhiyun <0xf0 388>, 774*4882a593Smuzhiyun <0xbe 0x175>; 775*4882a593Smuzhiyun }; 776*4882a593Smuzhiyun 777*4882a593Smuzhiyun ir_key2 { 778*4882a593Smuzhiyun rockchip,usercode = <0xff00>; 779*4882a593Smuzhiyun rockchip,key_table = 780*4882a593Smuzhiyun <0xf9 KEY_HOME>, 781*4882a593Smuzhiyun <0xbf KEY_BACK>, 782*4882a593Smuzhiyun <0xfb KEY_MENU>, 783*4882a593Smuzhiyun <0xaa KEY_REPLY>, 784*4882a593Smuzhiyun <0xb9 KEY_UP>, 785*4882a593Smuzhiyun <0xe9 KEY_DOWN>, 786*4882a593Smuzhiyun <0xb8 KEY_LEFT>, 787*4882a593Smuzhiyun <0xea KEY_RIGHT>, 788*4882a593Smuzhiyun <0xeb KEY_VOLUMEDOWN>, 789*4882a593Smuzhiyun <0xef KEY_VOLUMEUP>, 790*4882a593Smuzhiyun <0xf7 KEY_MUTE>, 791*4882a593Smuzhiyun <0xe7 KEY_POWER>, 792*4882a593Smuzhiyun <0xfc KEY_POWER>, 793*4882a593Smuzhiyun <0xa9 KEY_VOLUMEDOWN>, 794*4882a593Smuzhiyun <0xa8 KEY_VOLUMEDOWN>, 795*4882a593Smuzhiyun <0xe0 KEY_VOLUMEDOWN>, 796*4882a593Smuzhiyun <0xa5 KEY_VOLUMEDOWN>, 797*4882a593Smuzhiyun <0xab 183>, 798*4882a593Smuzhiyun <0xb7 388>, 799*4882a593Smuzhiyun <0xe8 388>, 800*4882a593Smuzhiyun <0xf8 184>, 801*4882a593Smuzhiyun <0xaf 185>, 802*4882a593Smuzhiyun <0xed KEY_VOLUMEDOWN>, 803*4882a593Smuzhiyun <0xee 186>, 804*4882a593Smuzhiyun <0xb3 KEY_VOLUMEDOWN>, 805*4882a593Smuzhiyun <0xf1 KEY_VOLUMEDOWN>, 806*4882a593Smuzhiyun <0xf2 KEY_VOLUMEDOWN>, 807*4882a593Smuzhiyun <0xf3 KEY_SEARCH>, 808*4882a593Smuzhiyun <0xb4 KEY_VOLUMEDOWN>, 809*4882a593Smuzhiyun <0xbe KEY_SEARCH>; 810*4882a593Smuzhiyun }; 811*4882a593Smuzhiyun 812*4882a593Smuzhiyun ir_key3 { 813*4882a593Smuzhiyun rockchip,usercode = <0x1dcc>; 814*4882a593Smuzhiyun rockchip,key_table = 815*4882a593Smuzhiyun <0xee KEY_REPLY>, 816*4882a593Smuzhiyun <0xf0 KEY_BACK>, 817*4882a593Smuzhiyun <0xf8 KEY_UP>, 818*4882a593Smuzhiyun <0xbb KEY_DOWN>, 819*4882a593Smuzhiyun <0xef KEY_LEFT>, 820*4882a593Smuzhiyun <0xed KEY_RIGHT>, 821*4882a593Smuzhiyun <0xfc KEY_HOME>, 822*4882a593Smuzhiyun <0xf1 KEY_VOLUMEUP>, 823*4882a593Smuzhiyun <0xfd KEY_VOLUMEDOWN>, 824*4882a593Smuzhiyun <0xb7 KEY_SEARCH>, 825*4882a593Smuzhiyun <0xff KEY_POWER>, 826*4882a593Smuzhiyun <0xf3 KEY_MUTE>, 827*4882a593Smuzhiyun <0xbf KEY_MENU>, 828*4882a593Smuzhiyun <0xf9 0x191>, 829*4882a593Smuzhiyun <0xf5 0x192>, 830*4882a593Smuzhiyun <0xb3 388>, 831*4882a593Smuzhiyun <0xbe KEY_1>, 832*4882a593Smuzhiyun <0xba KEY_2>, 833*4882a593Smuzhiyun <0xb2 KEY_3>, 834*4882a593Smuzhiyun <0xbd KEY_4>, 835*4882a593Smuzhiyun <0xf9 KEY_5>, 836*4882a593Smuzhiyun <0xb1 KEY_6>, 837*4882a593Smuzhiyun <0xfc KEY_7>, 838*4882a593Smuzhiyun <0xf8 KEY_8>, 839*4882a593Smuzhiyun <0xb0 KEY_9>, 840*4882a593Smuzhiyun <0xb6 KEY_0>, 841*4882a593Smuzhiyun <0xb5 KEY_BACKSPACE>; 842*4882a593Smuzhiyun }; 843*4882a593Smuzhiyun}; 844*4882a593Smuzhiyun 845*4882a593Smuzhiyun&gmac { 846*4882a593Smuzhiyun phy-supply = <&vcc_phy>; 847*4882a593Smuzhiyun phy-mode = "rgmii"; 848*4882a593Smuzhiyun clock_in_out = "input"; 849*4882a593Smuzhiyun snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>; 850*4882a593Smuzhiyun snps,reset-active-low; 851*4882a593Smuzhiyun snps,reset-delays-us = <0 10000 50000>; 852*4882a593Smuzhiyun assigned-clocks = <&cru SCLK_RMII_SRC>; 853*4882a593Smuzhiyun assigned-clock-parents = <&clkin_gmac>; 854*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 855*4882a593Smuzhiyun pinctrl-0 = <&rgmii_pins>; 856*4882a593Smuzhiyun pinctrl-1 = <&rgmii_sleep_pins>; 857*4882a593Smuzhiyun tx_delay = <0x28>; 858*4882a593Smuzhiyun rx_delay = <0x11>; 859*4882a593Smuzhiyun status = "disabled"; 860*4882a593Smuzhiyun}; 861*4882a593Smuzhiyun 862*4882a593Smuzhiyun&saradc { 863*4882a593Smuzhiyun status = "okay"; 864*4882a593Smuzhiyun}; 865*4882a593Smuzhiyun 866*4882a593Smuzhiyun&io_domains { 867*4882a593Smuzhiyun status = "okay"; 868*4882a593Smuzhiyun 869*4882a593Smuzhiyun bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */ 870*4882a593Smuzhiyun audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */ 871*4882a593Smuzhiyun sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */ 872*4882a593Smuzhiyun gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ 873*4882a593Smuzhiyun}; 874*4882a593Smuzhiyun 875*4882a593Smuzhiyun&pcie_phy { 876*4882a593Smuzhiyun status = "okay"; 877*4882a593Smuzhiyun}; 878*4882a593Smuzhiyun 879*4882a593Smuzhiyun&pcie0 { 880*4882a593Smuzhiyun ep-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; 881*4882a593Smuzhiyun num-lanes = <4>; 882*4882a593Smuzhiyun pinctrl-names = "default"; 883*4882a593Smuzhiyun pinctrl-0 = <&pcie_clkreqn_cpm>; 884*4882a593Smuzhiyun status = "okay"; 885*4882a593Smuzhiyun}; 886*4882a593Smuzhiyun 887*4882a593Smuzhiyun&pinctrl { 888*4882a593Smuzhiyun 889*4882a593Smuzhiyun sdio0 { 890*4882a593Smuzhiyun sdio0_bus1: sdio0-bus1 { 891*4882a593Smuzhiyun rockchip,pins = 892*4882a593Smuzhiyun <2 RK_PC4 1 &pcfg_pull_up_20ma>; 893*4882a593Smuzhiyun }; 894*4882a593Smuzhiyun 895*4882a593Smuzhiyun sdio0_bus4: sdio0-bus4 { 896*4882a593Smuzhiyun rockchip,pins = 897*4882a593Smuzhiyun <2 RK_PC4 1 &pcfg_pull_up_20ma>, 898*4882a593Smuzhiyun <2 RK_PC5 1 &pcfg_pull_up_20ma>, 899*4882a593Smuzhiyun <2 RK_PC6 1 &pcfg_pull_up_20ma>, 900*4882a593Smuzhiyun <2 RK_PC7 1 &pcfg_pull_up_20ma>; 901*4882a593Smuzhiyun }; 902*4882a593Smuzhiyun 903*4882a593Smuzhiyun sdio0_cmd: sdio0-cmd { 904*4882a593Smuzhiyun rockchip,pins = 905*4882a593Smuzhiyun <2 RK_PD0 1 &pcfg_pull_up_20ma>; 906*4882a593Smuzhiyun }; 907*4882a593Smuzhiyun 908*4882a593Smuzhiyun sdio0_clk: sdio0-clk { 909*4882a593Smuzhiyun rockchip,pins = 910*4882a593Smuzhiyun <2 RK_PD1 1 &pcfg_pull_none_20ma>; 911*4882a593Smuzhiyun }; 912*4882a593Smuzhiyun }; 913*4882a593Smuzhiyun 914*4882a593Smuzhiyun sdmmc { 915*4882a593Smuzhiyun sdmmc_bus1: sdmmc-bus1 { 916*4882a593Smuzhiyun rockchip,pins = 917*4882a593Smuzhiyun <4 RK_PB0 1 &pcfg_pull_up_8ma>; 918*4882a593Smuzhiyun }; 919*4882a593Smuzhiyun 920*4882a593Smuzhiyun sdmmc_bus4: sdmmc-bus4 { 921*4882a593Smuzhiyun rockchip,pins = 922*4882a593Smuzhiyun <4 RK_PB0 1 &pcfg_pull_up_8ma>, 923*4882a593Smuzhiyun <4 RK_PB1 1 &pcfg_pull_up_8ma>, 924*4882a593Smuzhiyun <4 RK_PB2 1 &pcfg_pull_up_8ma>, 925*4882a593Smuzhiyun <4 RK_PB3 1 &pcfg_pull_up_8ma>; 926*4882a593Smuzhiyun }; 927*4882a593Smuzhiyun 928*4882a593Smuzhiyun sdmmc_clk: sdmmc-clk { 929*4882a593Smuzhiyun rockchip,pins = 930*4882a593Smuzhiyun <4 RK_PB4 1 &pcfg_pull_none_18ma>; 931*4882a593Smuzhiyun }; 932*4882a593Smuzhiyun 933*4882a593Smuzhiyun sdmmc_cmd: sdmmc-cmd { 934*4882a593Smuzhiyun rockchip,pins = 935*4882a593Smuzhiyun <4 RK_PB5 1 &pcfg_pull_up_8ma>; 936*4882a593Smuzhiyun }; 937*4882a593Smuzhiyun }; 938*4882a593Smuzhiyun 939*4882a593Smuzhiyun sdio-pwrseq { 940*4882a593Smuzhiyun wifi_enable_h: wifi-enable-h { 941*4882a593Smuzhiyun rockchip,pins = 942*4882a593Smuzhiyun <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 943*4882a593Smuzhiyun }; 944*4882a593Smuzhiyun }; 945*4882a593Smuzhiyun 946*4882a593Smuzhiyun wireless-bluetooth { 947*4882a593Smuzhiyun uart0_gpios: uart0-gpios { 948*4882a593Smuzhiyun rockchip,pins = 949*4882a593Smuzhiyun <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 950*4882a593Smuzhiyun }; 951*4882a593Smuzhiyun }; 952*4882a593Smuzhiyun 953*4882a593Smuzhiyun usb2 { 954*4882a593Smuzhiyun host_vbus_drv: host-vbus-drv { 955*4882a593Smuzhiyun rockchip,pins = 956*4882a593Smuzhiyun <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; 957*4882a593Smuzhiyun }; 958*4882a593Smuzhiyun }; 959*4882a593Smuzhiyun 960*4882a593Smuzhiyun pcie { 961*4882a593Smuzhiyun pcie_drv: pcie-drv { 962*4882a593Smuzhiyun rockchip,pins = 963*4882a593Smuzhiyun <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; 964*4882a593Smuzhiyun }; 965*4882a593Smuzhiyun }; 966*4882a593Smuzhiyun 967*4882a593Smuzhiyun pmic { 968*4882a593Smuzhiyun pmic_int_l: pmic-int-l { 969*4882a593Smuzhiyun rockchip,pins = 970*4882a593Smuzhiyun <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; 971*4882a593Smuzhiyun }; 972*4882a593Smuzhiyun 973*4882a593Smuzhiyun vsel1_gpio: vsel1-gpio { 974*4882a593Smuzhiyun rockchip,pins = 975*4882a593Smuzhiyun <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; 976*4882a593Smuzhiyun }; 977*4882a593Smuzhiyun 978*4882a593Smuzhiyun vsel2_gpio: vsel2-gpio { 979*4882a593Smuzhiyun rockchip,pins = 980*4882a593Smuzhiyun <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; 981*4882a593Smuzhiyun }; 982*4882a593Smuzhiyun }; 983*4882a593Smuzhiyun 984*4882a593Smuzhiyun gmac { 985*4882a593Smuzhiyun rgmii_sleep_pins: rgmii-sleep-pins { 986*4882a593Smuzhiyun rockchip,pins = 987*4882a593Smuzhiyun <3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; 988*4882a593Smuzhiyun }; 989*4882a593Smuzhiyun }; 990*4882a593Smuzhiyun 991*4882a593Smuzhiyun fusb30x { 992*4882a593Smuzhiyun fusb0_int: fusb0-int { 993*4882a593Smuzhiyun rockchip,pins = 994*4882a593Smuzhiyun <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; 995*4882a593Smuzhiyun }; 996*4882a593Smuzhiyun }; 997*4882a593Smuzhiyun}; 998*4882a593Smuzhiyun 999*4882a593Smuzhiyun&pvtm { 1000*4882a593Smuzhiyun status = "okay"; 1001*4882a593Smuzhiyun}; 1002*4882a593Smuzhiyun 1003*4882a593Smuzhiyun&pmu_pvtm { 1004*4882a593Smuzhiyun status = "okay"; 1005*4882a593Smuzhiyun}; 1006*4882a593Smuzhiyun 1007*4882a593Smuzhiyun&pmu_io_domains { 1008*4882a593Smuzhiyun status = "okay"; 1009*4882a593Smuzhiyun pmu1830-supply = <&vcc_1v8>; 1010*4882a593Smuzhiyun}; 1011*4882a593Smuzhiyun 1012*4882a593Smuzhiyun&rockchip_suspend { 1013*4882a593Smuzhiyun status = "okay"; 1014*4882a593Smuzhiyun rockchip,sleep-debug-en = <0>; 1015*4882a593Smuzhiyun rockchip,sleep-mode-config = < 1016*4882a593Smuzhiyun (0 1017*4882a593Smuzhiyun | RKPM_SLP_ARMPD 1018*4882a593Smuzhiyun | RKPM_SLP_PERILPPD 1019*4882a593Smuzhiyun | RKPM_SLP_DDR_RET 1020*4882a593Smuzhiyun | RKPM_SLP_PLLPD 1021*4882a593Smuzhiyun | RKPM_SLP_CENTER_PD 1022*4882a593Smuzhiyun | RKPM_SLP_AP_PWROFF 1023*4882a593Smuzhiyun ) 1024*4882a593Smuzhiyun >; 1025*4882a593Smuzhiyun rockchip,wakeup-config = < 1026*4882a593Smuzhiyun (0 1027*4882a593Smuzhiyun | RKPM_GPIO_WKUP_EN 1028*4882a593Smuzhiyun | RKPM_PWM_WKUP_EN 1029*4882a593Smuzhiyun ) 1030*4882a593Smuzhiyun >; 1031*4882a593Smuzhiyun rockchip,pwm-regulator-config = < 1032*4882a593Smuzhiyun (0 1033*4882a593Smuzhiyun | PWM2_REGULATOR_EN 1034*4882a593Smuzhiyun ) 1035*4882a593Smuzhiyun >; 1036*4882a593Smuzhiyun rockchip,power-ctrl = 1037*4882a593Smuzhiyun <&gpio1 17 GPIO_ACTIVE_HIGH>, 1038*4882a593Smuzhiyun <&gpio1 14 GPIO_ACTIVE_HIGH>; 1039*4882a593Smuzhiyun}; 1040*4882a593Smuzhiyun 1041*4882a593Smuzhiyun&vopb { 1042*4882a593Smuzhiyun status = "okay"; 1043*4882a593Smuzhiyun}; 1044*4882a593Smuzhiyun 1045*4882a593Smuzhiyun&vopb_mmu { 1046*4882a593Smuzhiyun status = "okay"; 1047*4882a593Smuzhiyun}; 1048*4882a593Smuzhiyun 1049*4882a593Smuzhiyun&vopl { 1050*4882a593Smuzhiyun status = "okay"; 1051*4882a593Smuzhiyun}; 1052*4882a593Smuzhiyun 1053*4882a593Smuzhiyun&vopl_mmu { 1054*4882a593Smuzhiyun status = "okay"; 1055*4882a593Smuzhiyun}; 1056*4882a593Smuzhiyun 1057*4882a593Smuzhiyun&cif_isp0 { 1058*4882a593Smuzhiyun rockchip,camera-modules-attached = <&camera0>; 1059*4882a593Smuzhiyun status = "okay"; 1060*4882a593Smuzhiyun}; 1061*4882a593Smuzhiyun 1062*4882a593Smuzhiyun&isp0_mmu { 1063*4882a593Smuzhiyun status = "okay"; 1064*4882a593Smuzhiyun}; 1065*4882a593Smuzhiyun 1066*4882a593Smuzhiyun&cif_isp1 { 1067*4882a593Smuzhiyun rockchip,camera-modules-attached = <&camera1>; 1068*4882a593Smuzhiyun status = "disabled"; 1069*4882a593Smuzhiyun}; 1070*4882a593Smuzhiyun 1071*4882a593Smuzhiyun&isp1_mmu { 1072*4882a593Smuzhiyun status = "okay"; 1073*4882a593Smuzhiyun}; 1074*4882a593Smuzhiyun 1075*4882a593Smuzhiyun&vpu { 1076*4882a593Smuzhiyun status = "okay"; 1077*4882a593Smuzhiyun /* 0 means ion, 1 means drm */ 1078*4882a593Smuzhiyun //allocator = <0>; 1079*4882a593Smuzhiyun}; 1080*4882a593Smuzhiyun 1081*4882a593Smuzhiyun&rkvdec { 1082*4882a593Smuzhiyun status = "okay"; 1083*4882a593Smuzhiyun /* 0 means ion, 1 means drm */ 1084*4882a593Smuzhiyun //allocator = <0>; 1085*4882a593Smuzhiyun}; 1086*4882a593Smuzhiyun 1087*4882a593Smuzhiyun&display_subsystem { 1088*4882a593Smuzhiyun status = "okay"; 1089*4882a593Smuzhiyun}; 1090