1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include "rk3399-sched-energy.dtsi" 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/ { 9*4882a593Smuzhiyun cluster0_opp: opp-table0 { 10*4882a593Smuzhiyun compatible = "operating-points-v2"; 11*4882a593Smuzhiyun opp-shared; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun rockchip,temp-hysteresis = <5000>; 14*4882a593Smuzhiyun rockchip,low-temp = <10000>; 15*4882a593Smuzhiyun rockchip,low-temp-min-volt = <900000>; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun nvmem-cells = <&cpul_leakage>, <&specification_serial_number>, 18*4882a593Smuzhiyun <&customer_demand>; 19*4882a593Smuzhiyun nvmem-cell-names = "cpu_leakage", 20*4882a593Smuzhiyun "specification_serial_number", 21*4882a593Smuzhiyun "customer_demand"; 22*4882a593Smuzhiyun clocks = <&cru PLL_APLLL>; 23*4882a593Smuzhiyun rockchip,avs-scale = <20>; 24*4882a593Smuzhiyun rockchip,bin-scaling-sel = < 25*4882a593Smuzhiyun 0 30 26*4882a593Smuzhiyun 1 34 27*4882a593Smuzhiyun >; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun rockchip,pvtm-voltage-sel = < 30*4882a593Smuzhiyun 0 143500 0 31*4882a593Smuzhiyun 143501 148500 1 32*4882a593Smuzhiyun 148501 152000 2 33*4882a593Smuzhiyun 152001 999999 3 34*4882a593Smuzhiyun >; 35*4882a593Smuzhiyun rockchip,pvtm-freq = <408000>; 36*4882a593Smuzhiyun rockchip,pvtm-volt = <1000000>; 37*4882a593Smuzhiyun rockchip,pvtm-ch = <0 0>; 38*4882a593Smuzhiyun rockchip,pvtm-sample-time = <1000>; 39*4882a593Smuzhiyun rockchip,pvtm-number = <10>; 40*4882a593Smuzhiyun rockchip,pvtm-error = <1000>; 41*4882a593Smuzhiyun rockchip,pvtm-ref-temp = <41>; 42*4882a593Smuzhiyun rockchip,pvtm-temp-prop = <115 66>; 43*4882a593Smuzhiyun rockchip,pvtm-thermal-zone = "soc-thermal"; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun opp-408000000 { 46*4882a593Smuzhiyun opp-hz = /bits/ 64 <408000000>; 47*4882a593Smuzhiyun opp-microvolt = <825000 825000 1250000>; 48*4882a593Smuzhiyun opp-microvolt-L0 = <825000 825000 1250000>; 49*4882a593Smuzhiyun opp-microvolt-L1 = <825000 825000 1250000>; 50*4882a593Smuzhiyun opp-microvolt-L2 = <825000 825000 1250000>; 51*4882a593Smuzhiyun opp-microvolt-L3 = <825000 825000 1250000>; 52*4882a593Smuzhiyun clock-latency-ns = <40000>; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun opp-600000000 { 55*4882a593Smuzhiyun opp-hz = /bits/ 64 <600000000>; 56*4882a593Smuzhiyun opp-microvolt = <825000 825000 1250000>; 57*4882a593Smuzhiyun opp-microvolt-L0 = <825000 825000 1250000>; 58*4882a593Smuzhiyun opp-microvolt-L1 = <825000 825000 1250000>; 59*4882a593Smuzhiyun opp-microvolt-L2 = <825000 825000 1250000>; 60*4882a593Smuzhiyun opp-microvolt-L3 = <825000 825000 1250000>; 61*4882a593Smuzhiyun clock-latency-ns = <40000>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun opp-816000000 { 64*4882a593Smuzhiyun opp-hz = /bits/ 64 <816000000>; 65*4882a593Smuzhiyun opp-microvolt = <850000 850000 1250000>; 66*4882a593Smuzhiyun opp-microvolt-L0 = <850000 850000 1250000>; 67*4882a593Smuzhiyun opp-microvolt-L1 = <825000 825000 1250000>; 68*4882a593Smuzhiyun opp-microvolt-L2 = <825000 825000 1250000>; 69*4882a593Smuzhiyun opp-microvolt-L3 = <825000 825000 1250000>; 70*4882a593Smuzhiyun clock-latency-ns = <40000>; 71*4882a593Smuzhiyun opp-suspend; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun opp-1008000000 { 74*4882a593Smuzhiyun opp-hz = /bits/ 64 <1008000000>; 75*4882a593Smuzhiyun opp-microvolt = <925000 925000 1250000>; 76*4882a593Smuzhiyun opp-microvolt-L0 = <925000 925000 1250000>; 77*4882a593Smuzhiyun opp-microvolt-L1 = <900000 900000 1250000>; 78*4882a593Smuzhiyun opp-microvolt-L2 = <875000 875000 1250000>; 79*4882a593Smuzhiyun opp-microvolt-L3 = <850000 850000 1250000>; 80*4882a593Smuzhiyun clock-latency-ns = <40000>; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun opp-1200000000 { 83*4882a593Smuzhiyun opp-hz = /bits/ 64 <1200000000>; 84*4882a593Smuzhiyun opp-microvolt = <1000000 1000000 1250000>; 85*4882a593Smuzhiyun opp-microvolt-L0 = <1000000 1000000 1250000>; 86*4882a593Smuzhiyun opp-microvolt-L1 = <975000 975000 1250000>; 87*4882a593Smuzhiyun opp-microvolt-L2 = <950000 950000 1250000>; 88*4882a593Smuzhiyun opp-microvolt-L3 = <925000 925000 1250000>; 89*4882a593Smuzhiyun clock-latency-ns = <40000>; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun opp-1416000000 { 92*4882a593Smuzhiyun opp-hz = /bits/ 64 <1416000000>; 93*4882a593Smuzhiyun opp-microvolt = <1125000 1125000 1250000>; 94*4882a593Smuzhiyun opp-microvolt-L0 = <1125000 1125000 1250000>; 95*4882a593Smuzhiyun opp-microvolt-L1 = <1100000 1100000 1250000>; 96*4882a593Smuzhiyun opp-microvolt-L2 = <1075000 1075000 1200000>; 97*4882a593Smuzhiyun opp-microvolt-L3 = <1050000 1050000 1250000>; 98*4882a593Smuzhiyun clock-latency-ns = <40000>; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun cluster1_opp: opp-table1 { 103*4882a593Smuzhiyun compatible = "operating-points-v2"; 104*4882a593Smuzhiyun opp-shared; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun rockchip,temp-hysteresis = <5000>; 107*4882a593Smuzhiyun rockchip,low-temp = <10000>; 108*4882a593Smuzhiyun rockchip,low-temp-min-volt = <900000>; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun nvmem-cells = <&cpub_leakage>, <&specification_serial_number>, 111*4882a593Smuzhiyun <&customer_demand>; 112*4882a593Smuzhiyun nvmem-cell-names = "cpu_leakage", 113*4882a593Smuzhiyun "specification_serial_number", 114*4882a593Smuzhiyun "customer_demand"; 115*4882a593Smuzhiyun clocks = <&cru PLL_APLLB>; 116*4882a593Smuzhiyun rockchip,avs-scale = <8>; 117*4882a593Smuzhiyun rockchip,bin-scaling-sel = < 118*4882a593Smuzhiyun 0 8 119*4882a593Smuzhiyun 1 17 120*4882a593Smuzhiyun >; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun rockchip,pvtm-voltage-sel = < 123*4882a593Smuzhiyun 0 149000 0 124*4882a593Smuzhiyun 149001 155000 1 125*4882a593Smuzhiyun 155001 159000 2 126*4882a593Smuzhiyun 159001 161000 3 127*4882a593Smuzhiyun 161001 999999 4 128*4882a593Smuzhiyun >; 129*4882a593Smuzhiyun rockchip,pvtm-freq = <408000>; 130*4882a593Smuzhiyun rockchip,pvtm-volt = <1000000>; 131*4882a593Smuzhiyun rockchip,pvtm-ch = <1 0>; 132*4882a593Smuzhiyun rockchip,pvtm-sample-time = <1000>; 133*4882a593Smuzhiyun rockchip,pvtm-number = <10>; 134*4882a593Smuzhiyun rockchip,pvtm-error = <1000>; 135*4882a593Smuzhiyun rockchip,pvtm-ref-temp = <41>; 136*4882a593Smuzhiyun rockchip,pvtm-temp-prop = <71 35>; 137*4882a593Smuzhiyun rockchip,pvtm-thermal-zone = "soc-thermal"; 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun opp-408000000 { 140*4882a593Smuzhiyun opp-hz = /bits/ 64 <408000000>; 141*4882a593Smuzhiyun opp-microvolt = <825000 825000 1250000>; 142*4882a593Smuzhiyun opp-microvolt-L0 = <825000 825000 1250000>; 143*4882a593Smuzhiyun opp-microvolt-L1 = <825000 825000 1250000>; 144*4882a593Smuzhiyun opp-microvolt-L2 = <825000 825000 1250000>; 145*4882a593Smuzhiyun opp-microvolt-L3 = <825000 825000 1250000>; 146*4882a593Smuzhiyun opp-microvolt-L4 = <825000 825000 1250000>; 147*4882a593Smuzhiyun clock-latency-ns = <40000>; 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun opp-600000000 { 150*4882a593Smuzhiyun opp-hz = /bits/ 64 <600000000>; 151*4882a593Smuzhiyun opp-microvolt = <825000 825000 1250000>; 152*4882a593Smuzhiyun opp-microvolt-L0 = <825000 825000 1250000>; 153*4882a593Smuzhiyun opp-microvolt-L1 = <825000 825000 1250000>; 154*4882a593Smuzhiyun opp-microvolt-L2 = <825000 825000 1250000>; 155*4882a593Smuzhiyun opp-microvolt-L3 = <825000 825000 1250000>; 156*4882a593Smuzhiyun opp-microvolt-L4 = <825000 825000 1250000>; 157*4882a593Smuzhiyun clock-latency-ns = <40000>; 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun opp-816000000 { 160*4882a593Smuzhiyun opp-hz = /bits/ 64 <816000000>; 161*4882a593Smuzhiyun opp-microvolt = <825000 825000 1250000>; 162*4882a593Smuzhiyun opp-microvolt-L0 = <825000 825000 1250000>; 163*4882a593Smuzhiyun opp-microvolt-L1 = <825000 825000 1250000>; 164*4882a593Smuzhiyun opp-microvolt-L2 = <825000 825000 1250000>; 165*4882a593Smuzhiyun opp-microvolt-L3 = <825000 825000 1250000>; 166*4882a593Smuzhiyun opp-microvolt-L4 = <825000 825000 1250000>; 167*4882a593Smuzhiyun clock-latency-ns = <40000>; 168*4882a593Smuzhiyun opp-suspend; 169*4882a593Smuzhiyun }; 170*4882a593Smuzhiyun opp-1008000000 { 171*4882a593Smuzhiyun opp-hz = /bits/ 64 <1008000000>; 172*4882a593Smuzhiyun opp-microvolt = <875000 875000 1250000>; 173*4882a593Smuzhiyun opp-microvolt-L0 = <875000 875000 1250000>; 174*4882a593Smuzhiyun opp-microvolt-L1 = <850000 850000 1250000>; 175*4882a593Smuzhiyun opp-microvolt-L2 = <850000 850000 1250000>; 176*4882a593Smuzhiyun opp-microvolt-L3 = <850000 850000 1250000>; 177*4882a593Smuzhiyun opp-microvolt-L4 = <850000 850000 1250000>; 178*4882a593Smuzhiyun clock-latency-ns = <40000>; 179*4882a593Smuzhiyun }; 180*4882a593Smuzhiyun opp-1200000000 { 181*4882a593Smuzhiyun opp-hz = /bits/ 64 <1200000000>; 182*4882a593Smuzhiyun opp-microvolt = <950000 950000 1250000>; 183*4882a593Smuzhiyun opp-microvolt-L0 = <950000 950000 1250000>; 184*4882a593Smuzhiyun opp-microvolt-L1 = <925000 925000 1250000>; 185*4882a593Smuzhiyun opp-microvolt-L2 = <900000 900000 1250000>; 186*4882a593Smuzhiyun opp-microvolt-L3 = <875000 875000 1250000>; 187*4882a593Smuzhiyun opp-microvolt-L4 = <875000 875000 1250000>; 188*4882a593Smuzhiyun clock-latency-ns = <40000>; 189*4882a593Smuzhiyun }; 190*4882a593Smuzhiyun opp-1416000000 { 191*4882a593Smuzhiyun opp-hz = /bits/ 64 <1416000000>; 192*4882a593Smuzhiyun opp-microvolt = <1025000 1025000 1250000>; 193*4882a593Smuzhiyun opp-microvolt-L0 = <1025000 1025000 1250000>; 194*4882a593Smuzhiyun opp-microvolt-L1 = <1000000 1000000 1250000>; 195*4882a593Smuzhiyun opp-microvolt-L2 = <1000000 1000000 1250000>; 196*4882a593Smuzhiyun opp-microvolt-L3 = <975000 975000 1250000>; 197*4882a593Smuzhiyun opp-microvolt-L4 = <975000 975000 1250000>; 198*4882a593Smuzhiyun clock-latency-ns = <40000>; 199*4882a593Smuzhiyun }; 200*4882a593Smuzhiyun opp-1608000000 { 201*4882a593Smuzhiyun opp-hz = /bits/ 64 <1608000000>; 202*4882a593Smuzhiyun opp-microvolt = <1100000 1100000 1250000>; 203*4882a593Smuzhiyun opp-microvolt-L0 = <1100000 1100000 1250000>; 204*4882a593Smuzhiyun opp-microvolt-L1 = <1075000 1075000 1250000>; 205*4882a593Smuzhiyun opp-microvolt-L2 = <1050000 1050000 1250000>; 206*4882a593Smuzhiyun opp-microvolt-L3 = <1025000 1025000 1250000>; 207*4882a593Smuzhiyun opp-microvolt-L4 = <1025000 1025000 1250000>; 208*4882a593Smuzhiyun clock-latency-ns = <40000>; 209*4882a593Smuzhiyun }; 210*4882a593Smuzhiyun opp-1800000000 { 211*4882a593Smuzhiyun opp-hz = /bits/ 64 <1800000000>; 212*4882a593Smuzhiyun opp-microvolt = <1200000 1200000 1250000>; 213*4882a593Smuzhiyun opp-microvolt-L0 = <1200000 1200000 1250000>; 214*4882a593Smuzhiyun opp-microvolt-L1 = <1175000 1175000 1250000>; 215*4882a593Smuzhiyun opp-microvolt-L2 = <1150000 1150000 1250000>; 216*4882a593Smuzhiyun opp-microvolt-L3 = <1125000 1125000 1250000>; 217*4882a593Smuzhiyun opp-microvolt-L4 = <1100000 1100000 1250000>; 218*4882a593Smuzhiyun clock-latency-ns = <40000>; 219*4882a593Smuzhiyun }; 220*4882a593Smuzhiyun }; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun gpu_opp_table: opp-table2 { 223*4882a593Smuzhiyun compatible = "operating-points-v2"; 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun rockchip,thermal-zone = "soc-thermal"; 226*4882a593Smuzhiyun rockchip,temp-hysteresis = <5000>; 227*4882a593Smuzhiyun rockchip,low-temp = <10000>; 228*4882a593Smuzhiyun rockchip,low-temp-min-volt = <900000>; 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun nvmem-cells = <&gpu_leakage>; 231*4882a593Smuzhiyun nvmem-cell-names = "gpu_leakage"; 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun rockchip,pvtm-voltage-sel = < 234*4882a593Smuzhiyun 0 121000 0 235*4882a593Smuzhiyun 121001 125500 1 236*4882a593Smuzhiyun 125501 128500 2 237*4882a593Smuzhiyun 128501 999999 3 238*4882a593Smuzhiyun >; 239*4882a593Smuzhiyun rockchip,pvtm-freq = <200000>; 240*4882a593Smuzhiyun rockchip,pvtm-volt = <900000>; 241*4882a593Smuzhiyun rockchip,pvtm-ch = <3 0>; 242*4882a593Smuzhiyun rockchip,pvtm-sample-time = <1000>; 243*4882a593Smuzhiyun rockchip,pvtm-number = <10>; 244*4882a593Smuzhiyun rockchip,pvtm-error = <1000>; 245*4882a593Smuzhiyun rockchip,pvtm-ref-temp = <41>; 246*4882a593Smuzhiyun rockchip,pvtm-temp-prop = <46 12>; 247*4882a593Smuzhiyun rockchip,pvtm-thermal-zone = "gpu-thermal"; 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun opp-200000000 { 250*4882a593Smuzhiyun opp-hz = /bits/ 64 <200000000>; 251*4882a593Smuzhiyun opp-microvolt = <825000>; 252*4882a593Smuzhiyun opp-microvolt-L0 = <825000>; 253*4882a593Smuzhiyun opp-microvolt-L1 = <825000>; 254*4882a593Smuzhiyun opp-microvolt-L2 = <825000>; 255*4882a593Smuzhiyun opp-microvolt-L3 = <825000>; 256*4882a593Smuzhiyun }; 257*4882a593Smuzhiyun opp-300000000 { 258*4882a593Smuzhiyun opp-hz = /bits/ 64 <300000000>; 259*4882a593Smuzhiyun opp-microvolt = <825000>; 260*4882a593Smuzhiyun opp-microvolt-L0 = <825000>; 261*4882a593Smuzhiyun opp-microvolt-L1 = <825000>; 262*4882a593Smuzhiyun opp-microvolt-L2 = <825000>; 263*4882a593Smuzhiyun opp-microvolt-L3 = <825000>; 264*4882a593Smuzhiyun }; 265*4882a593Smuzhiyun opp-400000000 { 266*4882a593Smuzhiyun opp-hz = /bits/ 64 <400000000>; 267*4882a593Smuzhiyun opp-microvolt = <825000>; 268*4882a593Smuzhiyun opp-microvolt-L0 = <825000>; 269*4882a593Smuzhiyun opp-microvolt-L1 = <825000>; 270*4882a593Smuzhiyun opp-microvolt-L2 = <825000>; 271*4882a593Smuzhiyun opp-microvolt-L3 = <825000>; 272*4882a593Smuzhiyun }; 273*4882a593Smuzhiyun opp-600000000 { 274*4882a593Smuzhiyun opp-hz = /bits/ 64 <600000000>; 275*4882a593Smuzhiyun opp-microvolt = <925000>; 276*4882a593Smuzhiyun opp-microvolt-L0 = <925000>; 277*4882a593Smuzhiyun opp-microvolt-L1 = <925000>; 278*4882a593Smuzhiyun opp-microvolt-L2 = <900000>; 279*4882a593Smuzhiyun opp-microvolt-L3 = <900000>; 280*4882a593Smuzhiyun }; 281*4882a593Smuzhiyun opp-800000000 { 282*4882a593Smuzhiyun opp-hz = /bits/ 64 <800000000>; 283*4882a593Smuzhiyun opp-microvolt = <1100000>; 284*4882a593Smuzhiyun opp-microvolt-L0 = <1100000>; 285*4882a593Smuzhiyun opp-microvolt-L1 = <1075000>; 286*4882a593Smuzhiyun opp-microvolt-L2 = <1050000>; 287*4882a593Smuzhiyun opp-microvolt-L3 = <1025000>; 288*4882a593Smuzhiyun }; 289*4882a593Smuzhiyun }; 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun dmc_opp_table: opp-table3 { 292*4882a593Smuzhiyun compatible = "operating-points-v2"; 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun opp-200000000 { 295*4882a593Smuzhiyun opp-hz = /bits/ 64 <200000000>; 296*4882a593Smuzhiyun opp-microvolt = <900000>; 297*4882a593Smuzhiyun }; 298*4882a593Smuzhiyun opp-300000000 { 299*4882a593Smuzhiyun opp-hz = /bits/ 64 <300000000>; 300*4882a593Smuzhiyun opp-microvolt = <900000>; 301*4882a593Smuzhiyun }; 302*4882a593Smuzhiyun opp-400000000 { 303*4882a593Smuzhiyun opp-hz = /bits/ 64 <400000000>; 304*4882a593Smuzhiyun opp-microvolt = <900000>; 305*4882a593Smuzhiyun }; 306*4882a593Smuzhiyun opp-528000000 { 307*4882a593Smuzhiyun opp-hz = /bits/ 64 <528000000>; 308*4882a593Smuzhiyun opp-microvolt = <900000>; 309*4882a593Smuzhiyun }; 310*4882a593Smuzhiyun opp-600000000 { 311*4882a593Smuzhiyun opp-hz = /bits/ 64 <600000000>; 312*4882a593Smuzhiyun opp-microvolt = <900000>; 313*4882a593Smuzhiyun }; 314*4882a593Smuzhiyun opp-800000000 { 315*4882a593Smuzhiyun opp-hz = /bits/ 64 <800000000>; 316*4882a593Smuzhiyun opp-microvolt = <900000>; 317*4882a593Smuzhiyun }; 318*4882a593Smuzhiyun }; 319*4882a593Smuzhiyun}; 320*4882a593Smuzhiyun 321*4882a593Smuzhiyun&cpu_l0 { 322*4882a593Smuzhiyun operating-points-v2 = <&cluster0_opp>; 323*4882a593Smuzhiyun sched-energy-costs = <&RK3399_CPU_COST_0 &RK3399_CLUSTER_COST_0>; 324*4882a593Smuzhiyun}; 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun&cpu_l1 { 327*4882a593Smuzhiyun operating-points-v2 = <&cluster0_opp>; 328*4882a593Smuzhiyun sched-energy-costs = <&RK3399_CPU_COST_0 &RK3399_CLUSTER_COST_0>; 329*4882a593Smuzhiyun}; 330*4882a593Smuzhiyun 331*4882a593Smuzhiyun&cpu_l2 { 332*4882a593Smuzhiyun operating-points-v2 = <&cluster0_opp>; 333*4882a593Smuzhiyun sched-energy-costs = <&RK3399_CPU_COST_0 &RK3399_CLUSTER_COST_0>; 334*4882a593Smuzhiyun}; 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun&cpu_l3 { 337*4882a593Smuzhiyun operating-points-v2 = <&cluster0_opp>; 338*4882a593Smuzhiyun sched-energy-costs = <&RK3399_CPU_COST_0 &RK3399_CLUSTER_COST_0>; 339*4882a593Smuzhiyun}; 340*4882a593Smuzhiyun 341*4882a593Smuzhiyun&cpu_b0 { 342*4882a593Smuzhiyun operating-points-v2 = <&cluster1_opp>; 343*4882a593Smuzhiyun sched-energy-costs = <&RK3399_CPU_COST_1 &RK3399_CLUSTER_COST_1>; 344*4882a593Smuzhiyun}; 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun&cpu_b1 { 347*4882a593Smuzhiyun operating-points-v2 = <&cluster1_opp>; 348*4882a593Smuzhiyun sched-energy-costs = <&RK3399_CPU_COST_1 &RK3399_CLUSTER_COST_1>; 349*4882a593Smuzhiyun}; 350*4882a593Smuzhiyun 351*4882a593Smuzhiyun&dmc { 352*4882a593Smuzhiyun operating-points-v2 = <&dmc_opp_table>; 353*4882a593Smuzhiyun}; 354*4882a593Smuzhiyun 355*4882a593Smuzhiyun&gpu { 356*4882a593Smuzhiyun operating-points-v2 = <&gpu_opp_table>; 357*4882a593Smuzhiyun}; 358