1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun#include <dt-bindings/sensor-dev.h> 9*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 10*4882a593Smuzhiyun#include <dt-bindings/display/mipi_dsi.h> 11*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h> 12*4882a593Smuzhiyun#include "rk3399.dtsi" 13*4882a593Smuzhiyun#include "rk3399-android.dtsi" 14*4882a593Smuzhiyun#include "rk3399-opp.dtsi" 15*4882a593Smuzhiyun#include "rk3399-vop-clk-set.dtsi" 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun/ { 18*4882a593Smuzhiyun compatible = "rockchip,rk3399-mid", "rockchip,rk3399"; 19*4882a593Smuzhiyun chosen: chosen { 20*4882a593Smuzhiyun bootargs = "earlycon=uart8250,mmio32,0xff1a0000 console=ttyFIQ0 init=/init initrd=0x62000001,0x00800000 coherent_pool=1m"; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun adc_keys { 24*4882a593Smuzhiyun compatible = "adc-keys"; 25*4882a593Smuzhiyun io-channels = <&saradc 1>; 26*4882a593Smuzhiyun io-channel-names = "buttons"; 27*4882a593Smuzhiyun keyup-threshold-microvolt = <1800000>; 28*4882a593Smuzhiyun poll-interval = <100>; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun vol-up-key { 31*4882a593Smuzhiyun label = "volume up"; 32*4882a593Smuzhiyun linux,code = <KEY_VOLUMEUP>; 33*4882a593Smuzhiyun press-threshold-microvolt = <1000>; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun vol-down-key { 37*4882a593Smuzhiyun label = "volume down"; 38*4882a593Smuzhiyun linux,code = <KEY_VOLUMEDOWN>; 39*4882a593Smuzhiyun press-threshold-microvolt = <170000>; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun rk_headset: rk-headset { 44*4882a593Smuzhiyun compatible = "rockchip_headset"; 45*4882a593Smuzhiyun headset_gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; 46*4882a593Smuzhiyun pinctrl-names = "default"; 47*4882a593Smuzhiyun pinctrl-0 = <&hp_det>; 48*4882a593Smuzhiyun io-channels = <&saradc 2>; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun charge-animation { 52*4882a593Smuzhiyun compatible = "rockchip,uboot-charge"; 53*4882a593Smuzhiyun rockchip,uboot-charge-on = <1>; 54*4882a593Smuzhiyun rockchip,android-charge-on = <0>; 55*4882a593Smuzhiyun rockchip,uboot-low-power-voltage = <6700>; 56*4882a593Smuzhiyun rockchip,screen-on-voltage = <6800>; 57*4882a593Smuzhiyun status = "okay"; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun sdio_pwrseq: sdio-pwrseq { 61*4882a593Smuzhiyun compatible = "mmc-pwrseq-simple"; 62*4882a593Smuzhiyun clocks = <&rk818 1>; 63*4882a593Smuzhiyun clock-names = "ext_clock"; 64*4882a593Smuzhiyun pinctrl-names = "default"; 65*4882a593Smuzhiyun pinctrl-0 = <&wifi_enable_h>; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* 68*4882a593Smuzhiyun * On the module itself this is one of these (depending 69*4882a593Smuzhiyun * on the actual card populated): 70*4882a593Smuzhiyun * - SDIO_RESET_L_WL_REG_ON 71*4882a593Smuzhiyun * - PDN (power down when low) 72*4882a593Smuzhiyun */ 73*4882a593Smuzhiyun reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */ 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun hall_sensor: hall-mh248 { 77*4882a593Smuzhiyun compatible = "hall-mh248"; 78*4882a593Smuzhiyun pinctrl-names = "default"; 79*4882a593Smuzhiyun pinctrl-0 = <&mh248_irq_gpio>; 80*4882a593Smuzhiyun irq-gpio = <&gpio1 2 IRQ_TYPE_EDGE_BOTH>; 81*4882a593Smuzhiyun hall-active = <1>; 82*4882a593Smuzhiyun status = "okay"; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun vcc_sys: vcc-sys { 86*4882a593Smuzhiyun compatible = "regulator-fixed"; 87*4882a593Smuzhiyun regulator-name = "vcc_sys"; 88*4882a593Smuzhiyun regulator-always-on; 89*4882a593Smuzhiyun regulator-boot-on; 90*4882a593Smuzhiyun regulator-min-microvolt = <3900000>; 91*4882a593Smuzhiyun regulator-max-microvolt = <3900000>; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun vcc3v3_sys: vcc3v3-sys { 95*4882a593Smuzhiyun compatible = "regulator-fixed"; 96*4882a593Smuzhiyun regulator-name = "vcc3v3_sys"; 97*4882a593Smuzhiyun regulator-always-on; 98*4882a593Smuzhiyun regulator-boot-on; 99*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 100*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun vcc5v0_host: vcc5v0-host-regulator { 104*4882a593Smuzhiyun compatible = "regulator-fixed"; 105*4882a593Smuzhiyun enable-active-high; 106*4882a593Smuzhiyun gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; 107*4882a593Smuzhiyun pinctrl-names = "default"; 108*4882a593Smuzhiyun pinctrl-0 = <&host_vbus_drv>; 109*4882a593Smuzhiyun regulator-name = "vcc5v0_host"; 110*4882a593Smuzhiyun regulator-always-on; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun vdd_log: vdd-log { 114*4882a593Smuzhiyun compatible = "pwm-regulator"; 115*4882a593Smuzhiyun pwms = <&pwm2 0 25000 1>; 116*4882a593Smuzhiyun rockchip,pwm_id= <2>; 117*4882a593Smuzhiyun rockchip,pwm_voltage = <900000>; 118*4882a593Smuzhiyun regulator-name = "vdd_log"; 119*4882a593Smuzhiyun regulator-min-microvolt = <750000>; 120*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 121*4882a593Smuzhiyun regulator-always-on; 122*4882a593Smuzhiyun regulator-boot-on; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun xin32k: xin32k { 126*4882a593Smuzhiyun compatible = "fixed-clock"; 127*4882a593Smuzhiyun clock-frequency = <32768>; 128*4882a593Smuzhiyun clock-output-names = "xin32k"; 129*4882a593Smuzhiyun #clock-cells = <0>; 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun edp_panel: edp-panel { 133*4882a593Smuzhiyun compatible = "lg,lp079qx1-sp0v", "panel-simple"; 134*4882a593Smuzhiyun bus-format = <MEDIA_BUS_FMT_RGB666_1X18>; 135*4882a593Smuzhiyun bpc = <6>; 136*4882a593Smuzhiyun backlight = <&backlight>; 137*4882a593Smuzhiyun power-supply = <&vcc3v3_s0>; 138*4882a593Smuzhiyun enable-gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; 139*4882a593Smuzhiyun ports { 140*4882a593Smuzhiyun panel_in_edp: endpoint { 141*4882a593Smuzhiyun remote-endpoint = <&edp_out_panel>; 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun }; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun backlight: backlight { 147*4882a593Smuzhiyun compatible = "pwm-backlight"; 148*4882a593Smuzhiyun pwms = <&pwm0 0 25000 0>; 149*4882a593Smuzhiyun brightness-levels = < 150*4882a593Smuzhiyun 255 200 199 198 197 197 196 195 194 193 193 192 151*4882a593Smuzhiyun 191 190 189 189 188 187 186 185 185 184 183 182 152*4882a593Smuzhiyun 181 181 180 179 178 177 177 176 175 174 173 173 153*4882a593Smuzhiyun 172 171 170 169 169 168 167 166 165 165 164 163 154*4882a593Smuzhiyun 162 161 161 160 159 158 157 157 156 155 154 153 155*4882a593Smuzhiyun 153 152 151 150 149 149 148 147 146 145 145 144 156*4882a593Smuzhiyun 143 142 141 141 140 139 138 137 137 136 135 134 157*4882a593Smuzhiyun 133 133 132 131 130 129 129 128 127 126 125 125 158*4882a593Smuzhiyun 124 123 122 121 121 120 119 118 117 117 116 115 159*4882a593Smuzhiyun 114 113 113 112 111 110 109 109 108 107 106 105 160*4882a593Smuzhiyun 105 104 103 102 101 101 100 99 98 97 97 96 161*4882a593Smuzhiyun 95 94 93 93 92 91 90 89 89 88 87 86 162*4882a593Smuzhiyun 85 85 84 83 82 81 81 80 79 78 77 77 163*4882a593Smuzhiyun 76 75 74 73 73 72 71 70 69 69 68 67 164*4882a593Smuzhiyun 66 65 65 64 63 62 61 61 60 59 58 57 165*4882a593Smuzhiyun 57 56 55 54 53 53 52 51 50 49 49 48 166*4882a593Smuzhiyun 47 46 45 45 44 43 42 41 41 40 39 38 167*4882a593Smuzhiyun 37 37 36 35 34 33 33 32 31 30 29 29 168*4882a593Smuzhiyun 28 27 26 25 25 24 23 22 21 21 20 19 169*4882a593Smuzhiyun 18 17 17 16 15 14 13 13 12 11 10 9 170*4882a593Smuzhiyun 9 8 7 6 5 5 4 3 2 1 1 0 171*4882a593Smuzhiyun 0 0 0 0>; 172*4882a593Smuzhiyun default-brightness-level = <200>; 173*4882a593Smuzhiyun enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; 174*4882a593Smuzhiyun }; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun vcc_phy: vcc-phy-regulator { 177*4882a593Smuzhiyun compatible = "regulator-fixed"; 178*4882a593Smuzhiyun regulator-name = "vcc_phy"; 179*4882a593Smuzhiyun regulator-always-on; 180*4882a593Smuzhiyun regulator-boot-on; 181*4882a593Smuzhiyun }; 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun es8316-sound { 184*4882a593Smuzhiyun compatible = "simple-audio-card"; 185*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 186*4882a593Smuzhiyun simple-audio-card,name = "rockchip,es8316-codec"; 187*4882a593Smuzhiyun simple-audio-card,mclk-fs = <256>; 188*4882a593Smuzhiyun simple-audio-card,widgets = 189*4882a593Smuzhiyun "Microphone", "Mic Jack", 190*4882a593Smuzhiyun "Headphone", "Headphone Jack"; 191*4882a593Smuzhiyun simple-audio-card,routing = 192*4882a593Smuzhiyun "Mic Jack", "MICBIAS1", 193*4882a593Smuzhiyun "IN1P", "Mic Jack", 194*4882a593Smuzhiyun "Headphone Jack", "HPOL", 195*4882a593Smuzhiyun "Headphone Jack", "HPOR"; 196*4882a593Smuzhiyun simple-audio-card,cpu { 197*4882a593Smuzhiyun sound-dai = <&i2s0>; 198*4882a593Smuzhiyun }; 199*4882a593Smuzhiyun simple-audio-card,codec { 200*4882a593Smuzhiyun sound-dai = <&es8316>; 201*4882a593Smuzhiyun }; 202*4882a593Smuzhiyun }; 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun spdif-sound { 205*4882a593Smuzhiyun compatible = "simple-audio-card"; 206*4882a593Smuzhiyun simple-audio-card,name = "rockchip,spdif"; 207*4882a593Smuzhiyun simple-audio-card,mclk-fs = <128>; 208*4882a593Smuzhiyun simple-audio-card,cpu { 209*4882a593Smuzhiyun sound-dai = <&spdif>; 210*4882a593Smuzhiyun }; 211*4882a593Smuzhiyun simple-audio-card,codec { 212*4882a593Smuzhiyun sound-dai = <&spdif_out>; 213*4882a593Smuzhiyun }; 214*4882a593Smuzhiyun }; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun spdif_out: spdif-out { 217*4882a593Smuzhiyun compatible = "linux,spdif-dit"; 218*4882a593Smuzhiyun #sound-dai-cells = <0>; 219*4882a593Smuzhiyun }; 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun sdio_pwrseq: sdio-pwrseq { 222*4882a593Smuzhiyun compatible = "mmc-pwrseq-simple"; 223*4882a593Smuzhiyun clocks = <&rk818 1>; 224*4882a593Smuzhiyun clock-names = "ext_clock"; 225*4882a593Smuzhiyun pinctrl-names = "default"; 226*4882a593Smuzhiyun pinctrl-0 = <&wifi_enable_h>; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun /* 229*4882a593Smuzhiyun * On the module itself this is one of these (depending 230*4882a593Smuzhiyun * on the actual card populated): 231*4882a593Smuzhiyun * - SDIO_RESET_L_WL_REG_ON 232*4882a593Smuzhiyun * - PDN (power down when low) 233*4882a593Smuzhiyun */ 234*4882a593Smuzhiyun reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */ 235*4882a593Smuzhiyun }; 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun wireless-wlan { 238*4882a593Smuzhiyun compatible = "wlan-platdata"; 239*4882a593Smuzhiyun rockchip,grf = <&grf>; 240*4882a593Smuzhiyun wifi_chip_type = "ap6354"; 241*4882a593Smuzhiyun sdio_vref = <1800>; 242*4882a593Smuzhiyun WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; /* GPIO0_a3 */ 243*4882a593Smuzhiyun status = "okay"; 244*4882a593Smuzhiyun }; 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun wireless-bluetooth { 247*4882a593Smuzhiyun compatible = "bluetooth-platdata"; 248*4882a593Smuzhiyun clocks = <&rk818 1>; 249*4882a593Smuzhiyun clock-names = "ext_clock"; 250*4882a593Smuzhiyun //wifi-bt-power-toggle; 251*4882a593Smuzhiyun uart_rts_gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; /* GPIO2_C3 */ 252*4882a593Smuzhiyun pinctrl-names = "default", "rts_gpio"; 253*4882a593Smuzhiyun pinctrl-0 = <&uart0_rts>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; 254*4882a593Smuzhiyun pinctrl-1 = <&uart0_gpios>; 255*4882a593Smuzhiyun //BT,power_gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; /* GPIOx_xx */ 256*4882a593Smuzhiyun BT,reset_gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; /* GPIO0_B1 */ 257*4882a593Smuzhiyun BT,wake_gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>; /* GPIO2_D2 */ 258*4882a593Smuzhiyun BT,wake_host_irq = <&gpio0 4 GPIO_ACTIVE_HIGH>; /* GPIO0_A4 */ 259*4882a593Smuzhiyun status = "okay"; 260*4882a593Smuzhiyun }; 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun vibrator { 263*4882a593Smuzhiyun compatible = "rk-vibrator-gpio"; 264*4882a593Smuzhiyun vibrator-gpio = <&gpio4 30 GPIO_ACTIVE_LOW>; 265*4882a593Smuzhiyun status = "okay"; 266*4882a593Smuzhiyun }; 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun}; 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun&dfi { 271*4882a593Smuzhiyun status = "okay"; 272*4882a593Smuzhiyun}; 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun&dmc { 275*4882a593Smuzhiyun status = "okay"; 276*4882a593Smuzhiyun center-supply = <&vdd_center>; 277*4882a593Smuzhiyun upthreshold = <40>; 278*4882a593Smuzhiyun downdifferential = <20>; 279*4882a593Smuzhiyun system-status-freq = < 280*4882a593Smuzhiyun /*system status freq(KHz)*/ 281*4882a593Smuzhiyun SYS_STATUS_NORMAL 800000 282*4882a593Smuzhiyun SYS_STATUS_REBOOT 528000 283*4882a593Smuzhiyun SYS_STATUS_SUSPEND 200000 284*4882a593Smuzhiyun SYS_STATUS_VIDEO_1080P 200000 285*4882a593Smuzhiyun SYS_STATUS_VIDEO_4K 600000 286*4882a593Smuzhiyun SYS_STATUS_VIDEO_4K_10B 800000 287*4882a593Smuzhiyun SYS_STATUS_PERFORMANCE 800000 288*4882a593Smuzhiyun SYS_STATUS_BOOST 600000 289*4882a593Smuzhiyun SYS_STATUS_DUALVIEW 600000 290*4882a593Smuzhiyun SYS_STATUS_ISP 600000 291*4882a593Smuzhiyun >; 292*4882a593Smuzhiyun vop-bw-dmc-freq = < 293*4882a593Smuzhiyun /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */ 294*4882a593Smuzhiyun 0 762 200000 295*4882a593Smuzhiyun 763 1893 400000 296*4882a593Smuzhiyun 1894 3012 528000 297*4882a593Smuzhiyun 3013 99999 800000 298*4882a593Smuzhiyun >; 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun auto-min-freq = <200000>; 301*4882a593Smuzhiyun}; 302*4882a593Smuzhiyun 303*4882a593Smuzhiyun&sdmmc { 304*4882a593Smuzhiyun clock-frequency = <50000000>; 305*4882a593Smuzhiyun clock-freq-min-max = <400000 150000000>; 306*4882a593Smuzhiyun no-sdio; 307*4882a593Smuzhiyun no-mmc; 308*4882a593Smuzhiyun bus-width = <4>; 309*4882a593Smuzhiyun cap-mmc-highspeed; 310*4882a593Smuzhiyun cap-sd-highspeed; 311*4882a593Smuzhiyun disable-wp; 312*4882a593Smuzhiyun num-slots = <1>; 313*4882a593Smuzhiyun //sd-uhs-sdr104; 314*4882a593Smuzhiyun vqmmc-supply = <&vcc_sd>; 315*4882a593Smuzhiyun pinctrl-names = "default"; 316*4882a593Smuzhiyun pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; 317*4882a593Smuzhiyun status = "okay"; 318*4882a593Smuzhiyun}; 319*4882a593Smuzhiyun 320*4882a593Smuzhiyun&sdio0 { 321*4882a593Smuzhiyun clock-frequency = <150000000>; 322*4882a593Smuzhiyun clock-freq-min-max = <200000 150000000>; 323*4882a593Smuzhiyun no-sd; 324*4882a593Smuzhiyun no-mmc; 325*4882a593Smuzhiyun bus-width = <4>; 326*4882a593Smuzhiyun disable-wp; 327*4882a593Smuzhiyun cap-sd-highspeed; 328*4882a593Smuzhiyun cap-sdio-irq; 329*4882a593Smuzhiyun keep-power-in-suspend; 330*4882a593Smuzhiyun mmc-pwrseq = <&sdio_pwrseq>; 331*4882a593Smuzhiyun non-removable; 332*4882a593Smuzhiyun num-slots = <1>; 333*4882a593Smuzhiyun pinctrl-names = "default"; 334*4882a593Smuzhiyun pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; 335*4882a593Smuzhiyun sd-uhs-sdr104; 336*4882a593Smuzhiyun status = "okay"; 337*4882a593Smuzhiyun}; 338*4882a593Smuzhiyun 339*4882a593Smuzhiyun&emmc_phy { 340*4882a593Smuzhiyun status = "okay"; 341*4882a593Smuzhiyun}; 342*4882a593Smuzhiyun 343*4882a593Smuzhiyun&sdhci { 344*4882a593Smuzhiyun bus-width = <8>; 345*4882a593Smuzhiyun mmc-hs400-1_8v; 346*4882a593Smuzhiyun no-sdio; 347*4882a593Smuzhiyun no-sd; 348*4882a593Smuzhiyun non-removable; 349*4882a593Smuzhiyun keep-power-in-suspend; 350*4882a593Smuzhiyun mmc-hs400-enhanced-strobe; 351*4882a593Smuzhiyun status = "okay"; 352*4882a593Smuzhiyun}; 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun&i2s0 { 355*4882a593Smuzhiyun status = "okay"; 356*4882a593Smuzhiyun rockchip,i2s-broken-burst-len; 357*4882a593Smuzhiyun rockchip,playback-channels = <8>; 358*4882a593Smuzhiyun rockchip,capture-channels = <8>; 359*4882a593Smuzhiyun #sound-dai-cells = <0>; 360*4882a593Smuzhiyun}; 361*4882a593Smuzhiyun 362*4882a593Smuzhiyun&i2s2 { 363*4882a593Smuzhiyun #sound-dai-cells = <0>; 364*4882a593Smuzhiyun}; 365*4882a593Smuzhiyun 366*4882a593Smuzhiyun&spdif { 367*4882a593Smuzhiyun status = "disabled"; 368*4882a593Smuzhiyun #sound-dai-cells = <0>; 369*4882a593Smuzhiyun}; 370*4882a593Smuzhiyun 371*4882a593Smuzhiyun&i2c0 { 372*4882a593Smuzhiyun status = "okay"; 373*4882a593Smuzhiyun i2c-scl-rising-time-ns = <180>; 374*4882a593Smuzhiyun i2c-scl-falling-time-ns = <30>; 375*4882a593Smuzhiyun clock-frequency = <400000>; 376*4882a593Smuzhiyun 377*4882a593Smuzhiyun vdd_cpu_b: syr837@40 { 378*4882a593Smuzhiyun compatible = "silergy,syr827"; 379*4882a593Smuzhiyun reg = <0x40>; 380*4882a593Smuzhiyun vin-supply = <&vcc_sys>; 381*4882a593Smuzhiyun regulator-compatible = "fan53555-reg"; 382*4882a593Smuzhiyun pinctrl-0 = <&vsel1_gpio>; 383*4882a593Smuzhiyun vsel-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; 384*4882a593Smuzhiyun regulator-name = "vdd_cpu_b"; 385*4882a593Smuzhiyun regulator-min-microvolt = <712500>; 386*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 387*4882a593Smuzhiyun regulator-ramp-delay = <1000>; 388*4882a593Smuzhiyun fcs,suspend-voltage-selector = <1>; 389*4882a593Smuzhiyun regulator-always-on; 390*4882a593Smuzhiyun regulator-initial-state = <3>; 391*4882a593Smuzhiyun regulator-state-mem { 392*4882a593Smuzhiyun regulator-off-in-suspend; 393*4882a593Smuzhiyun }; 394*4882a593Smuzhiyun }; 395*4882a593Smuzhiyun 396*4882a593Smuzhiyun vdd_gpu: syr828@41 { 397*4882a593Smuzhiyun compatible = "silergy,syr828"; 398*4882a593Smuzhiyun status = "okay"; 399*4882a593Smuzhiyun reg = <0x41>; 400*4882a593Smuzhiyun vin-supply = <&vcc_sys>; 401*4882a593Smuzhiyun regulator-compatible = "fan53555-reg"; 402*4882a593Smuzhiyun pinctrl-0 = <&vsel2_gpio>; 403*4882a593Smuzhiyun vsel-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; 404*4882a593Smuzhiyun regulator-name = "vdd_gpu"; 405*4882a593Smuzhiyun regulator-min-microvolt = <735000>; 406*4882a593Smuzhiyun regulator-max-microvolt = <1400000>; 407*4882a593Smuzhiyun regulator-ramp-delay = <1000>; 408*4882a593Smuzhiyun fcs,suspend-voltage-selector = <1>; 409*4882a593Smuzhiyun regulator-always-on; 410*4882a593Smuzhiyun regulator-boot-on; 411*4882a593Smuzhiyun regulator-state-mem { 412*4882a593Smuzhiyun regulator-off-in-suspend; 413*4882a593Smuzhiyun }; 414*4882a593Smuzhiyun }; 415*4882a593Smuzhiyun 416*4882a593Smuzhiyun rk818: pmic@1c { 417*4882a593Smuzhiyun compatible = "rockchip,rk818"; 418*4882a593Smuzhiyun status = "okay"; 419*4882a593Smuzhiyun reg = <0x1c>; 420*4882a593Smuzhiyun clock-output-names = "rk818-clkout1", "wifibt_32kin"; 421*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 422*4882a593Smuzhiyun interrupts = <21 IRQ_TYPE_LEVEL_LOW>; 423*4882a593Smuzhiyun pinctrl-names = "default"; 424*4882a593Smuzhiyun pinctrl-0 = <&pmic_int_l>; 425*4882a593Smuzhiyun rockchip,system-power-controller; 426*4882a593Smuzhiyun rk818,support_dc_chg = <1>;/*1: dc chg; 0:usb chg*/ 427*4882a593Smuzhiyun wakeup-source; 428*4882a593Smuzhiyun extcon = <&fusb0>; 429*4882a593Smuzhiyun #clock-cells = <1>; 430*4882a593Smuzhiyun 431*4882a593Smuzhiyun vcc1-supply = <&vcc_sys>; 432*4882a593Smuzhiyun vcc2-supply = <&vcc_sys>; 433*4882a593Smuzhiyun vcc3-supply = <&vcc_sys>; 434*4882a593Smuzhiyun vcc4-supply = <&vcc_sys>; 435*4882a593Smuzhiyun vcc6-supply = <&vcc_sys>; 436*4882a593Smuzhiyun vcc7-supply = <&vcc3v3_sys>; 437*4882a593Smuzhiyun vcc8-supply = <&vcc_sys>; 438*4882a593Smuzhiyun vcc9-supply = <&vcc3v3_sys>; 439*4882a593Smuzhiyun 440*4882a593Smuzhiyun regulators { 441*4882a593Smuzhiyun vdd_cpu_l: DCDC_REG1 { 442*4882a593Smuzhiyun regulator-name = "vdd_cpu_l"; 443*4882a593Smuzhiyun regulator-always-on; 444*4882a593Smuzhiyun regulator-boot-on; 445*4882a593Smuzhiyun regulator-min-microvolt = <750000>; 446*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 447*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 448*4882a593Smuzhiyun regulator-state-mem { 449*4882a593Smuzhiyun regulator-off-in-suspend; 450*4882a593Smuzhiyun }; 451*4882a593Smuzhiyun }; 452*4882a593Smuzhiyun 453*4882a593Smuzhiyun vdd_center: DCDC_REG2 { 454*4882a593Smuzhiyun regulator-name = "vdd_center"; 455*4882a593Smuzhiyun regulator-always-on; 456*4882a593Smuzhiyun regulator-boot-on; 457*4882a593Smuzhiyun regulator-min-microvolt = <800000>; 458*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 459*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 460*4882a593Smuzhiyun regulator-state-mem { 461*4882a593Smuzhiyun regulator-off-in-suspend; 462*4882a593Smuzhiyun }; 463*4882a593Smuzhiyun }; 464*4882a593Smuzhiyun 465*4882a593Smuzhiyun vcc_ddr: DCDC_REG3 { 466*4882a593Smuzhiyun regulator-name = "vcc_ddr"; 467*4882a593Smuzhiyun regulator-always-on; 468*4882a593Smuzhiyun regulator-boot-on; 469*4882a593Smuzhiyun regulator-state-mem { 470*4882a593Smuzhiyun regulator-on-in-suspend; 471*4882a593Smuzhiyun }; 472*4882a593Smuzhiyun }; 473*4882a593Smuzhiyun 474*4882a593Smuzhiyun vcc_1v8: DCDC_REG4 { 475*4882a593Smuzhiyun regulator-name = "vcc_1v8"; 476*4882a593Smuzhiyun regulator-always-on; 477*4882a593Smuzhiyun regulator-boot-on; 478*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 479*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 480*4882a593Smuzhiyun regulator-state-mem { 481*4882a593Smuzhiyun regulator-on-in-suspend; 482*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 483*4882a593Smuzhiyun }; 484*4882a593Smuzhiyun }; 485*4882a593Smuzhiyun 486*4882a593Smuzhiyun vcca3v0_codec: LDO_REG1 { 487*4882a593Smuzhiyun regulator-always-on; 488*4882a593Smuzhiyun regulator-boot-on; 489*4882a593Smuzhiyun regulator-min-microvolt = <3000000>; 490*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 491*4882a593Smuzhiyun regulator-name = "vcca3v0_codec"; 492*4882a593Smuzhiyun regulator-state-mem { 493*4882a593Smuzhiyun regulator-off-in-suspend; 494*4882a593Smuzhiyun }; 495*4882a593Smuzhiyun }; 496*4882a593Smuzhiyun 497*4882a593Smuzhiyun vcc3v0_tp: LDO_REG2 { 498*4882a593Smuzhiyun regulator-always-on; 499*4882a593Smuzhiyun regulator-boot-on; 500*4882a593Smuzhiyun regulator-min-microvolt = <3000000>; 501*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 502*4882a593Smuzhiyun regulator-name = "vcc3v0_tp"; 503*4882a593Smuzhiyun regulator-state-mem { 504*4882a593Smuzhiyun regulator-off-in-suspend; 505*4882a593Smuzhiyun }; 506*4882a593Smuzhiyun }; 507*4882a593Smuzhiyun 508*4882a593Smuzhiyun vcca1v8_codec: LDO_REG3 { 509*4882a593Smuzhiyun regulator-always-on; 510*4882a593Smuzhiyun regulator-boot-on; 511*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 512*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 513*4882a593Smuzhiyun regulator-name = "vcca1v8_codec"; 514*4882a593Smuzhiyun regulator-state-mem { 515*4882a593Smuzhiyun regulator-off-in-suspend; 516*4882a593Smuzhiyun }; 517*4882a593Smuzhiyun }; 518*4882a593Smuzhiyun 519*4882a593Smuzhiyun vcc_power_on: LDO_REG4 { 520*4882a593Smuzhiyun regulator-always-on; 521*4882a593Smuzhiyun regulator-boot-on; 522*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 523*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 524*4882a593Smuzhiyun regulator-name = "vcc_power_on"; 525*4882a593Smuzhiyun regulator-state-mem { 526*4882a593Smuzhiyun regulator-on-in-suspend; 527*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 528*4882a593Smuzhiyun }; 529*4882a593Smuzhiyun }; 530*4882a593Smuzhiyun 531*4882a593Smuzhiyun vcc_3v0: LDO_REG5 { 532*4882a593Smuzhiyun regulator-always-on; 533*4882a593Smuzhiyun regulator-boot-on; 534*4882a593Smuzhiyun regulator-min-microvolt = <3000000>; 535*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 536*4882a593Smuzhiyun regulator-name = "vcc_3v0"; 537*4882a593Smuzhiyun regulator-state-mem { 538*4882a593Smuzhiyun regulator-on-in-suspend; 539*4882a593Smuzhiyun regulator-suspend-microvolt = <3000000>; 540*4882a593Smuzhiyun }; 541*4882a593Smuzhiyun }; 542*4882a593Smuzhiyun 543*4882a593Smuzhiyun vcc_1v5: LDO_REG6 { 544*4882a593Smuzhiyun regulator-always-on; 545*4882a593Smuzhiyun regulator-boot-on; 546*4882a593Smuzhiyun regulator-min-microvolt = <1500000>; 547*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 548*4882a593Smuzhiyun regulator-name = "vcc_1v5"; 549*4882a593Smuzhiyun regulator-state-mem { 550*4882a593Smuzhiyun regulator-on-in-suspend; 551*4882a593Smuzhiyun regulator-suspend-microvolt = <1500000>; 552*4882a593Smuzhiyun }; 553*4882a593Smuzhiyun }; 554*4882a593Smuzhiyun 555*4882a593Smuzhiyun vcc1v8_dvp: LDO_REG7 { 556*4882a593Smuzhiyun regulator-always-on; 557*4882a593Smuzhiyun regulator-boot-on; 558*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 559*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 560*4882a593Smuzhiyun regulator-name = "vcc1v8_dvp"; 561*4882a593Smuzhiyun regulator-state-mem { 562*4882a593Smuzhiyun regulator-off-in-suspend; 563*4882a593Smuzhiyun }; 564*4882a593Smuzhiyun }; 565*4882a593Smuzhiyun 566*4882a593Smuzhiyun vcc3v3_s3: LDO_REG8 { 567*4882a593Smuzhiyun regulator-always-on; 568*4882a593Smuzhiyun regulator-boot-on; 569*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 570*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 571*4882a593Smuzhiyun regulator-name = "vcc3v3_s3"; 572*4882a593Smuzhiyun regulator-state-mem { 573*4882a593Smuzhiyun regulator-off-in-suspend; 574*4882a593Smuzhiyun }; 575*4882a593Smuzhiyun }; 576*4882a593Smuzhiyun 577*4882a593Smuzhiyun vcc_sd: LDO_REG9 { 578*4882a593Smuzhiyun regulator-always-on; 579*4882a593Smuzhiyun regulator-boot-on; 580*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 581*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 582*4882a593Smuzhiyun regulator-name = "vcc_sd"; 583*4882a593Smuzhiyun regulator-state-mem { 584*4882a593Smuzhiyun regulator-on-in-suspend; 585*4882a593Smuzhiyun regulator-suspend-microvolt = <3000000>; 586*4882a593Smuzhiyun }; 587*4882a593Smuzhiyun }; 588*4882a593Smuzhiyun 589*4882a593Smuzhiyun vcc3v3_s0: SWITCH_REG { 590*4882a593Smuzhiyun regulator-always-on; 591*4882a593Smuzhiyun regulator-boot-on; 592*4882a593Smuzhiyun regulator-name = "vcc3v3_s0"; 593*4882a593Smuzhiyun regulator-state-mem { 594*4882a593Smuzhiyun regulator-on-in-suspend; 595*4882a593Smuzhiyun }; 596*4882a593Smuzhiyun }; 597*4882a593Smuzhiyun 598*4882a593Smuzhiyun boost_otg: DCDC_BOOST { 599*4882a593Smuzhiyun regulator-name = "boost_otg"; 600*4882a593Smuzhiyun regulator-always-on; 601*4882a593Smuzhiyun regulator-boot-on; 602*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 603*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 604*4882a593Smuzhiyun regulator-state-mem { 605*4882a593Smuzhiyun regulator-on-in-suspend; 606*4882a593Smuzhiyun regulator-suspend-microvolt = <5000000>; 607*4882a593Smuzhiyun }; 608*4882a593Smuzhiyun }; 609*4882a593Smuzhiyun 610*4882a593Smuzhiyun otg_switch: OTG_SWITCH { 611*4882a593Smuzhiyun regulator-name = "otg_switch"; 612*4882a593Smuzhiyun }; 613*4882a593Smuzhiyun }; 614*4882a593Smuzhiyun 615*4882a593Smuzhiyun battery { 616*4882a593Smuzhiyun compatible = "rk818-battery"; 617*4882a593Smuzhiyun ocv_table = <3400 3675 3689 3716 3740 3756 3768 3780 618*4882a593Smuzhiyun 3793 3807 3827 3853 3896 3937 3974 4007 4066 619*4882a593Smuzhiyun 4110 4161 4217 4308>; 620*4882a593Smuzhiyun design_capacity = <7916>; 621*4882a593Smuzhiyun design_qmax = <8708>; 622*4882a593Smuzhiyun bat_res = <65>; 623*4882a593Smuzhiyun max_input_current = <3000>; 624*4882a593Smuzhiyun max_chrg_current = <3000>; 625*4882a593Smuzhiyun max_chrg_voltage = <4350>; 626*4882a593Smuzhiyun sleep_enter_current = <300>; 627*4882a593Smuzhiyun sleep_exit_current = <300>; 628*4882a593Smuzhiyun power_off_thresd = <3400>; 629*4882a593Smuzhiyun zero_algorithm_vol = <3950>; 630*4882a593Smuzhiyun fb_temperature = <105>; 631*4882a593Smuzhiyun sample_res = <20>; 632*4882a593Smuzhiyun max_soc_offset = <60>; 633*4882a593Smuzhiyun energy_mode = <0>; 634*4882a593Smuzhiyun monitor_sec = <5>; 635*4882a593Smuzhiyun virtual_power = <0>; 636*4882a593Smuzhiyun power_dc2otg = <0>; 637*4882a593Smuzhiyun }; 638*4882a593Smuzhiyun }; 639*4882a593Smuzhiyun}; 640*4882a593Smuzhiyun 641*4882a593Smuzhiyun&i2c1 { 642*4882a593Smuzhiyun status = "okay"; 643*4882a593Smuzhiyun i2c-scl-rising-time-ns = <140>; 644*4882a593Smuzhiyun i2c-scl-falling-time-ns = <30>; 645*4882a593Smuzhiyun 646*4882a593Smuzhiyun es8316: es8316@10 { 647*4882a593Smuzhiyun #sound-dai-cells = <0>; 648*4882a593Smuzhiyun compatible = "everest,es8316"; 649*4882a593Smuzhiyun reg = <0x11>; 650*4882a593Smuzhiyun clocks = <&cru SCLK_I2S_8CH_OUT>; 651*4882a593Smuzhiyun clock-names = "mclk"; 652*4882a593Smuzhiyun pinctrl-names = "default"; 653*4882a593Smuzhiyun pinctrl-0 = <&i2s_8ch_mclk>; 654*4882a593Smuzhiyun spk-con-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; 655*4882a593Smuzhiyun }; 656*4882a593Smuzhiyun}; 657*4882a593Smuzhiyun 658*4882a593Smuzhiyun&i2c4 { 659*4882a593Smuzhiyun status = "okay"; 660*4882a593Smuzhiyun i2c-scl-rising-time-ns = <345>; 661*4882a593Smuzhiyun i2c-scl-falling-time-ns = <11>; 662*4882a593Smuzhiyun clock-frequency = <400000>; 663*4882a593Smuzhiyun 664*4882a593Smuzhiyun lsm330_accel@1e { 665*4882a593Smuzhiyun status = "okay"; 666*4882a593Smuzhiyun compatible = "lsm330_acc"; 667*4882a593Smuzhiyun pinctrl-names = "default"; 668*4882a593Smuzhiyun pinctrl-0 = <&lsm330a_irq_gpio>; 669*4882a593Smuzhiyun reg = <0x1e>; 670*4882a593Smuzhiyun irq-gpio = <&gpio2 27 IRQ_TYPE_EDGE_RISING>; 671*4882a593Smuzhiyun type = <SENSOR_TYPE_ACCEL>; 672*4882a593Smuzhiyun irq_enable = <1>; 673*4882a593Smuzhiyun poll_delay_ms = <30>; 674*4882a593Smuzhiyun power-off-in-suspend = <1>; 675*4882a593Smuzhiyun layout = <4>; 676*4882a593Smuzhiyun }; 677*4882a593Smuzhiyun 678*4882a593Smuzhiyun lsm330_gyro@6a { 679*4882a593Smuzhiyun status = "okay"; 680*4882a593Smuzhiyun compatible = "lsm330_gyro"; 681*4882a593Smuzhiyun pinctrl-names = "default"; 682*4882a593Smuzhiyun pinctrl-0 = <&lsm330g_irq_gpio>; 683*4882a593Smuzhiyun reg = <0x6a>; 684*4882a593Smuzhiyun irq-gpio = <&gpio1 20 IRQ_TYPE_EDGE_RISING>; 685*4882a593Smuzhiyun type = <SENSOR_TYPE_GYROSCOPE>; 686*4882a593Smuzhiyun irq_enable = <0>; 687*4882a593Smuzhiyun power-off-in-suspend = <1>; 688*4882a593Smuzhiyun poll_delay_ms = <30>; 689*4882a593Smuzhiyun }; 690*4882a593Smuzhiyun 691*4882a593Smuzhiyun mpu6500@68 { 692*4882a593Smuzhiyun status = "disabled"; 693*4882a593Smuzhiyun compatible = "invensense,mpu6500"; 694*4882a593Smuzhiyun pinctrl-names = "default"; 695*4882a593Smuzhiyun pinctrl-0 = <&mpu6500_irq_gpio>; 696*4882a593Smuzhiyun reg = <0x68>; 697*4882a593Smuzhiyun irq-gpio = <&gpio2 27 IRQ_TYPE_EDGE_RISING>; 698*4882a593Smuzhiyun mpu-int_config = <0x10>; 699*4882a593Smuzhiyun mpu-level_shifter = <0>; 700*4882a593Smuzhiyun mpu-orientation = <1 0 0 0 1 0 0 0 1>; 701*4882a593Smuzhiyun orientation-x= <1>; 702*4882a593Smuzhiyun orientation-y= <1>; 703*4882a593Smuzhiyun orientation-z= <0>; 704*4882a593Smuzhiyun support-hw-poweroff = <1>; 705*4882a593Smuzhiyun mpu-debug = <1>; 706*4882a593Smuzhiyun }; 707*4882a593Smuzhiyun 708*4882a593Smuzhiyun sensor@0d { 709*4882a593Smuzhiyun status = "okay"; 710*4882a593Smuzhiyun compatible = "ak8963"; 711*4882a593Smuzhiyun pinctrl-names = "default"; 712*4882a593Smuzhiyun pinctrl-0 = <&ak8963_irq_gpio>; 713*4882a593Smuzhiyun reg = <0x0d>; 714*4882a593Smuzhiyun type = <SENSOR_TYPE_COMPASS>; 715*4882a593Smuzhiyun irq-gpio = <&gpio2 28 IRQ_TYPE_EDGE_RISING>; 716*4882a593Smuzhiyun irq_enable = <0>; 717*4882a593Smuzhiyun poll_delay_ms = <30>; 718*4882a593Smuzhiyun layout = <3>; 719*4882a593Smuzhiyun }; 720*4882a593Smuzhiyun 721*4882a593Smuzhiyun sensor@10 { 722*4882a593Smuzhiyun status = "okay"; 723*4882a593Smuzhiyun compatible = "capella,light_cm3218"; 724*4882a593Smuzhiyun pinctrl-names = "default"; 725*4882a593Smuzhiyun pinctrl-0 = <&cm3218_irq_gpio>; 726*4882a593Smuzhiyun reg = <0x10>; 727*4882a593Smuzhiyun type = <SENSOR_TYPE_LIGHT>; 728*4882a593Smuzhiyun irq-gpio = <&gpio4 24 IRQ_TYPE_EDGE_FALLING>; 729*4882a593Smuzhiyun irq_enable = <1>; 730*4882a593Smuzhiyun poll_delay_ms = <30>; 731*4882a593Smuzhiyun }; 732*4882a593Smuzhiyun 733*4882a593Smuzhiyun fusb0: fusb30x@22 { 734*4882a593Smuzhiyun compatible = "fairchild,fusb302"; 735*4882a593Smuzhiyun reg = <0x22>; 736*4882a593Smuzhiyun pinctrl-names = "default"; 737*4882a593Smuzhiyun pinctrl-0 = <&fusb0_int>; 738*4882a593Smuzhiyun int-n-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; 739*4882a593Smuzhiyun status = "okay"; 740*4882a593Smuzhiyun }; 741*4882a593Smuzhiyun}; 742*4882a593Smuzhiyun 743*4882a593Smuzhiyun&i2c5 { 744*4882a593Smuzhiyun status = "okay"; 745*4882a593Smuzhiyun i2c-scl-rising-time-ns = <150>; 746*4882a593Smuzhiyun i2c-scl-falling-time-ns = <30>; 747*4882a593Smuzhiyun clock-frequency = <400000>; 748*4882a593Smuzhiyun 749*4882a593Smuzhiyun gt9xx: gt9xx@14 { 750*4882a593Smuzhiyun compatible = "goodix,gt9xx"; 751*4882a593Smuzhiyun reg = <0x14>; 752*4882a593Smuzhiyun touch-gpio = <&gpio3 12 IRQ_TYPE_LEVEL_LOW>; 753*4882a593Smuzhiyun reset-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>; 754*4882a593Smuzhiyun max-x = <1536>; 755*4882a593Smuzhiyun max-y = <2048>; 756*4882a593Smuzhiyun tp-size = <970>; 757*4882a593Smuzhiyun tp-supply = <&vcc3v0_tp>; 758*4882a593Smuzhiyun }; 759*4882a593Smuzhiyun}; 760*4882a593Smuzhiyun 761*4882a593Smuzhiyun&io_domains { 762*4882a593Smuzhiyun status = "okay"; 763*4882a593Smuzhiyun 764*4882a593Smuzhiyun bt656-supply = <&vcc1v8_dvp>; 765*4882a593Smuzhiyun audio-supply = <&vcca1v8_codec>; 766*4882a593Smuzhiyun sdmmc-supply = <&vcc_sd>; 767*4882a593Smuzhiyun gpio1830-supply = <&vcc_3v0>; 768*4882a593Smuzhiyun}; 769*4882a593Smuzhiyun 770*4882a593Smuzhiyun&isp0_mmu { 771*4882a593Smuzhiyun status = "okay"; 772*4882a593Smuzhiyun}; 773*4882a593Smuzhiyun 774*4882a593Smuzhiyun&isp1_mmu { 775*4882a593Smuzhiyun status = "okay"; 776*4882a593Smuzhiyun}; 777*4882a593Smuzhiyun 778*4882a593Smuzhiyun&cpu_l0 { 779*4882a593Smuzhiyun cpu-supply = <&vdd_cpu_l>; 780*4882a593Smuzhiyun}; 781*4882a593Smuzhiyun 782*4882a593Smuzhiyun&cpu_l1 { 783*4882a593Smuzhiyun cpu-supply = <&vdd_cpu_l>; 784*4882a593Smuzhiyun}; 785*4882a593Smuzhiyun 786*4882a593Smuzhiyun&cpu_l2 { 787*4882a593Smuzhiyun cpu-supply = <&vdd_cpu_l>; 788*4882a593Smuzhiyun}; 789*4882a593Smuzhiyun 790*4882a593Smuzhiyun&cpu_l3 { 791*4882a593Smuzhiyun cpu-supply = <&vdd_cpu_l>; 792*4882a593Smuzhiyun}; 793*4882a593Smuzhiyun 794*4882a593Smuzhiyun&cpu_b0 { 795*4882a593Smuzhiyun cpu-supply = <&vdd_cpu_b>; 796*4882a593Smuzhiyun}; 797*4882a593Smuzhiyun 798*4882a593Smuzhiyun&cpu_b1 { 799*4882a593Smuzhiyun cpu-supply = <&vdd_cpu_b>; 800*4882a593Smuzhiyun}; 801*4882a593Smuzhiyun 802*4882a593Smuzhiyun&gpu { 803*4882a593Smuzhiyun status = "okay"; 804*4882a593Smuzhiyun mali-supply = <&vdd_gpu>; 805*4882a593Smuzhiyun}; 806*4882a593Smuzhiyun 807*4882a593Smuzhiyun&spi1 { 808*4882a593Smuzhiyun status = "disabled"; 809*4882a593Smuzhiyun max-freq = <50000000>; 810*4882a593Smuzhiyun mpu6500@0 { 811*4882a593Smuzhiyun status = "disabled"; 812*4882a593Smuzhiyun compatible = "inv-spi,mpu6500"; 813*4882a593Smuzhiyun pinctrl-names = "default"; 814*4882a593Smuzhiyun pinctrl-0 = <&mpu6500_irq_gpio>; 815*4882a593Smuzhiyun irq-gpio = <&gpio2 27 IRQ_TYPE_EDGE_RISING>; 816*4882a593Smuzhiyun reg = <0>; 817*4882a593Smuzhiyun spi-max-frequency = <1000000>; 818*4882a593Smuzhiyun spi-cpha; 819*4882a593Smuzhiyun spi-cpol; 820*4882a593Smuzhiyun mpu-int_config = <0x00>; 821*4882a593Smuzhiyun mpu-level_shifter = <0>; 822*4882a593Smuzhiyun mpu-orientation = <1 0 0 0 1 0 0 0 1>; 823*4882a593Smuzhiyun orientation-x= <1>; 824*4882a593Smuzhiyun orientation-y= <0>; 825*4882a593Smuzhiyun orientation-z= <1>; 826*4882a593Smuzhiyun support-hw-poweroff = <1>; 827*4882a593Smuzhiyun mpu-debug = <1>; 828*4882a593Smuzhiyun }; 829*4882a593Smuzhiyun}; 830*4882a593Smuzhiyun 831*4882a593Smuzhiyun&tcphy0 { 832*4882a593Smuzhiyun extcon = <&fusb0>; 833*4882a593Smuzhiyun status = "okay"; 834*4882a593Smuzhiyun}; 835*4882a593Smuzhiyun 836*4882a593Smuzhiyun&tsadc { 837*4882a593Smuzhiyun rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ 838*4882a593Smuzhiyun rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ 839*4882a593Smuzhiyun status = "okay"; 840*4882a593Smuzhiyun}; 841*4882a593Smuzhiyun 842*4882a593Smuzhiyun&u2phy0 { 843*4882a593Smuzhiyun status = "okay"; 844*4882a593Smuzhiyun extcon = <&fusb0>; 845*4882a593Smuzhiyun 846*4882a593Smuzhiyun u2phy0_otg: otg-port { 847*4882a593Smuzhiyun status = "okay"; 848*4882a593Smuzhiyun }; 849*4882a593Smuzhiyun 850*4882a593Smuzhiyun u2phy0_host: host-port { 851*4882a593Smuzhiyun phy-supply = <&vcc5v0_host>; 852*4882a593Smuzhiyun status = "okay"; 853*4882a593Smuzhiyun }; 854*4882a593Smuzhiyun}; 855*4882a593Smuzhiyun 856*4882a593Smuzhiyun&uart0 { 857*4882a593Smuzhiyun pinctrl-names = "default"; 858*4882a593Smuzhiyun pinctrl-0 = <&uart0_xfer &uart0_cts>; 859*4882a593Smuzhiyun status = "okay"; 860*4882a593Smuzhiyun}; 861*4882a593Smuzhiyun 862*4882a593Smuzhiyun&uart2 { 863*4882a593Smuzhiyun status = "okay"; 864*4882a593Smuzhiyun}; 865*4882a593Smuzhiyun 866*4882a593Smuzhiyun&usb_host0_ehci { 867*4882a593Smuzhiyun status = "okay"; 868*4882a593Smuzhiyun}; 869*4882a593Smuzhiyun 870*4882a593Smuzhiyun&usb_host0_ohci { 871*4882a593Smuzhiyun status = "okay"; 872*4882a593Smuzhiyun}; 873*4882a593Smuzhiyun 874*4882a593Smuzhiyun&usbdrd3_0 { 875*4882a593Smuzhiyun status = "okay"; 876*4882a593Smuzhiyun}; 877*4882a593Smuzhiyun 878*4882a593Smuzhiyun&usbdrd_dwc3_0 { 879*4882a593Smuzhiyun status = "okay"; 880*4882a593Smuzhiyun extcon = <&fusb0>; 881*4882a593Smuzhiyun}; 882*4882a593Smuzhiyun 883*4882a593Smuzhiyun&pwm0 { 884*4882a593Smuzhiyun status = "okay"; 885*4882a593Smuzhiyun}; 886*4882a593Smuzhiyun 887*4882a593Smuzhiyun&pwm2 { 888*4882a593Smuzhiyun status = "okay"; 889*4882a593Smuzhiyun pinctrl-names = "active"; 890*4882a593Smuzhiyun pinctrl-0 = <&pwm2_pin_pull_down>; 891*4882a593Smuzhiyun}; 892*4882a593Smuzhiyun 893*4882a593Smuzhiyun&saradc { 894*4882a593Smuzhiyun status = "okay"; 895*4882a593Smuzhiyun}; 896*4882a593Smuzhiyun 897*4882a593Smuzhiyun&rockchip_suspend { 898*4882a593Smuzhiyun status = "okay"; 899*4882a593Smuzhiyun rockchip,sleep-debug-en = <1>; 900*4882a593Smuzhiyun rockchip,sleep-mode-config = < 901*4882a593Smuzhiyun (0 902*4882a593Smuzhiyun | RKPM_SLP_ARMPD 903*4882a593Smuzhiyun | RKPM_SLP_PERILPPD 904*4882a593Smuzhiyun | RKPM_SLP_DDR_RET 905*4882a593Smuzhiyun | RKPM_SLP_PLLPD 906*4882a593Smuzhiyun | RKPM_SLP_CENTER_PD 907*4882a593Smuzhiyun | RKPM_SLP_OSC_DIS 908*4882a593Smuzhiyun | RKPM_SLP_AP_PWROFF 909*4882a593Smuzhiyun ) 910*4882a593Smuzhiyun >; 911*4882a593Smuzhiyun rockchip,wakeup-config = < 912*4882a593Smuzhiyun (0 913*4882a593Smuzhiyun | RKPM_GPIO_WKUP_EN 914*4882a593Smuzhiyun ) 915*4882a593Smuzhiyun >; 916*4882a593Smuzhiyun rockchip,pwm-regulator-config = < 917*4882a593Smuzhiyun (0 918*4882a593Smuzhiyun | PWM2_REGULATOR_EN 919*4882a593Smuzhiyun ) 920*4882a593Smuzhiyun >; 921*4882a593Smuzhiyun rockchip,power-ctrl = 922*4882a593Smuzhiyun <&gpio1 17 GPIO_ACTIVE_HIGH>, 923*4882a593Smuzhiyun <&gpio1 14 GPIO_ACTIVE_HIGH>; 924*4882a593Smuzhiyun}; 925*4882a593Smuzhiyun 926*4882a593Smuzhiyun&pinctrl { 927*4882a593Smuzhiyun sdio-pwrseq { 928*4882a593Smuzhiyun wifi_enable_h: wifi-enable-h { 929*4882a593Smuzhiyun rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 930*4882a593Smuzhiyun }; 931*4882a593Smuzhiyun }; 932*4882a593Smuzhiyun 933*4882a593Smuzhiyun wireless-bluetooth { 934*4882a593Smuzhiyun uart0_gpios: uart0-gpios { 935*4882a593Smuzhiyun rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 936*4882a593Smuzhiyun }; 937*4882a593Smuzhiyun 938*4882a593Smuzhiyun bt_reset_gpio: bt-reset-gpio { 939*4882a593Smuzhiyun rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; 940*4882a593Smuzhiyun }; 941*4882a593Smuzhiyun 942*4882a593Smuzhiyun bt_wake_gpio: bt-wake-gpio { 943*4882a593Smuzhiyun rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 944*4882a593Smuzhiyun }; 945*4882a593Smuzhiyun 946*4882a593Smuzhiyun bt_irq_gpio: bt-irq-gpio { 947*4882a593Smuzhiyun rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; 948*4882a593Smuzhiyun }; 949*4882a593Smuzhiyun }; 950*4882a593Smuzhiyun 951*4882a593Smuzhiyun pmic { 952*4882a593Smuzhiyun pmic_int_l: pmic-int-l { 953*4882a593Smuzhiyun rockchip,pins = 954*4882a593Smuzhiyun <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; 955*4882a593Smuzhiyun }; 956*4882a593Smuzhiyun 957*4882a593Smuzhiyun pmic_dvs2: pmic-dvs2 { 958*4882a593Smuzhiyun rockchip,pins = 959*4882a593Smuzhiyun <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; 960*4882a593Smuzhiyun }; 961*4882a593Smuzhiyun vsel1_gpio: vsel1-gpio { 962*4882a593Smuzhiyun rockchip,pins = 963*4882a593Smuzhiyun <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; 964*4882a593Smuzhiyun }; 965*4882a593Smuzhiyun vsel2_gpio: vsel2-gpio { 966*4882a593Smuzhiyun rockchip,pins = 967*4882a593Smuzhiyun <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; 968*4882a593Smuzhiyun }; 969*4882a593Smuzhiyun }; 970*4882a593Smuzhiyun 971*4882a593Smuzhiyun hallsensor { 972*4882a593Smuzhiyun mh248_irq_gpio: mh248-irq-gpio { 973*4882a593Smuzhiyun rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; 974*4882a593Smuzhiyun }; 975*4882a593Smuzhiyun }; 976*4882a593Smuzhiyun 977*4882a593Smuzhiyun headphone { 978*4882a593Smuzhiyun hp_det: hp-det { 979*4882a593Smuzhiyun rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; 980*4882a593Smuzhiyun }; 981*4882a593Smuzhiyun }; 982*4882a593Smuzhiyun 983*4882a593Smuzhiyun lsm330_a { 984*4882a593Smuzhiyun lsm330a_irq_gpio: lsm330a-irq-gpio { 985*4882a593Smuzhiyun rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; 986*4882a593Smuzhiyun }; 987*4882a593Smuzhiyun }; 988*4882a593Smuzhiyun 989*4882a593Smuzhiyun lsm330_g { 990*4882a593Smuzhiyun lsm330g_irq_gpio: lsm330g-irq-gpio { 991*4882a593Smuzhiyun rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; 992*4882a593Smuzhiyun }; 993*4882a593Smuzhiyun }; 994*4882a593Smuzhiyun 995*4882a593Smuzhiyun mpu6500 { 996*4882a593Smuzhiyun mpu6500_irq_gpio: mpu6500-irq-gpio { 997*4882a593Smuzhiyun rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; 998*4882a593Smuzhiyun }; 999*4882a593Smuzhiyun }; 1000*4882a593Smuzhiyun 1001*4882a593Smuzhiyun ak8963 { 1002*4882a593Smuzhiyun ak8963_irq_gpio: ak8963-irq-gpio { 1003*4882a593Smuzhiyun rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; 1004*4882a593Smuzhiyun }; 1005*4882a593Smuzhiyun }; 1006*4882a593Smuzhiyun 1007*4882a593Smuzhiyun cm3218 { 1008*4882a593Smuzhiyun cm3218_irq_gpio: cm3218-irq-gpio { 1009*4882a593Smuzhiyun rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; 1010*4882a593Smuzhiyun }; 1011*4882a593Smuzhiyun }; 1012*4882a593Smuzhiyun 1013*4882a593Smuzhiyun usb2 { 1014*4882a593Smuzhiyun host_vbus_drv: host-vbus-drv { 1015*4882a593Smuzhiyun rockchip,pins = 1016*4882a593Smuzhiyun <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; 1017*4882a593Smuzhiyun }; 1018*4882a593Smuzhiyun }; 1019*4882a593Smuzhiyun 1020*4882a593Smuzhiyun fusb30x { 1021*4882a593Smuzhiyun fusb0_int: fusb0-int { 1022*4882a593Smuzhiyun rockchip,pins = 1023*4882a593Smuzhiyun <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; 1024*4882a593Smuzhiyun }; 1025*4882a593Smuzhiyun }; 1026*4882a593Smuzhiyun}; 1027*4882a593Smuzhiyun 1028*4882a593Smuzhiyun&edp { 1029*4882a593Smuzhiyun status = "okay"; 1030*4882a593Smuzhiyun pinctrl-names = "default"; 1031*4882a593Smuzhiyun pinctrl-0 = <&edp_hpd>; 1032*4882a593Smuzhiyun 1033*4882a593Smuzhiyun ports { 1034*4882a593Smuzhiyun edp_out: port@1 { 1035*4882a593Smuzhiyun reg = <1>; 1036*4882a593Smuzhiyun #address-cells = <1>; 1037*4882a593Smuzhiyun #size-cells = <0>; 1038*4882a593Smuzhiyun edp_out_panel: endpoint@0 { 1039*4882a593Smuzhiyun reg = <0>; 1040*4882a593Smuzhiyun remote-endpoint = <&panel_in_edp>; 1041*4882a593Smuzhiyun }; 1042*4882a593Smuzhiyun }; 1043*4882a593Smuzhiyun }; 1044*4882a593Smuzhiyun}; 1045*4882a593Smuzhiyun 1046*4882a593Smuzhiyun&edp_in_vopl { 1047*4882a593Smuzhiyun status = "disabled"; 1048*4882a593Smuzhiyun}; 1049*4882a593Smuzhiyun 1050*4882a593Smuzhiyun&hdmi { 1051*4882a593Smuzhiyun status = "disabled"; 1052*4882a593Smuzhiyun}; 1053*4882a593Smuzhiyun 1054*4882a593Smuzhiyun&hdmi_in_vopb { 1055*4882a593Smuzhiyun status = "disabled"; 1056*4882a593Smuzhiyun}; 1057*4882a593Smuzhiyun 1058*4882a593Smuzhiyun&cdn_dp { 1059*4882a593Smuzhiyun status = "okay"; 1060*4882a593Smuzhiyun extcon = <&fusb0>; 1061*4882a593Smuzhiyun phys = <&tcphy0_dp>; 1062*4882a593Smuzhiyun}; 1063*4882a593Smuzhiyun 1064*4882a593Smuzhiyun&dp_in_vopb { 1065*4882a593Smuzhiyun status = "disabled"; 1066*4882a593Smuzhiyun}; 1067*4882a593Smuzhiyun 1068*4882a593Smuzhiyun&pmu_io_domains { 1069*4882a593Smuzhiyun status = "okay"; 1070*4882a593Smuzhiyun pmu1830-supply = <&vcc_1v8>; 1071*4882a593Smuzhiyun}; 1072*4882a593Smuzhiyun 1073*4882a593Smuzhiyun&route_edp { 1074*4882a593Smuzhiyun status = "okay"; 1075*4882a593Smuzhiyun logo,mode = "center"; 1076*4882a593Smuzhiyun}; 1077*4882a593Smuzhiyun 1078*4882a593Smuzhiyun&vopb { 1079*4882a593Smuzhiyun assigned-clocks = <&cru DCLK_VOP0_DIV>; 1080*4882a593Smuzhiyun assigned-clock-parents = <&cru PLL_CPLL>; 1081*4882a593Smuzhiyun}; 1082*4882a593Smuzhiyun 1083*4882a593Smuzhiyun&vopl { 1084*4882a593Smuzhiyun assigned-clocks = <&cru DCLK_VOP1_DIV>; 1085*4882a593Smuzhiyun assigned-clock-parents = <&cru PLL_VPLL>; 1086*4882a593Smuzhiyun}; 1087