xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm64/rockchip/rk3399-firefly-android.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun/dts-v1/;
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun#include "dt-bindings/pwm/pwm.h"
10*4882a593Smuzhiyun#include "rk3399.dtsi"
11*4882a593Smuzhiyun#include "rk3399-opp.dtsi"
12*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h>
13*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
14*4882a593Smuzhiyun#include "rk3399-vop-clk-set.dtsi"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun/ {
17*4882a593Smuzhiyun	model = "Rockchip RK3399 Firefly Board (Android)";
18*4882a593Smuzhiyun	compatible = "rockchip,rk3399-firefly-android", "rockchip,rk3399";
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun	chosen: chosen {
21*4882a593Smuzhiyun		bootargs = "earlycon=uart8250,mmio32,0xff1a0000 coherent_pool=1m";
22*4882a593Smuzhiyun	};
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun	cpuinfo {
25*4882a593Smuzhiyun		compatible = "rockchip,cpuinfo";
26*4882a593Smuzhiyun		nvmem-cells = <&cpu_id>;
27*4882a593Smuzhiyun		nvmem-cell-names = "id";
28*4882a593Smuzhiyun	};
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun	backlight: backlight {
31*4882a593Smuzhiyun		compatible = "pwm-backlight";
32*4882a593Smuzhiyun		pwms = <&pwm0 0 25000 0>;
33*4882a593Smuzhiyun		brightness-levels = <
34*4882a593Smuzhiyun			  0   1   2   3   4   5   6   7
35*4882a593Smuzhiyun			  8   9  10  11  12  13  14  15
36*4882a593Smuzhiyun			 16  17  18  19  20  21  22  23
37*4882a593Smuzhiyun			 24  25  26  27  28  29  30  31
38*4882a593Smuzhiyun			 32  33  34  35  36  37  38  39
39*4882a593Smuzhiyun			 40  41  42  43  44  45  46  47
40*4882a593Smuzhiyun			 48  49  50  51  52  53  54  55
41*4882a593Smuzhiyun			 56  57  58  59  60  61  62  63
42*4882a593Smuzhiyun			 64  65  66  67  68  69  70  71
43*4882a593Smuzhiyun			 72  73  74  75  76  77  78  79
44*4882a593Smuzhiyun			 80  81  82  83  84  85  86  87
45*4882a593Smuzhiyun			 88  89  90  91  92  93  94  95
46*4882a593Smuzhiyun			 96  97  98  99 100 101 102 103
47*4882a593Smuzhiyun			104 105 106 107 108 109 110 111
48*4882a593Smuzhiyun			112 113 114 115 116 117 118 119
49*4882a593Smuzhiyun			120 121 122 123 124 125 126 127
50*4882a593Smuzhiyun			128 129 130 131 132 133 134 135
51*4882a593Smuzhiyun			136 137 138 139 140 141 142 143
52*4882a593Smuzhiyun			144 145 146 147 148 149 150 151
53*4882a593Smuzhiyun			152 153 154 155 156 157 158 159
54*4882a593Smuzhiyun			160 161 162 163 164 165 166 167
55*4882a593Smuzhiyun			168 169 170 171 172 173 174 175
56*4882a593Smuzhiyun			176 177 178 179 180 181 182 183
57*4882a593Smuzhiyun			184 185 186 187 188 189 190 191
58*4882a593Smuzhiyun			192 193 194 195 196 197 198 199
59*4882a593Smuzhiyun			200 201 202 203 204 205 206 207
60*4882a593Smuzhiyun			208 209 210 211 212 213 214 215
61*4882a593Smuzhiyun			216 217 218 219 220 221 222 223
62*4882a593Smuzhiyun			224 225 226 227 228 229 230 231
63*4882a593Smuzhiyun			232 233 234 235 236 237 238 239
64*4882a593Smuzhiyun			240 241 242 243 244 245 246 247
65*4882a593Smuzhiyun			248 249 250 251 252 253 254 255>;
66*4882a593Smuzhiyun		default-brightness-level = <200>;
67*4882a593Smuzhiyun	};
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun	clkin_gmac: external-gmac-clock {
70*4882a593Smuzhiyun		compatible = "fixed-clock";
71*4882a593Smuzhiyun		clock-frequency = <125000000>;
72*4882a593Smuzhiyun		clock-output-names = "clkin_gmac";
73*4882a593Smuzhiyun		#clock-cells = <0>;
74*4882a593Smuzhiyun	};
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun	dw_hdmi_audio: dw-hdmi-audio {
77*4882a593Smuzhiyun		status = "okay";
78*4882a593Smuzhiyun		compatible = "rockchip,dw-hdmi-audio";
79*4882a593Smuzhiyun		#sound-dai-cells = <0>;
80*4882a593Smuzhiyun	};
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun	edp_panel: edp-panel {
83*4882a593Smuzhiyun		compatible = "sharp,lcd-f402", "panel-simple";
84*4882a593Smuzhiyun		status = "okay";
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun		backlight = <&backlight>;
87*4882a593Smuzhiyun		power-supply = <&vcc_lcd>;
88*4882a593Smuzhiyun		enable-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
89*4882a593Smuzhiyun		pinctrl-names = "default";
90*4882a593Smuzhiyun		pinctrl-0 = <&lcd_panel_reset>;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun		ports {
93*4882a593Smuzhiyun			panel_in_edp: endpoint {
94*4882a593Smuzhiyun				remote-endpoint = <&edp_out_panel>;
95*4882a593Smuzhiyun			};
96*4882a593Smuzhiyun		};
97*4882a593Smuzhiyun	};
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun	fiq_debugger: fiq-debugger {
100*4882a593Smuzhiyun		compatible = "rockchip,fiq-debugger";
101*4882a593Smuzhiyun		rockchip,serial-id = <2>;
102*4882a593Smuzhiyun		rockchip,wake-irq = <0>;
103*4882a593Smuzhiyun		/* If enable uart uses irq instead of fiq */
104*4882a593Smuzhiyun		rockchip,irq-mode-enable = <0>;
105*4882a593Smuzhiyun		/* Only 115200 and 1500000 */
106*4882a593Smuzhiyun		rockchip,baudrate = <1500000>;
107*4882a593Smuzhiyun		pinctrl-names = "default";
108*4882a593Smuzhiyun		pinctrl-0 = <&uart2c_xfer>;
109*4882a593Smuzhiyun		interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
110*4882a593Smuzhiyun	};
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun	reserved-memory {
113*4882a593Smuzhiyun		#address-cells = <2>;
114*4882a593Smuzhiyun		#size-cells = <2>;
115*4882a593Smuzhiyun		ranges;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun		drm_logo: drm-logo@00000000 {
118*4882a593Smuzhiyun			compatible = "rockchip,drm-logo";
119*4882a593Smuzhiyun			reg = <0x0 0x0 0x0 0x0>;
120*4882a593Smuzhiyun		};
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun		stb_devinfo: stb-devinfo@00000000 {
123*4882a593Smuzhiyun			compatible = "rockchip,stb-devinfo";
124*4882a593Smuzhiyun			reg = <0x0 0x0 0x0 0x0>;
125*4882a593Smuzhiyun		};
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun		ramoops: ramoops@110000 {
128*4882a593Smuzhiyun			compatible = "ramoops";
129*4882a593Smuzhiyun			reg = <0x0 0x110000 0x0 0xf0000>;
130*4882a593Smuzhiyun			record-size = <0x20000>;
131*4882a593Smuzhiyun			console-size = <0x80000>;
132*4882a593Smuzhiyun			ftrace-size = <0x00000>;
133*4882a593Smuzhiyun			pmsg-size = <0x50000>;
134*4882a593Smuzhiyun		};
135*4882a593Smuzhiyun	};
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun	rockchip-key {
138*4882a593Smuzhiyun		compatible = "rockchip,key";
139*4882a593Smuzhiyun		status = "okay";
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun		io-channels = <&saradc 1>;
142*4882a593Smuzhiyun		power-key {
143*4882a593Smuzhiyun			gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
144*4882a593Smuzhiyun			linux,code = <116>;
145*4882a593Smuzhiyun			label = "power";
146*4882a593Smuzhiyun			gpio-key,wakeup;
147*4882a593Smuzhiyun		};
148*4882a593Smuzhiyun	};
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun	rt5640-sound {
151*4882a593Smuzhiyun		compatible = "simple-audio-card";
152*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
153*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,rt5640-codec";
154*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <256>;
155*4882a593Smuzhiyun		simple-audio-card,widgets =
156*4882a593Smuzhiyun			"Microphone", "Mic Jack",
157*4882a593Smuzhiyun			"Headphone", "Headphone Jack";
158*4882a593Smuzhiyun		simple-audio-card,routing =
159*4882a593Smuzhiyun			"Mic Jack", "MICBIAS1",
160*4882a593Smuzhiyun			"IN1P", "Mic Jack",
161*4882a593Smuzhiyun			"Headphone Jack", "HPOL",
162*4882a593Smuzhiyun			"Headphone Jack", "HPOR";
163*4882a593Smuzhiyun		simple-audio-card,cpu {
164*4882a593Smuzhiyun			sound-dai = <&i2s1>;
165*4882a593Smuzhiyun		};
166*4882a593Smuzhiyun		simple-audio-card,codec {
167*4882a593Smuzhiyun			sound-dai = <&rt5640>;
168*4882a593Smuzhiyun		};
169*4882a593Smuzhiyun	};
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun	hdmi_sound: hdmi-sound {
172*4882a593Smuzhiyun		status = "disabled";
173*4882a593Smuzhiyun		compatible = "simple-audio-card";
174*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
175*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <256>;
176*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,hdmi";
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun		simple-audio-card,cpu {
179*4882a593Smuzhiyun			sound-dai = <&i2s2>;
180*4882a593Smuzhiyun		};
181*4882a593Smuzhiyun		simple-audio-card,codec {
182*4882a593Smuzhiyun			sound-dai = <&dw_hdmi_audio>;
183*4882a593Smuzhiyun		};
184*4882a593Smuzhiyun	};
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun	hdmi_codec: hdmi-codec {
187*4882a593Smuzhiyun		compatible = "simple-audio-card";
188*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
189*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <256>;
190*4882a593Smuzhiyun		simple-audio-card,name = "HDMI-CODEC";
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun		simple-audio-card,cpu {
193*4882a593Smuzhiyun			sound-dai = <&i2s2>;
194*4882a593Smuzhiyun		};
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun		simple-audio-card,codec {
197*4882a593Smuzhiyun			sound-dai = <&hdmi>;
198*4882a593Smuzhiyun		};
199*4882a593Smuzhiyun	};
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun	rga: rga@ff680000 {
202*4882a593Smuzhiyun		compatible = "rockchip,rga2";
203*4882a593Smuzhiyun		dev_mode = <1>;
204*4882a593Smuzhiyun		reg = <0x0 0xff680000 0x0 0x1000>;
205*4882a593Smuzhiyun		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
206*4882a593Smuzhiyun		clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
207*4882a593Smuzhiyun		clock-names = "aclk_rga", "hclk_rga", "clk_rga";
208*4882a593Smuzhiyun		power-domains = <&power RK3399_PD_RGA>;
209*4882a593Smuzhiyun		dma-coherent;
210*4882a593Smuzhiyun		status = "okay";
211*4882a593Smuzhiyun	};
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun	spdif-sound {
214*4882a593Smuzhiyun		compatible = "simple-audio-card";
215*4882a593Smuzhiyun		status = "okay";
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun		simple-audio-card,name = "ROCKCHIP,SPDIF";
218*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <128>;
219*4882a593Smuzhiyun		simple-audio-card,cpu {
220*4882a593Smuzhiyun			sound-dai = <&spdif>;
221*4882a593Smuzhiyun		};
222*4882a593Smuzhiyun		simple-audio-card,codec {
223*4882a593Smuzhiyun			sound-dai = <&spdif_out>;
224*4882a593Smuzhiyun		};
225*4882a593Smuzhiyun	};
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun	spdif_out: spdif-out {
228*4882a593Smuzhiyun		compatible = "linux,spdif-dit";
229*4882a593Smuzhiyun		status = "okay";
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun		#sound-dai-cells = <0>;
232*4882a593Smuzhiyun	};
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun	sdio_pwrseq: sdio-pwrseq {
235*4882a593Smuzhiyun		compatible = "mmc-pwrseq-simple";
236*4882a593Smuzhiyun		clocks = <&rk808 1>;
237*4882a593Smuzhiyun		clock-names = "ext_clock";
238*4882a593Smuzhiyun		pinctrl-names = "default";
239*4882a593Smuzhiyun		pinctrl-0 = <&wifi_enable_h>;
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun		/*
242*4882a593Smuzhiyun		 * On the module itself this is one of these (depending
243*4882a593Smuzhiyun		 * on the actual card populated):
244*4882a593Smuzhiyun		 * - SDIO_RESET_L_WL_REG_ON
245*4882a593Smuzhiyun		 * - PDN (power down when low)
246*4882a593Smuzhiyun		 */
247*4882a593Smuzhiyun		reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */
248*4882a593Smuzhiyun	};
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun	vcc3v3_pcie: vcc3v3-pcie-regulator {
251*4882a593Smuzhiyun		compatible = "regulator-fixed";
252*4882a593Smuzhiyun		enable-active-high;
253*4882a593Smuzhiyun		regulator-always-on;
254*4882a593Smuzhiyun		regulator-boot-on;
255*4882a593Smuzhiyun		gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
256*4882a593Smuzhiyun		pinctrl-names = "default";
257*4882a593Smuzhiyun		pinctrl-0 = <&pcie_drv>;
258*4882a593Smuzhiyun		regulator-name = "vcc3v3_pcie";
259*4882a593Smuzhiyun	};
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun	vcc3v3_sys: vcc3v3-sys {
262*4882a593Smuzhiyun		compatible = "regulator-fixed";
263*4882a593Smuzhiyun		regulator-name = "vcc3v3_sys";
264*4882a593Smuzhiyun		regulator-always-on;
265*4882a593Smuzhiyun		regulator-boot-on;
266*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
267*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
268*4882a593Smuzhiyun	};
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun	vcc5v0_host: vcc5v0-host-regulator {
271*4882a593Smuzhiyun		compatible = "regulator-fixed";
272*4882a593Smuzhiyun		enable-active-high;
273*4882a593Smuzhiyun		gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
274*4882a593Smuzhiyun		pinctrl-names = "default";
275*4882a593Smuzhiyun		pinctrl-0 = <&host_vbus_drv>;
276*4882a593Smuzhiyun		regulator-name = "vcc5v0_host";
277*4882a593Smuzhiyun		regulator-always-on;
278*4882a593Smuzhiyun	};
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun	vcc5v0_sys: vcc5v0-sys {
281*4882a593Smuzhiyun		compatible = "regulator-fixed";
282*4882a593Smuzhiyun		regulator-name = "vcc5v0_sys";
283*4882a593Smuzhiyun		regulator-always-on;
284*4882a593Smuzhiyun		regulator-boot-on;
285*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
286*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
287*4882a593Smuzhiyun	};
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun	vcc_phy: vcc-phy-regulator {
290*4882a593Smuzhiyun		compatible = "regulator-fixed";
291*4882a593Smuzhiyun		regulator-name = "vcc_phy";
292*4882a593Smuzhiyun		regulator-always-on;
293*4882a593Smuzhiyun		regulator-boot-on;
294*4882a593Smuzhiyun	};
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun	vdd_log: vdd-log {
297*4882a593Smuzhiyun		compatible = "pwm-regulator";
298*4882a593Smuzhiyun		pwms = <&pwm2 0 25000 1>;
299*4882a593Smuzhiyun		regulator-name = "vdd_log";
300*4882a593Smuzhiyun		regulator-min-microvolt = <800000>;
301*4882a593Smuzhiyun		/*
302*4882a593Smuzhiyun		 * the firefly hardware using 3.0 v as APIO2_VDD
303*4882a593Smuzhiyun		 * voltage, but the pwm divider resistance is designed
304*4882a593Smuzhiyun		 * based on hardware which the APIO2_VDD is 1.8v, so we
305*4882a593Smuzhiyun		 * need to change the regulator-max-microvolt from 1.4v
306*4882a593Smuzhiyun		 * to 1.0v, so the pwm can output 0.9v voltage.
307*4882a593Smuzhiyun		 */
308*4882a593Smuzhiyun		regulator-max-microvolt = <1000000>;
309*4882a593Smuzhiyun		regulator-always-on;
310*4882a593Smuzhiyun		regulator-boot-on;
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun		/* for rockchip boot on */
313*4882a593Smuzhiyun		rockchip,pwm_id= <2>;
314*4882a593Smuzhiyun		rockchip,pwm_voltage = <900000>;
315*4882a593Smuzhiyun	};
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun	vccadc_ref: vccadc-ref {
318*4882a593Smuzhiyun		compatible = "regulator-fixed";
319*4882a593Smuzhiyun		regulator-name = "vcc1v8_sys";
320*4882a593Smuzhiyun		regulator-always-on;
321*4882a593Smuzhiyun		regulator-boot-on;
322*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
323*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
324*4882a593Smuzhiyun	};
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun	vcc_lcd: vcc-lcd-regulator {
327*4882a593Smuzhiyun		compatible = "regulator-fixed";
328*4882a593Smuzhiyun		regulator-always-on;
329*4882a593Smuzhiyun		regulator-boot-on;
330*4882a593Smuzhiyun		enable-active-high;
331*4882a593Smuzhiyun		gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
332*4882a593Smuzhiyun		pinctrl-names = "default";
333*4882a593Smuzhiyun		pinctrl-0 = <&lcd_en>;
334*4882a593Smuzhiyun		regulator-name = "vcc_lcd";
335*4882a593Smuzhiyun	};
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun	xin32k: xin32k {
338*4882a593Smuzhiyun		compatible = "fixed-clock";
339*4882a593Smuzhiyun		clock-frequency = <32768>;
340*4882a593Smuzhiyun		clock-output-names = "xin32k";
341*4882a593Smuzhiyun		#clock-cells = <0>;
342*4882a593Smuzhiyun	};
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun	wireless-wlan {
345*4882a593Smuzhiyun		compatible = "wlan-platdata";
346*4882a593Smuzhiyun		rockchip,grf = <&grf>;
347*4882a593Smuzhiyun		wifi_chip_type = "ap6354";
348*4882a593Smuzhiyun		sdio_vref = <1800>;
349*4882a593Smuzhiyun		WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; /* GPIO0_a3 */
350*4882a593Smuzhiyun		status = "okay";
351*4882a593Smuzhiyun	};
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun	wireless-bluetooth {
354*4882a593Smuzhiyun		compatible = "bluetooth-platdata";
355*4882a593Smuzhiyun		//wifi-bt-power-toggle;
356*4882a593Smuzhiyun		uart_rts_gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; /* GPIO2_C3 */
357*4882a593Smuzhiyun		pinctrl-names = "default", "rts_gpio";
358*4882a593Smuzhiyun		pinctrl-0 = <&uart0_rts>;
359*4882a593Smuzhiyun		pinctrl-1 = <&uart0_gpios>;
360*4882a593Smuzhiyun		//BT,power_gpio  = <&gpio3 19 GPIO_ACTIVE_HIGH>; /* GPIOx_xx */
361*4882a593Smuzhiyun		BT,reset_gpio    = <&gpio0 9 GPIO_ACTIVE_HIGH>; /* GPIO0_B1 */
362*4882a593Smuzhiyun		BT,wake_gpio     = <&gpio2 26 GPIO_ACTIVE_HIGH>; /* GPIO2_D2 */
363*4882a593Smuzhiyun		BT,wake_host_irq = <&gpio0 4 GPIO_ACTIVE_HIGH>; /* GPIO0_A4 */
364*4882a593Smuzhiyun		status = "okay";
365*4882a593Smuzhiyun	};
366*4882a593Smuzhiyun};
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun&cpu_l0 {
369*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_l>;
370*4882a593Smuzhiyun};
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun&cpu_l1 {
373*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_l>;
374*4882a593Smuzhiyun};
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun&cpu_l2 {
377*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_l>;
378*4882a593Smuzhiyun};
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun&cpu_l3 {
381*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_l>;
382*4882a593Smuzhiyun};
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun&cpu_b0 {
385*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_b>;
386*4882a593Smuzhiyun};
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun&cpu_b1 {
389*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu_b>;
390*4882a593Smuzhiyun};
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun&display_subsystem {
393*4882a593Smuzhiyun	status = "okay";
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun	ports = <&vopb_out>, <&vopl_out>;
396*4882a593Smuzhiyun	logo-memory-region = <&drm_logo>;
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun	route {
399*4882a593Smuzhiyun		route_hdmi: route-hdmi {
400*4882a593Smuzhiyun			status = "okay";
401*4882a593Smuzhiyun			logo,uboot = "logo.bmp";
402*4882a593Smuzhiyun			logo,kernel = "logo_kernel.bmp";
403*4882a593Smuzhiyun			logo,mode = "fullscreen";
404*4882a593Smuzhiyun			charge_logo,mode = "center";
405*4882a593Smuzhiyun			connect = <&vopl_out_hdmi>;
406*4882a593Smuzhiyun		};
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun		route_edp: route-edp {
409*4882a593Smuzhiyun			status = "okay";
410*4882a593Smuzhiyun			logo,uboot = "logo.bmp";
411*4882a593Smuzhiyun			logo,kernel = "logo_kernel.bmp";
412*4882a593Smuzhiyun			logo,mode = "fullscreen";
413*4882a593Smuzhiyun			charge_logo,mode = "center";
414*4882a593Smuzhiyun			connect = <&vopb_out_edp>;
415*4882a593Smuzhiyun		};
416*4882a593Smuzhiyun	};
417*4882a593Smuzhiyun};
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun&edp {
420*4882a593Smuzhiyun	status = "okay";
421*4882a593Smuzhiyun	pinctrl-names = "default";
422*4882a593Smuzhiyun	pinctrl-0 = <&edp_hpd>;
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun	ports {
425*4882a593Smuzhiyun		edp_out: port@1 {
426*4882a593Smuzhiyun			reg = <1>;
427*4882a593Smuzhiyun			#address-cells = <1>;
428*4882a593Smuzhiyun			#size-cells = <0>;
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun			edp_out_panel: endpoint@0 {
431*4882a593Smuzhiyun				reg = <0>;
432*4882a593Smuzhiyun				remote-endpoint = <&panel_in_edp>;
433*4882a593Smuzhiyun			};
434*4882a593Smuzhiyun		};
435*4882a593Smuzhiyun	};
436*4882a593Smuzhiyun};
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun&emmc_phy {
439*4882a593Smuzhiyun	status = "okay";
440*4882a593Smuzhiyun};
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun&gmac {
443*4882a593Smuzhiyun	phy-supply = <&vcc_phy>;
444*4882a593Smuzhiyun	phy-mode = "rgmii";
445*4882a593Smuzhiyun	clock_in_out = "input";
446*4882a593Smuzhiyun	snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>;
447*4882a593Smuzhiyun	snps,reset-active-low;
448*4882a593Smuzhiyun	snps,reset-delays-us = <0 10000 50000>;
449*4882a593Smuzhiyun	assigned-clocks = <&cru SCLK_RMII_SRC>;
450*4882a593Smuzhiyun	assigned-clock-parents = <&clkin_gmac>;
451*4882a593Smuzhiyun	pinctrl-names = "default";
452*4882a593Smuzhiyun	pinctrl-0 = <&rgmii_pins>;
453*4882a593Smuzhiyun	tx_delay = <0x28>;
454*4882a593Smuzhiyun	rx_delay = <0x11>;
455*4882a593Smuzhiyun	status = "okay";
456*4882a593Smuzhiyun};
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun&gpu {
459*4882a593Smuzhiyun	status = "okay";
460*4882a593Smuzhiyun	mali-supply = <&vdd_gpu>;
461*4882a593Smuzhiyun};
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun&hdmi {
464*4882a593Smuzhiyun	#address-cells = <1>;
465*4882a593Smuzhiyun	#size-cells = <0>;
466*4882a593Smuzhiyun	#sound-dai-cells = <0>;
467*4882a593Smuzhiyun	status = "okay";
468*4882a593Smuzhiyun};
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun&i2c0 {
471*4882a593Smuzhiyun	status = "okay";
472*4882a593Smuzhiyun	i2c-scl-rising-time-ns = <168>;
473*4882a593Smuzhiyun	i2c-scl-falling-time-ns = <4>;
474*4882a593Smuzhiyun	clock-frequency = <400000>;
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun	vdd_cpu_b: syr827@40 {
477*4882a593Smuzhiyun		compatible = "silergy,syr827";
478*4882a593Smuzhiyun		reg = <0x40>;
479*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
480*4882a593Smuzhiyun		regulator-compatible = "fan53555-reg";
481*4882a593Smuzhiyun		regulator-name = "vdd_cpu_b";
482*4882a593Smuzhiyun		regulator-min-microvolt = <712500>;
483*4882a593Smuzhiyun		regulator-max-microvolt = <1500000>;
484*4882a593Smuzhiyun		regulator-ramp-delay = <1000>;
485*4882a593Smuzhiyun		vsel-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
486*4882a593Smuzhiyun		fcs,suspend-voltage-selector = <1>;
487*4882a593Smuzhiyun		regulator-always-on;
488*4882a593Smuzhiyun		regulator-boot-on;
489*4882a593Smuzhiyun		regulator-initial-state = <3>;
490*4882a593Smuzhiyun			regulator-state-mem {
491*4882a593Smuzhiyun			regulator-off-in-suspend;
492*4882a593Smuzhiyun		};
493*4882a593Smuzhiyun	};
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun	vdd_gpu: syr828@41 {
496*4882a593Smuzhiyun		compatible = "silergy,syr828";
497*4882a593Smuzhiyun		reg = <0x41>;
498*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
499*4882a593Smuzhiyun		regulator-compatible = "fan53555-reg";
500*4882a593Smuzhiyun		regulator-name = "vdd_gpu";
501*4882a593Smuzhiyun		regulator-min-microvolt = <712500>;
502*4882a593Smuzhiyun		regulator-max-microvolt = <1500000>;
503*4882a593Smuzhiyun		regulator-ramp-delay = <1000>;
504*4882a593Smuzhiyun		fcs,suspend-voltage-selector = <1>;
505*4882a593Smuzhiyun		regulator-always-on;
506*4882a593Smuzhiyun		regulator-boot-on;
507*4882a593Smuzhiyun		regulator-initial-state = <3>;
508*4882a593Smuzhiyun			regulator-state-mem {
509*4882a593Smuzhiyun			regulator-off-in-suspend;
510*4882a593Smuzhiyun		};
511*4882a593Smuzhiyun	};
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun	rk808: pmic@1b {
514*4882a593Smuzhiyun		compatible = "rockchip,rk808";
515*4882a593Smuzhiyun		reg = <0x1b>;
516*4882a593Smuzhiyun		interrupt-parent = <&gpio1>;
517*4882a593Smuzhiyun		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
518*4882a593Smuzhiyun		pinctrl-names = "default";
519*4882a593Smuzhiyun		pinctrl-0 = <&pmic_int_l &pmic_dvs2>;
520*4882a593Smuzhiyun		rockchip,system-power-controller;
521*4882a593Smuzhiyun		wakeup-source;
522*4882a593Smuzhiyun		#clock-cells = <1>;
523*4882a593Smuzhiyun		clock-output-names = "rk808-clkout1", "rk808-clkout2";
524*4882a593Smuzhiyun
525*4882a593Smuzhiyun		vcc1-supply = <&vcc3v3_sys>;
526*4882a593Smuzhiyun		vcc2-supply = <&vcc3v3_sys>;
527*4882a593Smuzhiyun		vcc3-supply = <&vcc3v3_sys>;
528*4882a593Smuzhiyun		vcc4-supply = <&vcc3v3_sys>;
529*4882a593Smuzhiyun		vcc6-supply = <&vcc3v3_sys>;
530*4882a593Smuzhiyun		vcc7-supply = <&vcc3v3_sys>;
531*4882a593Smuzhiyun		vcc8-supply = <&vcc3v3_sys>;
532*4882a593Smuzhiyun		vcc9-supply = <&vcc3v3_sys>;
533*4882a593Smuzhiyun		vcc10-supply = <&vcc3v3_sys>;
534*4882a593Smuzhiyun		vcc11-supply = <&vcc3v3_sys>;
535*4882a593Smuzhiyun		vcc12-supply = <&vcc3v3_sys>;
536*4882a593Smuzhiyun		vddio-supply = <&vcc1v8_pmu>;
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun		regulators {
539*4882a593Smuzhiyun			vdd_center: DCDC_REG1 {
540*4882a593Smuzhiyun				regulator-always-on;
541*4882a593Smuzhiyun				regulator-boot-on;
542*4882a593Smuzhiyun				regulator-min-microvolt = <750000>;
543*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
544*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
545*4882a593Smuzhiyun				regulator-name = "vdd_center";
546*4882a593Smuzhiyun				regulator-state-mem {
547*4882a593Smuzhiyun					regulator-off-in-suspend;
548*4882a593Smuzhiyun				};
549*4882a593Smuzhiyun			};
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun			vdd_cpu_l: DCDC_REG2 {
552*4882a593Smuzhiyun				regulator-always-on;
553*4882a593Smuzhiyun				regulator-boot-on;
554*4882a593Smuzhiyun				regulator-min-microvolt = <750000>;
555*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
556*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
557*4882a593Smuzhiyun				regulator-name = "vdd_cpu_l";
558*4882a593Smuzhiyun				regulator-state-mem {
559*4882a593Smuzhiyun					regulator-off-in-suspend;
560*4882a593Smuzhiyun				};
561*4882a593Smuzhiyun			};
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun			vcc_ddr: DCDC_REG3 {
564*4882a593Smuzhiyun				regulator-always-on;
565*4882a593Smuzhiyun				regulator-boot-on;
566*4882a593Smuzhiyun				regulator-name = "vcc_ddr";
567*4882a593Smuzhiyun				regulator-state-mem {
568*4882a593Smuzhiyun					regulator-on-in-suspend;
569*4882a593Smuzhiyun				};
570*4882a593Smuzhiyun			};
571*4882a593Smuzhiyun
572*4882a593Smuzhiyun			vcc_1v8: DCDC_REG4 {
573*4882a593Smuzhiyun				regulator-always-on;
574*4882a593Smuzhiyun				regulator-boot-on;
575*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
576*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
577*4882a593Smuzhiyun				regulator-name = "vcc_1v8";
578*4882a593Smuzhiyun				regulator-state-mem {
579*4882a593Smuzhiyun					regulator-on-in-suspend;
580*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
581*4882a593Smuzhiyun				};
582*4882a593Smuzhiyun			};
583*4882a593Smuzhiyun
584*4882a593Smuzhiyun			vcc1v8_dvp: LDO_REG1 {
585*4882a593Smuzhiyun				regulator-always-on;
586*4882a593Smuzhiyun				regulator-boot-on;
587*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
588*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
589*4882a593Smuzhiyun				regulator-name = "vcc1v8_dvp";
590*4882a593Smuzhiyun				regulator-state-mem {
591*4882a593Smuzhiyun					regulator-off-in-suspend;
592*4882a593Smuzhiyun				};
593*4882a593Smuzhiyun			};
594*4882a593Smuzhiyun
595*4882a593Smuzhiyun			vcc3v0_tp: LDO_REG2 {
596*4882a593Smuzhiyun				regulator-always-on;
597*4882a593Smuzhiyun				regulator-boot-on;
598*4882a593Smuzhiyun				regulator-min-microvolt = <3000000>;
599*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
600*4882a593Smuzhiyun				regulator-name = "vcc3v0_tp";
601*4882a593Smuzhiyun				regulator-state-mem {
602*4882a593Smuzhiyun					regulator-off-in-suspend;
603*4882a593Smuzhiyun				};
604*4882a593Smuzhiyun			};
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun			vcc1v8_pmu: LDO_REG3 {
607*4882a593Smuzhiyun				regulator-always-on;
608*4882a593Smuzhiyun				regulator-boot-on;
609*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
610*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
611*4882a593Smuzhiyun				regulator-name = "vcc1v8_pmu";
612*4882a593Smuzhiyun				regulator-state-mem {
613*4882a593Smuzhiyun					regulator-on-in-suspend;
614*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
615*4882a593Smuzhiyun				};
616*4882a593Smuzhiyun			};
617*4882a593Smuzhiyun
618*4882a593Smuzhiyun			vcc_sd: LDO_REG4 {
619*4882a593Smuzhiyun				regulator-always-on;
620*4882a593Smuzhiyun				regulator-boot-on;
621*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
622*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
623*4882a593Smuzhiyun				regulator-name = "vcc_sd";
624*4882a593Smuzhiyun				regulator-state-mem {
625*4882a593Smuzhiyun					regulator-on-in-suspend;
626*4882a593Smuzhiyun					regulator-suspend-microvolt = <3000000>;
627*4882a593Smuzhiyun				};
628*4882a593Smuzhiyun			};
629*4882a593Smuzhiyun
630*4882a593Smuzhiyun			vcca3v0_codec: LDO_REG5 {
631*4882a593Smuzhiyun				regulator-always-on;
632*4882a593Smuzhiyun				regulator-boot-on;
633*4882a593Smuzhiyun				regulator-min-microvolt = <3000000>;
634*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
635*4882a593Smuzhiyun				regulator-name = "vcca3v0_codec";
636*4882a593Smuzhiyun				regulator-state-mem {
637*4882a593Smuzhiyun					regulator-off-in-suspend;
638*4882a593Smuzhiyun				};
639*4882a593Smuzhiyun			};
640*4882a593Smuzhiyun
641*4882a593Smuzhiyun			vcc_1v5: LDO_REG6 {
642*4882a593Smuzhiyun				regulator-always-on;
643*4882a593Smuzhiyun				regulator-boot-on;
644*4882a593Smuzhiyun				regulator-min-microvolt = <1500000>;
645*4882a593Smuzhiyun				regulator-max-microvolt = <1500000>;
646*4882a593Smuzhiyun				regulator-name = "vcc_1v5";
647*4882a593Smuzhiyun				regulator-state-mem {
648*4882a593Smuzhiyun					regulator-on-in-suspend;
649*4882a593Smuzhiyun					regulator-suspend-microvolt = <1500000>;
650*4882a593Smuzhiyun				};
651*4882a593Smuzhiyun			};
652*4882a593Smuzhiyun
653*4882a593Smuzhiyun			vcca1v8_codec: LDO_REG7 {
654*4882a593Smuzhiyun				regulator-always-on;
655*4882a593Smuzhiyun				regulator-boot-on;
656*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
657*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
658*4882a593Smuzhiyun				regulator-name = "vcca1v8_codec";
659*4882a593Smuzhiyun				regulator-state-mem {
660*4882a593Smuzhiyun					regulator-off-in-suspend;
661*4882a593Smuzhiyun				};
662*4882a593Smuzhiyun			};
663*4882a593Smuzhiyun
664*4882a593Smuzhiyun			vcc_3v0: LDO_REG8 {
665*4882a593Smuzhiyun				regulator-always-on;
666*4882a593Smuzhiyun				regulator-boot-on;
667*4882a593Smuzhiyun				regulator-min-microvolt = <3000000>;
668*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
669*4882a593Smuzhiyun				regulator-name = "vcc_3v0";
670*4882a593Smuzhiyun				regulator-state-mem {
671*4882a593Smuzhiyun					regulator-on-in-suspend;
672*4882a593Smuzhiyun					regulator-suspend-microvolt = <3000000>;
673*4882a593Smuzhiyun				};
674*4882a593Smuzhiyun			};
675*4882a593Smuzhiyun
676*4882a593Smuzhiyun			vcc3v3_s3: SWITCH_REG1 {
677*4882a593Smuzhiyun				regulator-always-on;
678*4882a593Smuzhiyun				regulator-boot-on;
679*4882a593Smuzhiyun				regulator-name = "vcc3v3_s3";
680*4882a593Smuzhiyun				regulator-state-mem {
681*4882a593Smuzhiyun					regulator-off-in-suspend;
682*4882a593Smuzhiyun				};
683*4882a593Smuzhiyun			};
684*4882a593Smuzhiyun
685*4882a593Smuzhiyun			vcc3v3_s0: SWITCH_REG2 {
686*4882a593Smuzhiyun				regulator-always-on;
687*4882a593Smuzhiyun				regulator-boot-on;
688*4882a593Smuzhiyun				regulator-name = "vcc3v3_s0";
689*4882a593Smuzhiyun				regulator-state-mem {
690*4882a593Smuzhiyun					regulator-off-in-suspend;
691*4882a593Smuzhiyun				};
692*4882a593Smuzhiyun			};
693*4882a593Smuzhiyun		};
694*4882a593Smuzhiyun	};
695*4882a593Smuzhiyun};
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun&i2c1 {
698*4882a593Smuzhiyun	status = "okay";
699*4882a593Smuzhiyun	i2c-scl-rising-time-ns = <300>;
700*4882a593Smuzhiyun	i2c-scl-falling-time-ns = <15>;
701*4882a593Smuzhiyun
702*4882a593Smuzhiyun	rt5640: rt5640@1c {
703*4882a593Smuzhiyun		#sound-dai-cells = <0>;
704*4882a593Smuzhiyun		compatible = "realtek,rt5640";
705*4882a593Smuzhiyun		reg = <0x1c>;
706*4882a593Smuzhiyun		clocks = <&cru SCLK_I2S_8CH_OUT>;
707*4882a593Smuzhiyun		clock-names = "mclk";
708*4882a593Smuzhiyun		realtek,in1-differential;
709*4882a593Smuzhiyun		pinctrl-names = "default";
710*4882a593Smuzhiyun		pinctrl-0 = <&rt5640_hpcon &i2s_8ch_mclk>;
711*4882a593Smuzhiyun		hp-con-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
712*4882a593Smuzhiyun		//hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_LOW>;
713*4882a593Smuzhiyun		io-channels = <&saradc 4>;
714*4882a593Smuzhiyun		hp-det-adc-value = <500>;
715*4882a593Smuzhiyun		status = "okay";
716*4882a593Smuzhiyun	};
717*4882a593Smuzhiyun};
718*4882a593Smuzhiyun
719*4882a593Smuzhiyun&i2c3 {
720*4882a593Smuzhiyun	status = "okay";
721*4882a593Smuzhiyun	i2c-scl-rising-time-ns = <450>;
722*4882a593Smuzhiyun	i2c-scl-falling-time-ns = <15>;
723*4882a593Smuzhiyun};
724*4882a593Smuzhiyun
725*4882a593Smuzhiyun&i2c4 {
726*4882a593Smuzhiyun	status = "okay";
727*4882a593Smuzhiyun	i2c-scl-rising-time-ns = <600>;
728*4882a593Smuzhiyun	i2c-scl-falling-time-ns = <20>;
729*4882a593Smuzhiyun
730*4882a593Smuzhiyun	fusb0: fusb30x@22 {
731*4882a593Smuzhiyun		compatible = "fairchild,fusb302";
732*4882a593Smuzhiyun		reg = <0x22>;
733*4882a593Smuzhiyun		pinctrl-names = "default";
734*4882a593Smuzhiyun		pinctrl-0 = <&fusb0_int>;
735*4882a593Smuzhiyun		int-n-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
736*4882a593Smuzhiyun		vbus-5v-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
737*4882a593Smuzhiyun		status = "okay";
738*4882a593Smuzhiyun	};
739*4882a593Smuzhiyun
740*4882a593Smuzhiyun	gsl3680: gsl3680@41 {
741*4882a593Smuzhiyun		compatible = "gslX680-pad";
742*4882a593Smuzhiyun		reg = <0x41>;
743*4882a593Smuzhiyun		screen_max_x = <1536>;
744*4882a593Smuzhiyun		screen_max_y = <2048>;
745*4882a593Smuzhiyun		touch-gpio = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>;
746*4882a593Smuzhiyun		reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
747*4882a593Smuzhiyun		status = "okay";
748*4882a593Smuzhiyun	};
749*4882a593Smuzhiyun
750*4882a593Smuzhiyun	mpu6050: mpu@68 {
751*4882a593Smuzhiyun		compatible = "invensense,mpu6050";
752*4882a593Smuzhiyun		reg = <0x68>;
753*4882a593Smuzhiyun		mpu-int_config = <0x10>;
754*4882a593Smuzhiyun		mpu-level_shifter = <0>;
755*4882a593Smuzhiyun		mpu-orientation = <0 1 0 1 0 0 0 0 1>;
756*4882a593Smuzhiyun		orientation-x= <1>;
757*4882a593Smuzhiyun		orientation-y= <1>;
758*4882a593Smuzhiyun		orientation-z= <1>;
759*4882a593Smuzhiyun		irq-gpio = <&gpio1 4 IRQ_TYPE_LEVEL_LOW>;
760*4882a593Smuzhiyun		mpu-debug = <1>;
761*4882a593Smuzhiyun		status = "okay";
762*4882a593Smuzhiyun	};
763*4882a593Smuzhiyun};
764*4882a593Smuzhiyun
765*4882a593Smuzhiyun&i2s0 {
766*4882a593Smuzhiyun	status = "okay";
767*4882a593Smuzhiyun	rockchip,i2s-broken-burst-len;
768*4882a593Smuzhiyun	rockchip,playback-channels = <8>;
769*4882a593Smuzhiyun	rockchip,capture-channels = <8>;
770*4882a593Smuzhiyun	#sound-dai-cells = <0>;
771*4882a593Smuzhiyun};
772*4882a593Smuzhiyun
773*4882a593Smuzhiyun&i2s1 {
774*4882a593Smuzhiyun	status = "okay";
775*4882a593Smuzhiyun	rockchip,i2s-broken-burst-len;
776*4882a593Smuzhiyun	rockchip,playback-channels = <2>;
777*4882a593Smuzhiyun	rockchip,capture-channels = <2>;
778*4882a593Smuzhiyun	#sound-dai-cells = <0>;
779*4882a593Smuzhiyun};
780*4882a593Smuzhiyun
781*4882a593Smuzhiyun&i2s2 {
782*4882a593Smuzhiyun	#sound-dai-cells = <0>;
783*4882a593Smuzhiyun	status = "okay";
784*4882a593Smuzhiyun};
785*4882a593Smuzhiyun
786*4882a593Smuzhiyun&io_domains {
787*4882a593Smuzhiyun	status = "okay";
788*4882a593Smuzhiyun
789*4882a593Smuzhiyun	bt656-supply = <&vcc1v8_dvp>;		/* bt656_gpio2ab_ms */
790*4882a593Smuzhiyun	audio-supply = <&vcca1v8_codec>;	/* audio_gpio3d4a_ms */
791*4882a593Smuzhiyun	sdmmc-supply = <&vcc_sd>;		/* sdmmc_gpio4b_ms */
792*4882a593Smuzhiyun	gpio1830-supply = <&vcc_3v0>;		/* gpio1833_gpio4cd_ms */
793*4882a593Smuzhiyun};
794*4882a593Smuzhiyun
795*4882a593Smuzhiyun&pcie_phy {
796*4882a593Smuzhiyun	status = "okay";
797*4882a593Smuzhiyun};
798*4882a593Smuzhiyun
799*4882a593Smuzhiyun&pcie0 {
800*4882a593Smuzhiyun	ep-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>;
801*4882a593Smuzhiyun	num-lanes = <4>;
802*4882a593Smuzhiyun	pinctrl-names = "default";
803*4882a593Smuzhiyun	pinctrl-0 = <&pcie_clkreqn_cpm>;
804*4882a593Smuzhiyun	status = "okay";
805*4882a593Smuzhiyun};
806*4882a593Smuzhiyun
807*4882a593Smuzhiyun&pmu_io_domains {
808*4882a593Smuzhiyun	status = "okay";
809*4882a593Smuzhiyun	pmu1830-supply = <&vcc_3v0>;
810*4882a593Smuzhiyun};
811*4882a593Smuzhiyun
812*4882a593Smuzhiyun&pinctrl {
813*4882a593Smuzhiyun
814*4882a593Smuzhiyun	lcd-panel {
815*4882a593Smuzhiyun		lcd_panel_reset: lcd-panel-reset {
816*4882a593Smuzhiyun			rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;
817*4882a593Smuzhiyun		};
818*4882a593Smuzhiyun
819*4882a593Smuzhiyun		lcd_en: lcd-en {
820*4882a593Smuzhiyun			rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
821*4882a593Smuzhiyun		};
822*4882a593Smuzhiyun	};
823*4882a593Smuzhiyun
824*4882a593Smuzhiyun	pcie {
825*4882a593Smuzhiyun		pcie_drv: pcie-drv {
826*4882a593Smuzhiyun			rockchip,pins =
827*4882a593Smuzhiyun				<1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
828*4882a593Smuzhiyun			};
829*4882a593Smuzhiyun			pcie_3g_drv: pcie-3g-drv {
830*4882a593Smuzhiyun			rockchip,pins =
831*4882a593Smuzhiyun				<0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
832*4882a593Smuzhiyun		};
833*4882a593Smuzhiyun	};
834*4882a593Smuzhiyun
835*4882a593Smuzhiyun	pmic {
836*4882a593Smuzhiyun		vsel1_gpio: vsel1-gpio {
837*4882a593Smuzhiyun			rockchip,pins =
838*4882a593Smuzhiyun				<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
839*4882a593Smuzhiyun		};
840*4882a593Smuzhiyun
841*4882a593Smuzhiyun		vsel2_gpio: vsel2-gpio {
842*4882a593Smuzhiyun			rockchip,pins =
843*4882a593Smuzhiyun			<1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
844*4882a593Smuzhiyun		};
845*4882a593Smuzhiyun	};
846*4882a593Smuzhiyun
847*4882a593Smuzhiyun	sdio-pwrseq {
848*4882a593Smuzhiyun		wifi_enable_h: wifi-enable-h {
849*4882a593Smuzhiyun			rockchip,pins =
850*4882a593Smuzhiyun				<0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
851*4882a593Smuzhiyun		};
852*4882a593Smuzhiyun	};
853*4882a593Smuzhiyun
854*4882a593Smuzhiyun	wireless-bluetooth {
855*4882a593Smuzhiyun		uart0_gpios: uart0-gpios {
856*4882a593Smuzhiyun			rockchip,pins =
857*4882a593Smuzhiyun				<2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
858*4882a593Smuzhiyun		};
859*4882a593Smuzhiyun	};
860*4882a593Smuzhiyun
861*4882a593Smuzhiyun	rt5640 {
862*4882a593Smuzhiyun		rt5640_hpcon: rt5640-hpcon {
863*4882a593Smuzhiyun			rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
864*4882a593Smuzhiyun		};
865*4882a593Smuzhiyun	};
866*4882a593Smuzhiyun
867*4882a593Smuzhiyun	pmic {
868*4882a593Smuzhiyun		pmic_int_l: pmic-int-l {
869*4882a593Smuzhiyun			rockchip,pins =
870*4882a593Smuzhiyun				<1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
871*4882a593Smuzhiyun		};
872*4882a593Smuzhiyun
873*4882a593Smuzhiyun		pmic_dvs2: pmic-dvs2 {
874*4882a593Smuzhiyun			rockchip,pins =
875*4882a593Smuzhiyun				<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
876*4882a593Smuzhiyun		};
877*4882a593Smuzhiyun	};
878*4882a593Smuzhiyun
879*4882a593Smuzhiyun	usb2 {
880*4882a593Smuzhiyun		host_vbus_drv: host-vbus-drv {
881*4882a593Smuzhiyun			rockchip,pins =
882*4882a593Smuzhiyun				<4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
883*4882a593Smuzhiyun		};
884*4882a593Smuzhiyun	};
885*4882a593Smuzhiyun
886*4882a593Smuzhiyun	fusb30x {
887*4882a593Smuzhiyun		fusb0_int: fusb0-int {
888*4882a593Smuzhiyun			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
889*4882a593Smuzhiyun		};
890*4882a593Smuzhiyun	};
891*4882a593Smuzhiyun};
892*4882a593Smuzhiyun
893*4882a593Smuzhiyun&pwm0 {
894*4882a593Smuzhiyun	status = "okay";
895*4882a593Smuzhiyun};
896*4882a593Smuzhiyun
897*4882a593Smuzhiyun&pwm2 {
898*4882a593Smuzhiyun	status = "okay";
899*4882a593Smuzhiyun	pinctrl-names = "active";
900*4882a593Smuzhiyun	pinctrl-0 = <&pwm2_pin_pull_down>;
901*4882a593Smuzhiyun};
902*4882a593Smuzhiyun
903*4882a593Smuzhiyun&rockchip_suspend {
904*4882a593Smuzhiyun	rockchip,power-ctrl =
905*4882a593Smuzhiyun		<&gpio1 18 GPIO_ACTIVE_LOW>,
906*4882a593Smuzhiyun		<&gpio1 14 GPIO_ACTIVE_HIGH>;
907*4882a593Smuzhiyun};
908*4882a593Smuzhiyun
909*4882a593Smuzhiyun&saradc {
910*4882a593Smuzhiyun	status = "okay";
911*4882a593Smuzhiyun	vref-supply = <&vccadc_ref>;
912*4882a593Smuzhiyun};
913*4882a593Smuzhiyun
914*4882a593Smuzhiyun&sdhci {
915*4882a593Smuzhiyun	bus-width = <8>;
916*4882a593Smuzhiyun	keep-power-in-suspend;
917*4882a593Smuzhiyun	mmc-hs400-1_8v;
918*4882a593Smuzhiyun	mmc-hs400-enhanced-strobe;
919*4882a593Smuzhiyun	non-removable;
920*4882a593Smuzhiyun	status = "okay";
921*4882a593Smuzhiyun	no-sdio;
922*4882a593Smuzhiyun	no-sd;
923*4882a593Smuzhiyun};
924*4882a593Smuzhiyun
925*4882a593Smuzhiyun&sdmmc {
926*4882a593Smuzhiyun	max-frequency = <150000000>;
927*4882a593Smuzhiyun	no-sdio;
928*4882a593Smuzhiyun	no-mmc;
929*4882a593Smuzhiyun	bus-width = <4>;
930*4882a593Smuzhiyun	cap-mmc-highspeed;
931*4882a593Smuzhiyun	cap-sd-highspeed;
932*4882a593Smuzhiyun	disable-wp;
933*4882a593Smuzhiyun	num-slots = <1>;
934*4882a593Smuzhiyun	vqmmc-supply = <&vcc_sd>;
935*4882a593Smuzhiyun	pinctrl-names = "default";
936*4882a593Smuzhiyun	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
937*4882a593Smuzhiyun	status = "okay";
938*4882a593Smuzhiyun};
939*4882a593Smuzhiyun
940*4882a593Smuzhiyun&sdio0 {
941*4882a593Smuzhiyun	max-frequency = <50000000>;
942*4882a593Smuzhiyun	no-sd;
943*4882a593Smuzhiyun	no-mmc;
944*4882a593Smuzhiyun	bus-width = <4>;
945*4882a593Smuzhiyun	disable-wp;
946*4882a593Smuzhiyun	cap-sd-highspeed;
947*4882a593Smuzhiyun	keep-power-in-suspend;
948*4882a593Smuzhiyun	mmc-pwrseq = <&sdio_pwrseq>;
949*4882a593Smuzhiyun	non-removable;
950*4882a593Smuzhiyun	num-slots = <1>;
951*4882a593Smuzhiyun	pinctrl-names = "default";
952*4882a593Smuzhiyun	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
953*4882a593Smuzhiyun	sd-uhs-sdr104;
954*4882a593Smuzhiyun	status = "okay";
955*4882a593Smuzhiyun};
956*4882a593Smuzhiyun
957*4882a593Smuzhiyun&spdif {
958*4882a593Smuzhiyun	status = "okay";
959*4882a593Smuzhiyun	pinctrl-0 = <&spdif_bus_1>;
960*4882a593Smuzhiyun	i2c-scl-rising-time-ns = <450>;
961*4882a593Smuzhiyun	i2c-scl-falling-time-ns = <15>;
962*4882a593Smuzhiyun	#sound-dai-cells = <0>;
963*4882a593Smuzhiyun};
964*4882a593Smuzhiyun
965*4882a593Smuzhiyun&tcphy0 {
966*4882a593Smuzhiyun	extcon = <&fusb0>;
967*4882a593Smuzhiyun	status = "okay";
968*4882a593Smuzhiyun};
969*4882a593Smuzhiyun
970*4882a593Smuzhiyun&tcphy1 {
971*4882a593Smuzhiyun	status = "okay";
972*4882a593Smuzhiyun};
973*4882a593Smuzhiyun
974*4882a593Smuzhiyun&tsadc {
975*4882a593Smuzhiyun	/* tshut mode 0:CRU 1:GPIO */
976*4882a593Smuzhiyun	rockchip,hw-tshut-mode = <1>;
977*4882a593Smuzhiyun	/* tshut polarity 0:LOW 1:HIGH */
978*4882a593Smuzhiyun	rockchip,hw-tshut-polarity = <1>;
979*4882a593Smuzhiyun	status = "okay";
980*4882a593Smuzhiyun};
981*4882a593Smuzhiyun
982*4882a593Smuzhiyun&u2phy0 {
983*4882a593Smuzhiyun	status = "okay";
984*4882a593Smuzhiyun	extcon = <&fusb0>;
985*4882a593Smuzhiyun
986*4882a593Smuzhiyun	u2phy0_otg: otg-port {
987*4882a593Smuzhiyun		status = "okay";
988*4882a593Smuzhiyun	};
989*4882a593Smuzhiyun
990*4882a593Smuzhiyun	u2phy0_host: host-port {
991*4882a593Smuzhiyun		phy-supply = <&vcc5v0_host>;
992*4882a593Smuzhiyun		status = "okay";
993*4882a593Smuzhiyun	};
994*4882a593Smuzhiyun};
995*4882a593Smuzhiyun
996*4882a593Smuzhiyun&u2phy1 {
997*4882a593Smuzhiyun	status = "okay";
998*4882a593Smuzhiyun
999*4882a593Smuzhiyun	u2phy1_otg: otg-port {
1000*4882a593Smuzhiyun		status = "okay";
1001*4882a593Smuzhiyun	};
1002*4882a593Smuzhiyun
1003*4882a593Smuzhiyun	u2phy1_host: host-port {
1004*4882a593Smuzhiyun		phy-supply = <&vcc5v0_host>;
1005*4882a593Smuzhiyun		status = "okay";
1006*4882a593Smuzhiyun	};
1007*4882a593Smuzhiyun};
1008*4882a593Smuzhiyun
1009*4882a593Smuzhiyun&uart0 {
1010*4882a593Smuzhiyun	pinctrl-names = "default";
1011*4882a593Smuzhiyun	pinctrl-0 = <&uart0_xfer &uart0_cts>;
1012*4882a593Smuzhiyun	status = "okay";
1013*4882a593Smuzhiyun};
1014*4882a593Smuzhiyun
1015*4882a593Smuzhiyun&uart2 {
1016*4882a593Smuzhiyun	status = "okay";
1017*4882a593Smuzhiyun};
1018*4882a593Smuzhiyun
1019*4882a593Smuzhiyun&usbdrd3_0 {
1020*4882a593Smuzhiyun	status = "okay";
1021*4882a593Smuzhiyun};
1022*4882a593Smuzhiyun
1023*4882a593Smuzhiyun&usbdrd3_1 {
1024*4882a593Smuzhiyun	status = "okay";
1025*4882a593Smuzhiyun};
1026*4882a593Smuzhiyun
1027*4882a593Smuzhiyun&usbdrd_dwc3_0 {
1028*4882a593Smuzhiyun	status = "okay";
1029*4882a593Smuzhiyun	extcon = <&fusb0>;
1030*4882a593Smuzhiyun};
1031*4882a593Smuzhiyun
1032*4882a593Smuzhiyun&usbdrd_dwc3_1 {
1033*4882a593Smuzhiyun	status = "okay";
1034*4882a593Smuzhiyun	dr_mode = "host";
1035*4882a593Smuzhiyun};
1036*4882a593Smuzhiyun
1037*4882a593Smuzhiyun&usb_host0_ehci {
1038*4882a593Smuzhiyun	status = "okay";
1039*4882a593Smuzhiyun};
1040*4882a593Smuzhiyun
1041*4882a593Smuzhiyun&usb_host0_ohci {
1042*4882a593Smuzhiyun	status = "okay";
1043*4882a593Smuzhiyun};
1044*4882a593Smuzhiyun
1045*4882a593Smuzhiyun&usb_host1_ehci {
1046*4882a593Smuzhiyun	status = "okay";
1047*4882a593Smuzhiyun};
1048*4882a593Smuzhiyun
1049*4882a593Smuzhiyun&usb_host1_ohci {
1050*4882a593Smuzhiyun	status = "okay";
1051*4882a593Smuzhiyun};
1052*4882a593Smuzhiyun
1053*4882a593Smuzhiyun&vopb {
1054*4882a593Smuzhiyun	status = "okay";
1055*4882a593Smuzhiyun};
1056*4882a593Smuzhiyun
1057*4882a593Smuzhiyun&vopb_mmu {
1058*4882a593Smuzhiyun	status = "okay";
1059*4882a593Smuzhiyun};
1060*4882a593Smuzhiyun
1061*4882a593Smuzhiyun&vopl {
1062*4882a593Smuzhiyun	status = "okay";
1063*4882a593Smuzhiyun};
1064*4882a593Smuzhiyun
1065*4882a593Smuzhiyun&vopl_mmu {
1066*4882a593Smuzhiyun	status = "okay";
1067*4882a593Smuzhiyun};
1068