1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/dts-v1/;
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun#include "rk3399-evb-ind.dtsi"
9*4882a593Smuzhiyun#include "rk3399-android.dtsi"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun/ {
12*4882a593Smuzhiyun	model = "Rockchip RK3399 EVB IND LPDDR4 Board edp (Android)";
13*4882a593Smuzhiyun	compatible = "rockchip,android", "rockchip,rk3399-evb-ind-lpddr4-android", "rockchip,rk3399";
14*4882a593Smuzhiyun	chosen: chosen {
15*4882a593Smuzhiyun		bootargs = "earlycon=uart8250,mmio32,0xff1a0000 console=ttyFIQ0 init=/init initrd=0x62000001,0x00800000 coherent_pool=1m";
16*4882a593Smuzhiyun	};
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun	iram: sram@ff8d0000 {
19*4882a593Smuzhiyun		compatible = "mmio-sram";
20*4882a593Smuzhiyun		reg = <0x0 0xff8d0000 0x0 0x20000>;
21*4882a593Smuzhiyun	};
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun	vcc_lcd: vcc-lcd {
24*4882a593Smuzhiyun		compatible = "regulator-fixed";
25*4882a593Smuzhiyun		regulator-name = "vcc_lcd";
26*4882a593Smuzhiyun		startup-delay-us = <20000>;
27*4882a593Smuzhiyun		enable-active-high;
28*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
29*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
30*4882a593Smuzhiyun		regulator-boot-on;
31*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
32*4882a593Smuzhiyun	};
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun	panel: panel {
35*4882a593Smuzhiyun		compatible = "simple-panel";
36*4882a593Smuzhiyun		backlight = <&backlight>;
37*4882a593Smuzhiyun		power-supply = <&vcc_lcd>;
38*4882a593Smuzhiyun		reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
39*4882a593Smuzhiyun		prepare-delay-ms = <20>;
40*4882a593Smuzhiyun		reset-delay-ms = <20>;
41*4882a593Smuzhiyun		enable-delay-ms = <20>;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun		display-timings {
44*4882a593Smuzhiyun			native-mode = <&timing0>;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun			timing0: timing0 {
47*4882a593Smuzhiyun				clock-frequency = <200000000>;
48*4882a593Smuzhiyun				hactive = <1536>;
49*4882a593Smuzhiyun				vactive = <2048>;
50*4882a593Smuzhiyun				hfront-porch = <12>;
51*4882a593Smuzhiyun				hsync-len = <16>;
52*4882a593Smuzhiyun				hback-porch = <48>;
53*4882a593Smuzhiyun				vfront-porch = <8>;
54*4882a593Smuzhiyun				vsync-len = <4>;
55*4882a593Smuzhiyun				vback-porch = <8>;
56*4882a593Smuzhiyun				hsync-active = <0>;
57*4882a593Smuzhiyun				vsync-active = <0>;
58*4882a593Smuzhiyun				de-active = <0>;
59*4882a593Smuzhiyun				pixelclk-active = <0>;
60*4882a593Smuzhiyun			};
61*4882a593Smuzhiyun		};
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun		ports {
64*4882a593Smuzhiyun			panel_in: endpoint {
65*4882a593Smuzhiyun				remote-endpoint = <&edp_out>;
66*4882a593Smuzhiyun			};
67*4882a593Smuzhiyun		};
68*4882a593Smuzhiyun	};
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun	test-power {
71*4882a593Smuzhiyun		status = "okay";
72*4882a593Smuzhiyun	};
73*4882a593Smuzhiyun};
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun&backlight {
76*4882a593Smuzhiyun	enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
77*4882a593Smuzhiyun};
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun&dmac_bus {
80*4882a593Smuzhiyun	iram = <&iram>;
81*4882a593Smuzhiyun	rockchip,force-iram;
82*4882a593Smuzhiyun};
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun&dp_sound {
85*4882a593Smuzhiyun	status = "disabled";
86*4882a593Smuzhiyun};
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun&edp {
89*4882a593Smuzhiyun	status = "okay";
90*4882a593Smuzhiyun	force-hpd;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun	ports {
93*4882a593Smuzhiyun		port@1 {
94*4882a593Smuzhiyun			reg = <1>;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun			edp_out: endpoint {
97*4882a593Smuzhiyun				remote-endpoint = <&panel_in>;
98*4882a593Smuzhiyun			};
99*4882a593Smuzhiyun		};
100*4882a593Smuzhiyun	};
101*4882a593Smuzhiyun};
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun&edp_in_vopl {
104*4882a593Smuzhiyun	status = "disabled";
105*4882a593Smuzhiyun};
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun&i2c1 {
108*4882a593Smuzhiyun	status = "okay";
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun	sgm3784: sgm3784@30 {
111*4882a593Smuzhiyun		#address-cells = <1>;
112*4882a593Smuzhiyun		#size-cells = <0>;
113*4882a593Smuzhiyun		compatible = "sgmicro,gsm3784";
114*4882a593Smuzhiyun		reg = <0x30>;
115*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
116*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
117*4882a593Smuzhiyun		//enable-gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
118*4882a593Smuzhiyun		//strobe-gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
119*4882a593Smuzhiyun		status = "okay";
120*4882a593Smuzhiyun		sgm3784_led0: led@0 {
121*4882a593Smuzhiyun			reg = <0x0>;
122*4882a593Smuzhiyun			led-max-microamp = <299200>;
123*4882a593Smuzhiyun			flash-max-microamp = <1122000>;
124*4882a593Smuzhiyun			flash-max-timeout-us = <1600000>;
125*4882a593Smuzhiyun		};
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun		sgm3784_led1: led@1 {
128*4882a593Smuzhiyun			reg = <0x1>;
129*4882a593Smuzhiyun			led-max-microamp = <299200>;
130*4882a593Smuzhiyun			flash-max-microamp = <1122000>;
131*4882a593Smuzhiyun			flash-max-timeout-us = <1600000>;
132*4882a593Smuzhiyun		};
133*4882a593Smuzhiyun	};
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun	vm149c: vm149c@0c {
136*4882a593Smuzhiyun		compatible = "silicon touch,vm149c";
137*4882a593Smuzhiyun		status = "okay";
138*4882a593Smuzhiyun		reg = <0x0c>;
139*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
140*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
141*4882a593Smuzhiyun	};
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun	gc2145: gc2145@3c{
144*4882a593Smuzhiyun		status = "okay";
145*4882a593Smuzhiyun		compatible = "galaxycore,gc2145";
146*4882a593Smuzhiyun		reg = <0x3c>;
147*4882a593Smuzhiyun		pinctrl-names = "rockchip,camera_default";
148*4882a593Smuzhiyun		pinctrl-0 = <&cif_clkout>;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun		clocks = <&cru SCLK_CIF_OUT>;
151*4882a593Smuzhiyun		clock-names = "xvclk";
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun		/* avdd-supply = <>; */
154*4882a593Smuzhiyun		/* dvdd-supply = <>; */
155*4882a593Smuzhiyun		/* dovdd-supply = <>; */
156*4882a593Smuzhiyun		power-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
157*4882a593Smuzhiyun		pwdn-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
158*4882a593Smuzhiyun		rockchip,camera-module-index = <1>;
159*4882a593Smuzhiyun		rockchip,camera-module-facing = "front";
160*4882a593Smuzhiyun		rockchip,camera-module-name = "CameraKing";
161*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "Largan";
162*4882a593Smuzhiyun		port {
163*4882a593Smuzhiyun			gc2145_out: endpoint {
164*4882a593Smuzhiyun				remote-endpoint = <&dvp_in_fcam>;
165*4882a593Smuzhiyun			};
166*4882a593Smuzhiyun		};
167*4882a593Smuzhiyun	};
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun	ov13850: ov13850@10 {
170*4882a593Smuzhiyun		compatible = "ovti,ov13850";
171*4882a593Smuzhiyun		status = "okay";
172*4882a593Smuzhiyun		reg = <0x10>;
173*4882a593Smuzhiyun		clocks = <&cru SCLK_CIF_OUT>;
174*4882a593Smuzhiyun		clock-names = "xvclk";
175*4882a593Smuzhiyun		/* avdd-supply = <>; */
176*4882a593Smuzhiyun		/* dvdd-supply = <>; */
177*4882a593Smuzhiyun		/* dovdd-supply = <>; */
178*4882a593Smuzhiyun		/* reset-gpios = <>; */
179*4882a593Smuzhiyun		reset-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
180*4882a593Smuzhiyun		pwdn-gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
181*4882a593Smuzhiyun		pinctrl-names = "rockchip,camera_default";
182*4882a593Smuzhiyun		pinctrl-0 = <&cif_clkout>;
183*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
184*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
185*4882a593Smuzhiyun		rockchip,camera-module-name = "CMK-CT0116";
186*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "Largan-50013A1";
187*4882a593Smuzhiyun		lens-focus = <&vm149c>;
188*4882a593Smuzhiyun		flash-leds = <&sgm3784_led0 &sgm3784_led1>;
189*4882a593Smuzhiyun		port {
190*4882a593Smuzhiyun			ucam_out0: endpoint {
191*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ucam0>;
192*4882a593Smuzhiyun				//remote-endpoint = <&mipi_in_ucam1>;
193*4882a593Smuzhiyun				data-lanes = <1 2>;
194*4882a593Smuzhiyun			};
195*4882a593Smuzhiyun		};
196*4882a593Smuzhiyun	};
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun	ov4689: ov4689@36 {
199*4882a593Smuzhiyun		compatible = "ovti,ov4689";
200*4882a593Smuzhiyun		status = "disabled";
201*4882a593Smuzhiyun		reg = <0x36>;
202*4882a593Smuzhiyun		clocks = <&cru SCLK_CIF_OUT>;
203*4882a593Smuzhiyun		clock-names = "xvclk";
204*4882a593Smuzhiyun		/* avdd-supply = <>; */
205*4882a593Smuzhiyun		/* dvdd-supply = <>; */
206*4882a593Smuzhiyun		/* dovdd-supply = <>; */
207*4882a593Smuzhiyun		/* reset-gpios = <>; */
208*4882a593Smuzhiyun		reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
209*4882a593Smuzhiyun		pwdn-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
210*4882a593Smuzhiyun		pinctrl-names = "rockchip,camera_default";
211*4882a593Smuzhiyun		pinctrl-0 = <&cif_clkout>;
212*4882a593Smuzhiyun		rockchip,camera-module-index = <1>;
213*4882a593Smuzhiyun		rockchip,camera-module-facing = "front";
214*4882a593Smuzhiyun		rockchip,camera-module-name = "JSD3425-C1";
215*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "JSD3425-C1";
216*4882a593Smuzhiyun		port {
217*4882a593Smuzhiyun			ucam_out1: endpoint {
218*4882a593Smuzhiyun				//remote-endpoint = <&mipi_in_ucam0>;
219*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ucam1>;
220*4882a593Smuzhiyun				data-lanes = <1 2>;
221*4882a593Smuzhiyun			};
222*4882a593Smuzhiyun		};
223*4882a593Smuzhiyun	};
224*4882a593Smuzhiyun};
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun&i2s2 {
227*4882a593Smuzhiyun	#sound-dai-cells = <0>;
228*4882a593Smuzhiyun	status = "okay";
229*4882a593Smuzhiyun};
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun&isp0_mmu {
232*4882a593Smuzhiyun	status = "okay";
233*4882a593Smuzhiyun};
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun&isp1_mmu {
236*4882a593Smuzhiyun	status = "okay";
237*4882a593Smuzhiyun};
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun&mipi_dphy_rx0 {
240*4882a593Smuzhiyun	status = "okay";
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun	ports {
243*4882a593Smuzhiyun		#address-cells = <1>;
244*4882a593Smuzhiyun		#size-cells = <0>;
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun		port@0 {
247*4882a593Smuzhiyun			reg = <0>;
248*4882a593Smuzhiyun			#address-cells = <1>;
249*4882a593Smuzhiyun			#size-cells = <0>;
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun			mipi_in_ucam0: endpoint@1 {
252*4882a593Smuzhiyun				reg = <1>;
253*4882a593Smuzhiyun				remote-endpoint = <&ucam_out0>;
254*4882a593Smuzhiyun				data-lanes = <1 2>;
255*4882a593Smuzhiyun			};
256*4882a593Smuzhiyun		};
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun		port@1 {
259*4882a593Smuzhiyun			reg = <1>;
260*4882a593Smuzhiyun			#address-cells = <1>;
261*4882a593Smuzhiyun			#size-cells = <0>;
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun			dphy_rx0_out: endpoint@0 {
264*4882a593Smuzhiyun				reg = <0>;
265*4882a593Smuzhiyun				remote-endpoint = <&isp0_mipi_in>;
266*4882a593Smuzhiyun			};
267*4882a593Smuzhiyun		};
268*4882a593Smuzhiyun	};
269*4882a593Smuzhiyun};
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun&mipi_dphy_tx1rx1 {
272*4882a593Smuzhiyun	status = "okay";
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun	ports {
275*4882a593Smuzhiyun		#address-cells = <1>;
276*4882a593Smuzhiyun		#size-cells = <0>;
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun		port@0 {
279*4882a593Smuzhiyun			reg = <0>;
280*4882a593Smuzhiyun			#address-cells = <1>;
281*4882a593Smuzhiyun			#size-cells = <0>;
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun			mipi_in_ucam1: endpoint@1 {
284*4882a593Smuzhiyun				reg = <1>;
285*4882a593Smuzhiyun				remote-endpoint = <&ucam_out1>;
286*4882a593Smuzhiyun				data-lanes = <1 2>;
287*4882a593Smuzhiyun			};
288*4882a593Smuzhiyun		};
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun		port@1 {
291*4882a593Smuzhiyun			reg = <1>;
292*4882a593Smuzhiyun			#address-cells = <1>;
293*4882a593Smuzhiyun			#size-cells = <0>;
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun			dphy_tx1rx1_out: endpoint@0 {
296*4882a593Smuzhiyun				reg = <0>;
297*4882a593Smuzhiyun				remote-endpoint = <&isp1_mipi_in>;
298*4882a593Smuzhiyun			};
299*4882a593Smuzhiyun		};
300*4882a593Smuzhiyun	};
301*4882a593Smuzhiyun};
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun&hdmi_sound {
304*4882a593Smuzhiyun	status = "okay";
305*4882a593Smuzhiyun};
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun&route_edp {
308*4882a593Smuzhiyun	status = "okay";
309*4882a593Smuzhiyun};
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun&route_hdmi {
312*4882a593Smuzhiyun	status = "okay";
313*4882a593Smuzhiyun	connect = <&vopl_out_hdmi>;
314*4882a593Smuzhiyun};
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun&i2s1 {
317*4882a593Smuzhiyun	#sound-dai-cells = <0>;
318*4882a593Smuzhiyun	status = "okay";
319*4882a593Smuzhiyun};
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun&rk809_sound {
322*4882a593Smuzhiyun	status = "okay";
323*4882a593Smuzhiyun};
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun&hdmi_in_vopb {
326*4882a593Smuzhiyun	status = "disabled";
327*4882a593Smuzhiyun};
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun&rkisp1_0 {
330*4882a593Smuzhiyun	status = "okay";
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun	port {
333*4882a593Smuzhiyun		#address-cells = <1>;
334*4882a593Smuzhiyun		#size-cells = <0>;
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun		isp0_mipi_in: endpoint@0 {
337*4882a593Smuzhiyun			reg = <0>;
338*4882a593Smuzhiyun			remote-endpoint = <&dphy_rx0_out>;
339*4882a593Smuzhiyun		};
340*4882a593Smuzhiyun	};
341*4882a593Smuzhiyun};
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun&rkisp1_1 {
344*4882a593Smuzhiyun	status = "okay";
345*4882a593Smuzhiyun	pinctrl-names = "default";
346*4882a593Smuzhiyun	pinctrl-0 = <&cif_clkout &isp_dvp_d0d7>;
347*4882a593Smuzhiyun	port {
348*4882a593Smuzhiyun		#address-cells = <1>;
349*4882a593Smuzhiyun		#size-cells = <0>;
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun		isp1_mipi_in: endpoint@0 {
352*4882a593Smuzhiyun			reg = <0>;
353*4882a593Smuzhiyun			remote-endpoint = <&dphy_tx1rx1_out>;
354*4882a593Smuzhiyun		};
355*4882a593Smuzhiyun		dvp_in_fcam: endpoint@1 {
356*4882a593Smuzhiyun			reg = <1>;
357*4882a593Smuzhiyun			remote-endpoint = <&gc2145_out>;
358*4882a593Smuzhiyun		};
359*4882a593Smuzhiyun	};
360*4882a593Smuzhiyun};
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun/*
363*4882a593Smuzhiyun * if enable dp_sound, should disable spdif_sound and spdif_out
364*4882a593Smuzhiyun */
365*4882a593Smuzhiyun&spdif_out {
366*4882a593Smuzhiyun	status = "disabled";
367*4882a593Smuzhiyun};
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun&spdif_sound {
370*4882a593Smuzhiyun	status = "disabled";
371*4882a593Smuzhiyun};
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun&i2s0 {
374*4882a593Smuzhiyun	#sound-dai-cells = <0>;
375*4882a593Smuzhiyun	status = "disabled";
376*4882a593Smuzhiyun};
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun&tc358749x_sound {
379*4882a593Smuzhiyun	status = "disabled";
380*4882a593Smuzhiyun};
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun&pinctrl {
383*4882a593Smuzhiyun	lcd-panel {
384*4882a593Smuzhiyun		lcd_panel_reset: lcd-panel-reset {
385*4882a593Smuzhiyun			rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
386*4882a593Smuzhiyun		};
387*4882a593Smuzhiyun	};
388*4882a593Smuzhiyun};
389*4882a593Smuzhiyun
390