1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include <dt-bindings/memory/rk3399-dram.h> 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun ddr_timing: ddr_timing { 11*4882a593Smuzhiyun compatible = "rockchip,ddr-timing"; 12*4882a593Smuzhiyun ddr3_speed_bin = <21>; 13*4882a593Smuzhiyun pd_idle = <0>; 14*4882a593Smuzhiyun sr_idle = <0>; 15*4882a593Smuzhiyun sr_mc_gate_idle = <0>; 16*4882a593Smuzhiyun srpd_lite_idle = <0>; 17*4882a593Smuzhiyun standby_idle = <0>; 18*4882a593Smuzhiyun auto_lp_dis_freq = <666>; 19*4882a593Smuzhiyun ddr3_dll_dis_freq = <300>; 20*4882a593Smuzhiyun phy_dll_dis_freq = <260>; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun ddr3_odt_dis_freq = <666>; 23*4882a593Smuzhiyun ddr3_drv = <DDR3_DS_40ohm>; 24*4882a593Smuzhiyun ddr3_odt = <DDR3_ODT_120ohm>; 25*4882a593Smuzhiyun phy_ddr3_ca_drv = <PHY_DRV_ODT_40>; 26*4882a593Smuzhiyun phy_ddr3_dq_drv = <PHY_DRV_ODT_40>; 27*4882a593Smuzhiyun phy_ddr3_odt = <PHY_DRV_ODT_240>; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun lpddr3_odt_dis_freq = <666>; 30*4882a593Smuzhiyun lpddr3_drv = <LP3_DS_34ohm>; 31*4882a593Smuzhiyun lpddr3_odt = <LP3_ODT_240ohm>; 32*4882a593Smuzhiyun phy_lpddr3_ca_drv = <PHY_DRV_ODT_34_3>; 33*4882a593Smuzhiyun phy_lpddr3_dq_drv = <PHY_DRV_ODT_34_3>; 34*4882a593Smuzhiyun phy_lpddr3_odt = <PHY_DRV_ODT_240>; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun lpddr4_odt_dis_freq = <800>; 37*4882a593Smuzhiyun lpddr4_drv = <LP4_PDDS_240ohm>; 38*4882a593Smuzhiyun lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>; 39*4882a593Smuzhiyun lpddr4_ca_odt = <LP4_CA_ODT_DIS>; 40*4882a593Smuzhiyun phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>; 41*4882a593Smuzhiyun phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_40>; 42*4882a593Smuzhiyun phy_lpddr4_dq_drv = <PHY_DRV_ODT_60>; 43*4882a593Smuzhiyun phy_lpddr4_odt = <PHY_DRV_ODT_40>; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun}; 46