xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm64/rockchip/rk3368-xikp-avb.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/dts-v1/;
7*4882a593Smuzhiyun#include "rk3368-xikp.dtsi"
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun/ {
10*4882a593Smuzhiyun	model = "Rockchip rk3368 xkp avb board";
11*4882a593Smuzhiyun	compatible = "rockchip,xkp-avb", "rockchip,rk3368";
12*4882a593Smuzhiyun};
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun&firmware_android {
15*4882a593Smuzhiyun	compatible = "android,firmware";
16*4882a593Smuzhiyun	boot_devices = "ff0f0000.dwmmc,ff400000.nandc";
17*4882a593Smuzhiyun	vbmeta {
18*4882a593Smuzhiyun		compatible = "android,vbmeta";
19*4882a593Smuzhiyun		parts = "vbmeta,dtbo";
20*4882a593Smuzhiyun	};
21*4882a593Smuzhiyun	fstab {
22*4882a593Smuzhiyun		compatible = "android,fstab";
23*4882a593Smuzhiyun		vendor {
24*4882a593Smuzhiyun			compatible = "android,vendor";
25*4882a593Smuzhiyun			dev = "/dev/block/by-name/vendor";
26*4882a593Smuzhiyun			type = "ext4";
27*4882a593Smuzhiyun			mnt_flags = "ro,barrier=1,inode_readahead_blks=8";
28*4882a593Smuzhiyun			fsmgr_flags = "wait,avb";
29*4882a593Smuzhiyun		};
30*4882a593Smuzhiyun	};
31*4882a593Smuzhiyun};
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun&chosen {
34*4882a593Smuzhiyun	bootargs = "earlycon=uart8250,mmio32,0xff690000 console=ttyFIQ0 androidboot.baseband=N/A androidboot.veritymode=enforcing androidboot.hardware=rk30board androidboot.console=ttyFIQ0 androidboot.selinux=permissive init=/init kpti=0";
35*4882a593Smuzhiyun};
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun&i2c3 {
38*4882a593Smuzhiyun	status = "okay";
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun	gc2145: gc2145@3c {
41*4882a593Smuzhiyun		compatible = "galaxycore,gc2145";
42*4882a593Smuzhiyun		reg = <0x3c>;
43*4882a593Smuzhiyun		clocks = <&cru SCLK_VIP_OUT>;
44*4882a593Smuzhiyun		clock-names = "xvclk";
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun		power-gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
47*4882a593Smuzhiyun		pwdn-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
48*4882a593Smuzhiyun		rockchip,camera-module-index = <1>;
49*4882a593Smuzhiyun		rockchip,camera-module-facing = "front";
50*4882a593Smuzhiyun		rockchip,camera-module-name = "CameraKing";
51*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "Largan";
52*4882a593Smuzhiyun		port {
53*4882a593Smuzhiyun			gc2145_out: endpoint {
54*4882a593Smuzhiyun				remote-endpoint = <&isp_dvp_in>;
55*4882a593Smuzhiyun			};
56*4882a593Smuzhiyun		};
57*4882a593Smuzhiyun	};
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun	ov8858: ov8858@36 {
60*4882a593Smuzhiyun		compatible = "ovti,ov8858";
61*4882a593Smuzhiyun		reg = <0x36>;
62*4882a593Smuzhiyun		clocks = <&cru SCLK_VIP_OUT>;
63*4882a593Smuzhiyun		clock-names = "xvclk";
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
66*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
67*4882a593Smuzhiyun		rockchip,camera-module-name = "CameraKing";
68*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "Largan-9569A2";
69*4882a593Smuzhiyun		power-gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
70*4882a593Smuzhiyun		pwdn-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
71*4882a593Smuzhiyun		port {
72*4882a593Smuzhiyun			ov8858_out: endpoint {
73*4882a593Smuzhiyun				remote-endpoint = <&mipi_in>;
74*4882a593Smuzhiyun				data-lanes = <1 2>;
75*4882a593Smuzhiyun			};
76*4882a593Smuzhiyun		};
77*4882a593Smuzhiyun	};
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun};
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun&isp {
82*4882a593Smuzhiyun	status = "disabled";
83*4882a593Smuzhiyun};
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun&isp_mmu {
86*4882a593Smuzhiyun	status = "okay";
87*4882a593Smuzhiyun};
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun&mipi_dphy_rx0 {
90*4882a593Smuzhiyun	status = "okay";
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun	ports {
93*4882a593Smuzhiyun		#address-cells = <1>;
94*4882a593Smuzhiyun		#size-cells = <0>;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun		port@0 {
97*4882a593Smuzhiyun			reg = <0>;
98*4882a593Smuzhiyun			#address-cells = <1>;
99*4882a593Smuzhiyun			#size-cells = <0>;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun			mipi_in: endpoint@1 {
102*4882a593Smuzhiyun				reg = <1>;
103*4882a593Smuzhiyun				remote-endpoint = <&ov8858_out>;
104*4882a593Smuzhiyun				data-lanes = <1 2>;
105*4882a593Smuzhiyun			};
106*4882a593Smuzhiyun		};
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun		port@1 {
109*4882a593Smuzhiyun			reg = <1>;
110*4882a593Smuzhiyun			#address-cells = <1>;
111*4882a593Smuzhiyun			#size-cells = <0>;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun			dphy_rx_out: endpoint@0 {
114*4882a593Smuzhiyun				reg = <0>;
115*4882a593Smuzhiyun				remote-endpoint = <&isp_mipi_in>;
116*4882a593Smuzhiyun			};
117*4882a593Smuzhiyun		};
118*4882a593Smuzhiyun	};
119*4882a593Smuzhiyun};
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun&rkisp1 {
122*4882a593Smuzhiyun	status = "okay";
123*4882a593Smuzhiyun	pinctrl-names = "default";
124*4882a593Smuzhiyun	pinctrl-0 = <&isp_dvp_d2d9 &isp_dvp_d10d11 &cif_clkout>;
125*4882a593Smuzhiyun	port {
126*4882a593Smuzhiyun		#address-cells = <1>;
127*4882a593Smuzhiyun		#size-cells = <0>;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun		isp_dvp_in: endpoint@1 {
130*4882a593Smuzhiyun			reg = <1>;
131*4882a593Smuzhiyun			remote-endpoint = <&gc2145_out>;
132*4882a593Smuzhiyun		};
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun		isp_mipi_in: endpoint@0 {
135*4882a593Smuzhiyun			reg = <0>;
136*4882a593Smuzhiyun			remote-endpoint = <&dphy_rx_out>;
137*4882a593Smuzhiyun		};
138*4882a593Smuzhiyun	};
139*4882a593Smuzhiyun};
140