1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 8*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h> 9*4882a593Smuzhiyun#include <dt-bindings/sensor-dev.h> 10*4882a593Smuzhiyun#include "rk3368.dtsi" 11*4882a593Smuzhiyun#include "rk3368-android.dtsi" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun rt5640-sound { 15*4882a593Smuzhiyun compatible = "simple-audio-card"; 16*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 17*4882a593Smuzhiyun simple-audio-card,name = "rockchip,rt5640-codec"; 18*4882a593Smuzhiyun simple-audio-card,mclk-fs = <256>; 19*4882a593Smuzhiyun simple-audio-card,widgets = 20*4882a593Smuzhiyun "Microphone", "Mic Jack", 21*4882a593Smuzhiyun "Headphone", "Headphone Jack"; 22*4882a593Smuzhiyun simple-audio-card,routing = 23*4882a593Smuzhiyun "Mic Jack", "MICBIAS1", 24*4882a593Smuzhiyun "IN1P", "Mic Jack", 25*4882a593Smuzhiyun "Headphone Jack", "HPOL", 26*4882a593Smuzhiyun "Headphone Jack", "HPOR"; 27*4882a593Smuzhiyun simple-audio-card,dai-link@0 { 28*4882a593Smuzhiyun format = "i2s"; 29*4882a593Smuzhiyun cpu { 30*4882a593Smuzhiyun sound-dai = <&i2s_8ch>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun codec { 33*4882a593Smuzhiyun sound-dai = <&rt5640>; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun simple-audio-card,dai-link@1 { 38*4882a593Smuzhiyun format = "i2s"; 39*4882a593Smuzhiyun cpu { 40*4882a593Smuzhiyun sound-dai = <&i2s_8ch>; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun codec { 43*4882a593Smuzhiyun sound-dai = <&hdmi>; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun rk_headset { 49*4882a593Smuzhiyun compatible = "rockchip_headset"; 50*4882a593Smuzhiyun headset_gpio = <&gpio2 RK_PC3 GPIO_ACTIVE_HIGH>; 51*4882a593Smuzhiyun pinctrl-names = "default"; 52*4882a593Smuzhiyun pinctrl-0 = <&hp_det>; 53*4882a593Smuzhiyun io-channels = <&saradc 2>; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun ext_gmac: gmac-clk { 57*4882a593Smuzhiyun compatible = "fixed-clock"; 58*4882a593Smuzhiyun clock-frequency = <125000000>; 59*4882a593Smuzhiyun clock-output-names = "ext_gmac"; 60*4882a593Smuzhiyun #clock-cells = <0>; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun vcc_phy: vcc-phy-regulator { 64*4882a593Smuzhiyun compatible = "regulator-fixed"; 65*4882a593Smuzhiyun regulator-name = "vcc_phy"; 66*4882a593Smuzhiyun regulator-always-on; 67*4882a593Smuzhiyun regulator-boot-on; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun vcc_camera: vcc-camera-regulator { 71*4882a593Smuzhiyun compatible = "regulator-fixed"; 72*4882a593Smuzhiyun gpio = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; 73*4882a593Smuzhiyun pinctrl-names = "default"; 74*4882a593Smuzhiyun pinctrl-0 = <&camera_pwr>; 75*4882a593Smuzhiyun regulator-name = "vcc_camera"; 76*4882a593Smuzhiyun enable-active-high; 77*4882a593Smuzhiyun regulator-always-on; 78*4882a593Smuzhiyun regulator-boot-on; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun vcc_lcd: vcc-lcd-regulator { 82*4882a593Smuzhiyun compatible = "regulator-fixed"; 83*4882a593Smuzhiyun gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; 84*4882a593Smuzhiyun pinctrl-names = "default"; 85*4882a593Smuzhiyun pinctrl-0 = <&lcd_pwr>; 86*4882a593Smuzhiyun regulator-name = "vcc_lcd"; 87*4882a593Smuzhiyun enable-active-high; 88*4882a593Smuzhiyun regulator-boot-on; 89*4882a593Smuzhiyun regulator-state-mem { 90*4882a593Smuzhiyun regulator-off-in-suspend; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun vcc_otg_vbus: otg-vbus-regulator { 95*4882a593Smuzhiyun compatible = "regulator-fixed"; 96*4882a593Smuzhiyun gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; 97*4882a593Smuzhiyun pinctrl-names = "default"; 98*4882a593Smuzhiyun pinctrl-0 = <&otg_vbus_drv>; 99*4882a593Smuzhiyun regulator-name = "vcc_otg_vbus"; 100*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 101*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 102*4882a593Smuzhiyun enable-active-high; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun backlight: backlight { 106*4882a593Smuzhiyun compatible = "pwm-backlight"; 107*4882a593Smuzhiyun pwms = <&pwm3 0 25000 0>; 108*4882a593Smuzhiyun brightness-levels = < 109*4882a593Smuzhiyun 0 1 2 3 4 5 6 7 110*4882a593Smuzhiyun 8 9 10 11 12 13 14 15 111*4882a593Smuzhiyun 16 17 18 19 20 21 22 23 112*4882a593Smuzhiyun 24 25 26 27 28 29 30 31 113*4882a593Smuzhiyun 32 33 34 35 36 37 38 39 114*4882a593Smuzhiyun 40 41 42 43 44 45 46 47 115*4882a593Smuzhiyun 48 49 50 51 52 53 54 55 116*4882a593Smuzhiyun 56 57 58 59 60 61 62 63 117*4882a593Smuzhiyun 64 65 66 67 68 69 70 71 118*4882a593Smuzhiyun 72 73 74 75 76 77 78 79 119*4882a593Smuzhiyun 80 81 82 83 84 85 86 87 120*4882a593Smuzhiyun 88 89 90 91 92 93 94 95 121*4882a593Smuzhiyun 96 97 98 99 100 101 102 103 122*4882a593Smuzhiyun 104 105 106 107 108 109 110 111 123*4882a593Smuzhiyun 112 113 114 115 116 117 118 119 124*4882a593Smuzhiyun 120 121 122 123 124 125 126 127 125*4882a593Smuzhiyun 128 129 130 131 132 133 134 135 126*4882a593Smuzhiyun 136 137 138 139 140 141 142 143 127*4882a593Smuzhiyun 144 145 146 147 148 149 150 151 128*4882a593Smuzhiyun 152 153 154 155 156 157 158 159 129*4882a593Smuzhiyun 160 161 162 163 164 165 166 167 130*4882a593Smuzhiyun 168 169 170 171 172 173 174 175 131*4882a593Smuzhiyun 176 177 178 179 180 181 182 183 132*4882a593Smuzhiyun 184 185 186 187 188 189 190 191 133*4882a593Smuzhiyun 192 193 194 195 196 197 198 199 134*4882a593Smuzhiyun 200 201 202 203 204 205 206 207 135*4882a593Smuzhiyun 208 209 210 211 212 213 214 215 136*4882a593Smuzhiyun 216 217 218 219 220 221 222 223 137*4882a593Smuzhiyun 224 225 226 227 228 229 230 231 138*4882a593Smuzhiyun 232 233 234 235 236 237 238 239 139*4882a593Smuzhiyun 240 241 242 243 244 245 246 247 140*4882a593Smuzhiyun 248 249 250 251 252 253 254 255>; 141*4882a593Smuzhiyun default-brightness-level = <200>; 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun panel { 145*4882a593Smuzhiyun compatible = "samsung,lsl070nl01", "simple-panel"; 146*4882a593Smuzhiyun backlight = <&backlight>; 147*4882a593Smuzhiyun enable-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; 148*4882a593Smuzhiyun enable-delay-ms = <120>; 149*4882a593Smuzhiyun prepare-delay-ms = <2>; 150*4882a593Smuzhiyun unprepare-delay-ms = <20>; 151*4882a593Smuzhiyun disable-delay-ms = <50>; 152*4882a593Smuzhiyun width-mm = <68>; 153*4882a593Smuzhiyun height-mm = <121>; 154*4882a593Smuzhiyun rockchip,data-mapping = "vesa"; 155*4882a593Smuzhiyun rockchip,data-width = <24>; 156*4882a593Smuzhiyun rockchip,output = "lvds"; 157*4882a593Smuzhiyun status = "disabled"; 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun display-timings { 160*4882a593Smuzhiyun native-mode = <&timing0>; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun timing0: timing0 { 163*4882a593Smuzhiyun clock-frequency = <160000000>; 164*4882a593Smuzhiyun hactive = <1200>; 165*4882a593Smuzhiyun vactive = <1920>; 166*4882a593Smuzhiyun hback-porch = <60>; 167*4882a593Smuzhiyun hfront-porch = <80>; 168*4882a593Smuzhiyun vback-porch = <25>; 169*4882a593Smuzhiyun vfront-porch = <35>; 170*4882a593Smuzhiyun hsync-len = <1>; 171*4882a593Smuzhiyun vsync-len = <1>; 172*4882a593Smuzhiyun hsync-active = <0>; 173*4882a593Smuzhiyun vsync-active = <0>; 174*4882a593Smuzhiyun de-active = <0>; 175*4882a593Smuzhiyun pixelclk-active = <0>; 176*4882a593Smuzhiyun }; 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun port { 180*4882a593Smuzhiyun panel_in: endpoint { 181*4882a593Smuzhiyun remote-endpoint = <&edp_out>; 182*4882a593Smuzhiyun }; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun }; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun charge-animation { 187*4882a593Smuzhiyun compatible = "rockchip,uboot-charge"; 188*4882a593Smuzhiyun rockchip,uboot-charge-on = <1>; 189*4882a593Smuzhiyun rockchip,android-charge-on = <0>; 190*4882a593Smuzhiyun rockchip,uboot-low-power-voltage = <3500>; 191*4882a593Smuzhiyun rockchip,screen-on-voltage = <3600>; 192*4882a593Smuzhiyun status = "okay"; 193*4882a593Smuzhiyun }; 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun gpio_keys: gpio-keys { 196*4882a593Smuzhiyun compatible = "gpio-keys"; 197*4882a593Smuzhiyun autorepeat; 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun power { 200*4882a593Smuzhiyun debounce-interval = <100>; 201*4882a593Smuzhiyun gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; 202*4882a593Smuzhiyun label = "GPIO Key Power"; 203*4882a593Smuzhiyun linux,code = <KEY_POWER>; 204*4882a593Smuzhiyun wakeup-source; 205*4882a593Smuzhiyun }; 206*4882a593Smuzhiyun }; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun adc_keys: adc-keys { 209*4882a593Smuzhiyun compatible = "adc-keys"; 210*4882a593Smuzhiyun io-channels = <&saradc 1>; 211*4882a593Smuzhiyun io-channel-names = "buttons"; 212*4882a593Smuzhiyun keyup-threshold-microvolt = <1024000>; 213*4882a593Smuzhiyun poll-interval = <100>; 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun vol-up-key { 216*4882a593Smuzhiyun label = "volume up"; 217*4882a593Smuzhiyun linux,code = <KEY_VOLUMEUP>; 218*4882a593Smuzhiyun press-threshold-microvolt = <1000>; 219*4882a593Smuzhiyun }; 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun vol-down-key { 222*4882a593Smuzhiyun label = "volume down"; 223*4882a593Smuzhiyun linux,code = <KEY_VOLUMEDOWN>; 224*4882a593Smuzhiyun press-threshold-microvolt = <170000>; 225*4882a593Smuzhiyun }; 226*4882a593Smuzhiyun }; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun sdio_pwrseq: sdio-pwrseq { 229*4882a593Smuzhiyun compatible = "mmc-pwrseq-simple"; 230*4882a593Smuzhiyun clocks = <&rk808 1>; 231*4882a593Smuzhiyun clock-names = "ext_clock"; 232*4882a593Smuzhiyun pinctrl-names = "default"; 233*4882a593Smuzhiyun pinctrl-0 = <&wifi_enable_h>; 234*4882a593Smuzhiyun /* 235*4882a593Smuzhiyun * On the module itself this is one of these (depending 236*4882a593Smuzhiyun * on the actual card populated): 237*4882a593Smuzhiyun * - SDIO_RESET_L_WL_REG_ON 238*4882a593Smuzhiyun * - PDN (power down when low) 239*4882a593Smuzhiyun */ 240*4882a593Smuzhiyun reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ 241*4882a593Smuzhiyun }; 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun wireless-wlan { 244*4882a593Smuzhiyun compatible = "wlan-platdata"; 245*4882a593Smuzhiyun rockchip,grf = <&grf>; 246*4882a593Smuzhiyun wifi_chip_type = "ap6255"; 247*4882a593Smuzhiyun sdio_vref = <1800>; //1800mv or 3300mv 248*4882a593Smuzhiyun WIFI,host_wake_irq = <&gpio3 6 GPIO_ACTIVE_HIGH>; 249*4882a593Smuzhiyun status = "okay"; 250*4882a593Smuzhiyun }; 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun wireless-bluetooth { 253*4882a593Smuzhiyun compatible = "bluetooth-platdata"; 254*4882a593Smuzhiyun clocks = <&rk808 1>; 255*4882a593Smuzhiyun clock-names = "ext_clock"; 256*4882a593Smuzhiyun uart_rts_gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; 257*4882a593Smuzhiyun pinctrl-names = "default","rts_gpio"; 258*4882a593Smuzhiyun pinctrl-0 = <&uart0_rts>; 259*4882a593Smuzhiyun pinctrl-1 = <&uart0_rts_gpio>; 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun /* BT,power_gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>; */ 262*4882a593Smuzhiyun BT,reset_gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; 263*4882a593Smuzhiyun BT,wake_gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>; 264*4882a593Smuzhiyun BT,wake_host_irq = <&gpio3 7 GPIO_ACTIVE_HIGH>; 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun status = "okay"; 267*4882a593Smuzhiyun }; 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun rk_modem: rk-modem { 270*4882a593Smuzhiyun compatible="4g-modem-platdata"; 271*4882a593Smuzhiyun pinctrl-names = "default"; 272*4882a593Smuzhiyun pinctrl-0 = <<e_vbat <e_power_en <e_reset>; 273*4882a593Smuzhiyun 4G,vbat-gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; 274*4882a593Smuzhiyun 4G,power-gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; 275*4882a593Smuzhiyun 4G,reset-gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; 276*4882a593Smuzhiyun status = "okay"; 277*4882a593Smuzhiyun }; 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun vcc_sys: vcc-sys { 280*4882a593Smuzhiyun compatible = "regulator-fixed"; 281*4882a593Smuzhiyun regulator-name = "vcc_sys"; 282*4882a593Smuzhiyun regulator-always-on; 283*4882a593Smuzhiyun regulator-boot-on; 284*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 285*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 286*4882a593Smuzhiyun }; 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun xin32k: xin32k { 289*4882a593Smuzhiyun compatible = "fixed-clock"; 290*4882a593Smuzhiyun clock-frequency = <32768>; 291*4882a593Smuzhiyun clock-output-names = "xin32k"; 292*4882a593Smuzhiyun #clock-cells = <0>; 293*4882a593Smuzhiyun }; 294*4882a593Smuzhiyun}; 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun&cpu_l0 { 297*4882a593Smuzhiyun cpu-supply = <&vdd_cpu>; 298*4882a593Smuzhiyun}; 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun&cpu_l1 { 301*4882a593Smuzhiyun cpu-supply = <&vdd_cpu>; 302*4882a593Smuzhiyun}; 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun&cpu_l2 { 305*4882a593Smuzhiyun cpu-supply = <&vdd_cpu>; 306*4882a593Smuzhiyun}; 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun&cpu_l3 { 309*4882a593Smuzhiyun cpu-supply = <&vdd_cpu>; 310*4882a593Smuzhiyun}; 311*4882a593Smuzhiyun 312*4882a593Smuzhiyun&cpu_b0 { 313*4882a593Smuzhiyun cpu-supply = <&vdd_cpu>; 314*4882a593Smuzhiyun}; 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun&cpu_b1 { 317*4882a593Smuzhiyun cpu-supply = <&vdd_cpu>; 318*4882a593Smuzhiyun}; 319*4882a593Smuzhiyun 320*4882a593Smuzhiyun&cpu_b2 { 321*4882a593Smuzhiyun cpu-supply = <&vdd_cpu>; 322*4882a593Smuzhiyun}; 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun&cpu_b3 { 325*4882a593Smuzhiyun cpu-supply = <&vdd_cpu>; 326*4882a593Smuzhiyun}; 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun&gpu { 329*4882a593Smuzhiyun logic-supply = <&vdd_log>; 330*4882a593Smuzhiyun}; 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun&dfi { 333*4882a593Smuzhiyun status = "okay"; 334*4882a593Smuzhiyun}; 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun&dmc { 337*4882a593Smuzhiyun status = "okay"; 338*4882a593Smuzhiyun center-supply = <&vdd_log>; 339*4882a593Smuzhiyun devfreq-events = <&dfi>; 340*4882a593Smuzhiyun upthreshold = <60>; 341*4882a593Smuzhiyun downdifferential = <20>; 342*4882a593Smuzhiyun system-status-freq = < 343*4882a593Smuzhiyun /*system status freq(KHz)*/ 344*4882a593Smuzhiyun SYS_STATUS_NORMAL 600000 345*4882a593Smuzhiyun SYS_STATUS_REBOOT 600000 346*4882a593Smuzhiyun SYS_STATUS_SUSPEND 240000 347*4882a593Smuzhiyun SYS_STATUS_VIDEO_1080P 396000 348*4882a593Smuzhiyun SYS_STATUS_VIDEO_4K 600000 349*4882a593Smuzhiyun SYS_STATUS_PERFORMANCE 600000 350*4882a593Smuzhiyun SYS_STATUS_BOOST 396000 351*4882a593Smuzhiyun SYS_STATUS_DUALVIEW 600000 352*4882a593Smuzhiyun SYS_STATUS_ISP 528000 353*4882a593Smuzhiyun >; 354*4882a593Smuzhiyun vop-bw-dmc-freq = < 355*4882a593Smuzhiyun /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */ 356*4882a593Smuzhiyun 0 582 240000 357*4882a593Smuzhiyun 583 99999 396000 358*4882a593Smuzhiyun >; 359*4882a593Smuzhiyun auto-min-freq = <240000>; 360*4882a593Smuzhiyun auto-freq-en = <0>; 361*4882a593Smuzhiyun}; 362*4882a593Smuzhiyun 363*4882a593Smuzhiyun&rockchip_suspend { 364*4882a593Smuzhiyun status = "okay"; 365*4882a593Smuzhiyun rockchip,sleep-mode-config = < 366*4882a593Smuzhiyun (0 367*4882a593Smuzhiyun | RKPM_SLP_ARMOFF 368*4882a593Smuzhiyun | RKPM_SLP_PMU_PLLS_PWRDN 369*4882a593Smuzhiyun | RKPM_SLP_PMU_PMUALIVE_32K 370*4882a593Smuzhiyun | RKPM_SLP_SFT_PLLS_DEEP 371*4882a593Smuzhiyun | RKPM_SLP_PMU_DIS_OSC 372*4882a593Smuzhiyun | RKPM_SLP_SFT_PD_NBSCUS 373*4882a593Smuzhiyun ) 374*4882a593Smuzhiyun >; 375*4882a593Smuzhiyun rockchip,wakeup-config = < 376*4882a593Smuzhiyun (0 377*4882a593Smuzhiyun | RKPM_GPIO_WKUP_EN 378*4882a593Smuzhiyun | RKPM_USB_WKUP_EN 379*4882a593Smuzhiyun | RKPM_CLUSTER_L_WKUP_EN 380*4882a593Smuzhiyun ) 381*4882a593Smuzhiyun >; 382*4882a593Smuzhiyun}; 383*4882a593Smuzhiyun 384*4882a593Smuzhiyun&emmc { 385*4882a593Smuzhiyun bus-width = <8>; 386*4882a593Smuzhiyun cap-mmc-highspeed; 387*4882a593Smuzhiyun mmc-hs200-1_8v; 388*4882a593Smuzhiyun no-sdio; 389*4882a593Smuzhiyun no-sd; 390*4882a593Smuzhiyun disable-wp; 391*4882a593Smuzhiyun non-removable; 392*4882a593Smuzhiyun num-slots = <1>; 393*4882a593Smuzhiyun status = "okay"; 394*4882a593Smuzhiyun}; 395*4882a593Smuzhiyun 396*4882a593Smuzhiyun&nandc0 { 397*4882a593Smuzhiyun status = "okay"; 398*4882a593Smuzhiyun}; 399*4882a593Smuzhiyun 400*4882a593Smuzhiyun&sdmmc { 401*4882a593Smuzhiyun clock-frequency = <37500000>; 402*4882a593Smuzhiyun clock-freq-min-max = <400000 37500000>; 403*4882a593Smuzhiyun no-sdio; 404*4882a593Smuzhiyun no-mmc; 405*4882a593Smuzhiyun cap-mmc-highspeed; 406*4882a593Smuzhiyun cap-sd-highspeed; 407*4882a593Smuzhiyun card-detect-delay = <200>; 408*4882a593Smuzhiyun disable-wp; 409*4882a593Smuzhiyun num-slots = <1>; 410*4882a593Smuzhiyun pinctrl-names = "default"; 411*4882a593Smuzhiyun pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; 412*4882a593Smuzhiyun status = "disabled"; 413*4882a593Smuzhiyun}; 414*4882a593Smuzhiyun 415*4882a593Smuzhiyun&sdio0 { 416*4882a593Smuzhiyun clock-frequency = <100000000>; 417*4882a593Smuzhiyun clock-freq-min-max = <200000 100000000>; 418*4882a593Smuzhiyun no-sd; 419*4882a593Smuzhiyun no-mmc; 420*4882a593Smuzhiyun bus-width = <4>; 421*4882a593Smuzhiyun disable-wp; 422*4882a593Smuzhiyun cap-sd-highspeed; 423*4882a593Smuzhiyun cap-sdio-irq; 424*4882a593Smuzhiyun keep-power-in-suspend; 425*4882a593Smuzhiyun mmc-pwrseq = <&sdio_pwrseq>; 426*4882a593Smuzhiyun non-removable; 427*4882a593Smuzhiyun num-slots = <1>; 428*4882a593Smuzhiyun pinctrl-names = "default"; 429*4882a593Smuzhiyun pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; 430*4882a593Smuzhiyun sd-uhs-sdr104; 431*4882a593Smuzhiyun status = "okay"; 432*4882a593Smuzhiyun}; 433*4882a593Smuzhiyun 434*4882a593Smuzhiyun&i2c0 { 435*4882a593Smuzhiyun status = "okay"; 436*4882a593Smuzhiyun 437*4882a593Smuzhiyun rk808: pmic@1b { 438*4882a593Smuzhiyun status = "okay"; 439*4882a593Smuzhiyun compatible = "rockchip,rk808"; 440*4882a593Smuzhiyun reg = <0x1b>; 441*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 442*4882a593Smuzhiyun interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 443*4882a593Smuzhiyun pinctrl-names = "default"; 444*4882a593Smuzhiyun pinctrl-0 = <&pmic_int>, <&pmic_sleep>; 445*4882a593Smuzhiyun rockchip,system-power-controller; 446*4882a593Smuzhiyun wakeup-source; 447*4882a593Smuzhiyun vcc1-supply = <&vcc_sys>; 448*4882a593Smuzhiyun vcc2-supply = <&vcc_sys>; 449*4882a593Smuzhiyun vcc3-supply = <&vcc_sys>; 450*4882a593Smuzhiyun vcc4-supply = <&vcc_sys>; 451*4882a593Smuzhiyun vcc6-supply = <&vcc_sys>; 452*4882a593Smuzhiyun vcc7-supply = <&vcc_sys>; 453*4882a593Smuzhiyun vcc8-supply = <&vcc_io>; 454*4882a593Smuzhiyun vcc9-supply = <&vcc_sys>; 455*4882a593Smuzhiyun vcc10-supply = <&vcc_sys>; 456*4882a593Smuzhiyun vcc11-supply = <&vcc_sys>; 457*4882a593Smuzhiyun vcc12-supply = <&vcc_io>; 458*4882a593Smuzhiyun clock-output-names = "rk808-clkout1", "rk808-clkout2"; 459*4882a593Smuzhiyun #clock-cells = <1>; 460*4882a593Smuzhiyun 461*4882a593Smuzhiyun regulators { 462*4882a593Smuzhiyun vdd_cpu: DCDC_REG1 { 463*4882a593Smuzhiyun regulator-always-on; 464*4882a593Smuzhiyun regulator-boot-on; 465*4882a593Smuzhiyun regulator-min-microvolt = <700000>; 466*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 467*4882a593Smuzhiyun regulator-name = "vdd_cpu"; 468*4882a593Smuzhiyun regulator-state-mem { 469*4882a593Smuzhiyun regulator-off-in-suspend; 470*4882a593Smuzhiyun }; 471*4882a593Smuzhiyun }; 472*4882a593Smuzhiyun 473*4882a593Smuzhiyun vdd_log: DCDC_REG2 { 474*4882a593Smuzhiyun regulator-always-on; 475*4882a593Smuzhiyun regulator-boot-on; 476*4882a593Smuzhiyun regulator-min-microvolt = <700000>; 477*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 478*4882a593Smuzhiyun regulator-name = "vdd_log"; 479*4882a593Smuzhiyun regulator-state-mem { 480*4882a593Smuzhiyun regulator-on-in-suspend; 481*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 482*4882a593Smuzhiyun }; 483*4882a593Smuzhiyun }; 484*4882a593Smuzhiyun 485*4882a593Smuzhiyun vcc_ddr: DCDC_REG3 { 486*4882a593Smuzhiyun regulator-always-on; 487*4882a593Smuzhiyun regulator-boot-on; 488*4882a593Smuzhiyun regulator-name = "vcc_ddr"; 489*4882a593Smuzhiyun regulator-state-mem { 490*4882a593Smuzhiyun regulator-on-in-suspend; 491*4882a593Smuzhiyun }; 492*4882a593Smuzhiyun }; 493*4882a593Smuzhiyun 494*4882a593Smuzhiyun vcc_io: DCDC_REG4 { 495*4882a593Smuzhiyun regulator-always-on; 496*4882a593Smuzhiyun regulator-boot-on; 497*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 498*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 499*4882a593Smuzhiyun regulator-name = "vcc_io"; 500*4882a593Smuzhiyun regulator-state-mem { 501*4882a593Smuzhiyun regulator-on-in-suspend; 502*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 503*4882a593Smuzhiyun }; 504*4882a593Smuzhiyun }; 505*4882a593Smuzhiyun 506*4882a593Smuzhiyun vcc18_flash: LDO_REG1 { 507*4882a593Smuzhiyun regulator-always-on; 508*4882a593Smuzhiyun regulator-boot-on; 509*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 510*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 511*4882a593Smuzhiyun regulator-name = "vcc18_flash"; 512*4882a593Smuzhiyun regulator-state-mem { 513*4882a593Smuzhiyun regulator-on-in-suspend; 514*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 515*4882a593Smuzhiyun }; 516*4882a593Smuzhiyun }; 517*4882a593Smuzhiyun 518*4882a593Smuzhiyun vcca_33: LDO_REG2 { 519*4882a593Smuzhiyun regulator-always-on; 520*4882a593Smuzhiyun regulator-boot-on; 521*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 522*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 523*4882a593Smuzhiyun regulator-name = "vcca_33"; 524*4882a593Smuzhiyun regulator-state-mem { 525*4882a593Smuzhiyun regulator-off-in-suspend; 526*4882a593Smuzhiyun }; 527*4882a593Smuzhiyun }; 528*4882a593Smuzhiyun 529*4882a593Smuzhiyun vdd_10: LDO_REG3 { 530*4882a593Smuzhiyun regulator-always-on; 531*4882a593Smuzhiyun regulator-boot-on; 532*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 533*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 534*4882a593Smuzhiyun regulator-name = "vdd_10"; 535*4882a593Smuzhiyun regulator-state-mem { 536*4882a593Smuzhiyun regulator-on-in-suspend; 537*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 538*4882a593Smuzhiyun }; 539*4882a593Smuzhiyun }; 540*4882a593Smuzhiyun 541*4882a593Smuzhiyun vcca_18: LDO_REG4 { 542*4882a593Smuzhiyun regulator-always-on; 543*4882a593Smuzhiyun regulator-boot-on; 544*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 545*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 546*4882a593Smuzhiyun regulator-name = "vcca_18"; 547*4882a593Smuzhiyun regulator-state-mem { 548*4882a593Smuzhiyun regulator-off-in-suspend; 549*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 550*4882a593Smuzhiyun }; 551*4882a593Smuzhiyun }; 552*4882a593Smuzhiyun 553*4882a593Smuzhiyun vccio_sd: LDO_REG5 { 554*4882a593Smuzhiyun regulator-always-on; 555*4882a593Smuzhiyun regulator-boot-on; 556*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 557*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 558*4882a593Smuzhiyun regulator-name = "vccio_sd"; 559*4882a593Smuzhiyun regulator-state-mem { 560*4882a593Smuzhiyun regulator-on-in-suspend; 561*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 562*4882a593Smuzhiyun }; 563*4882a593Smuzhiyun }; 564*4882a593Smuzhiyun 565*4882a593Smuzhiyun vdd10_lcd: LDO_REG6 { 566*4882a593Smuzhiyun regulator-always-on; 567*4882a593Smuzhiyun regulator-boot-on; 568*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 569*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 570*4882a593Smuzhiyun regulator-name = "vdd10_lcd"; 571*4882a593Smuzhiyun regulator-state-mem { 572*4882a593Smuzhiyun regulator-off-in-suspend; 573*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 574*4882a593Smuzhiyun }; 575*4882a593Smuzhiyun }; 576*4882a593Smuzhiyun 577*4882a593Smuzhiyun vcc_18: LDO_REG7 { 578*4882a593Smuzhiyun regulator-always-on; 579*4882a593Smuzhiyun regulator-boot-on; 580*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 581*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 582*4882a593Smuzhiyun regulator-name = "vcc_18"; 583*4882a593Smuzhiyun regulator-state-mem { 584*4882a593Smuzhiyun regulator-on-in-suspend; 585*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 586*4882a593Smuzhiyun }; 587*4882a593Smuzhiyun }; 588*4882a593Smuzhiyun 589*4882a593Smuzhiyun vcc18_lcd: LDO_REG8 { 590*4882a593Smuzhiyun regulator-always-on; 591*4882a593Smuzhiyun regulator-boot-on; 592*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 593*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 594*4882a593Smuzhiyun regulator-name = "vcc18_lcd"; 595*4882a593Smuzhiyun regulator-state-mem { 596*4882a593Smuzhiyun regulator-off-in-suspend; 597*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 598*4882a593Smuzhiyun }; 599*4882a593Smuzhiyun }; 600*4882a593Smuzhiyun 601*4882a593Smuzhiyun vcc_sd: SWITCH_REG1 { 602*4882a593Smuzhiyun regulator-always-on; 603*4882a593Smuzhiyun regulator-boot-on; 604*4882a593Smuzhiyun regulator-name = "vcc_sd"; 605*4882a593Smuzhiyun regulator-state-mem { 606*4882a593Smuzhiyun regulator-on-in-suspend; 607*4882a593Smuzhiyun }; 608*4882a593Smuzhiyun }; 609*4882a593Smuzhiyun 610*4882a593Smuzhiyun vcc_lan: SWITCH_REG2 { 611*4882a593Smuzhiyun regulator-always-on; 612*4882a593Smuzhiyun regulator-boot-on; 613*4882a593Smuzhiyun regulator-name = "vcc_lan"; 614*4882a593Smuzhiyun regulator-state-mem { 615*4882a593Smuzhiyun regulator-off-in-suspend; 616*4882a593Smuzhiyun }; 617*4882a593Smuzhiyun }; 618*4882a593Smuzhiyun }; 619*4882a593Smuzhiyun }; 620*4882a593Smuzhiyun 621*4882a593Smuzhiyun}; 622*4882a593Smuzhiyun 623*4882a593Smuzhiyun&i2c1 { 624*4882a593Smuzhiyun status = "okay"; 625*4882a593Smuzhiyun 626*4882a593Smuzhiyun rt5640: rt5640@1c { 627*4882a593Smuzhiyun status = "okay"; 628*4882a593Smuzhiyun #sound-dai-cells = <0>; 629*4882a593Smuzhiyun compatible = "realtek,rt5640"; 630*4882a593Smuzhiyun reg = <0x1c>; 631*4882a593Smuzhiyun clocks = <&cru SCLK_I2S_8CH_OUT>; 632*4882a593Smuzhiyun clock-names = "mclk"; 633*4882a593Smuzhiyun realtek,in1-differential; 634*4882a593Smuzhiyun /* spk-con-gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>; */ 635*4882a593Smuzhiyun pinctrl-names = "default"; 636*4882a593Smuzhiyun pinctrl-0 = <&i2s_8ch_mclk>; 637*4882a593Smuzhiyun }; 638*4882a593Smuzhiyun 639*4882a593Smuzhiyun mpu6500_acc: mpu_acc@68 { 640*4882a593Smuzhiyun status = "okay"; 641*4882a593Smuzhiyun compatible = "mpu6500_acc"; 642*4882a593Smuzhiyun pinctrl-names = "default"; 643*4882a593Smuzhiyun pinctrl-0 = <&mpu6500_irq_gpio>; 644*4882a593Smuzhiyun reg = <0x68>; 645*4882a593Smuzhiyun irq-gpio = <&gpio2 17 IRQ_TYPE_LEVEL_LOW>; 646*4882a593Smuzhiyun irq_enable = <0>; 647*4882a593Smuzhiyun poll_delay_ms = <30>; 648*4882a593Smuzhiyun type = <SENSOR_TYPE_ACCEL>; 649*4882a593Smuzhiyun power-off-in-suspend = <1>; 650*4882a593Smuzhiyun layout = <5>; 651*4882a593Smuzhiyun 652*4882a593Smuzhiyun }; 653*4882a593Smuzhiyun 654*4882a593Smuzhiyun mpu6500_gyro: mpu_gyro@68 { 655*4882a593Smuzhiyun status = "okay"; 656*4882a593Smuzhiyun compatible = "mpu6500_gyro"; 657*4882a593Smuzhiyun reg = <0x68>; 658*4882a593Smuzhiyun irq_enable = <0>; 659*4882a593Smuzhiyun poll_delay_ms = <30>; 660*4882a593Smuzhiyun type = <SENSOR_TYPE_GYROSCOPE>; 661*4882a593Smuzhiyun power-off-in-suspend = <1>; 662*4882a593Smuzhiyun layout = <5>; 663*4882a593Smuzhiyun }; 664*4882a593Smuzhiyun 665*4882a593Smuzhiyun ak8963_compass: ak8963_compass@d { 666*4882a593Smuzhiyun status = "okay"; 667*4882a593Smuzhiyun compatible = "ak8963"; 668*4882a593Smuzhiyun pinctrl-names = "default"; 669*4882a593Smuzhiyun pinctrl-0 = <&ak8963_irq_gpio>; 670*4882a593Smuzhiyun reg = <0x0d>; 671*4882a593Smuzhiyun type = <SENSOR_TYPE_COMPASS>; 672*4882a593Smuzhiyun irq-gpio = <&gpio2 18 IRQ_TYPE_EDGE_RISING>; 673*4882a593Smuzhiyun irq_enable = <0>; 674*4882a593Smuzhiyun poll_delay_ms = <30>; 675*4882a593Smuzhiyun layout = <7>; 676*4882a593Smuzhiyun }; 677*4882a593Smuzhiyun}; 678*4882a593Smuzhiyun 679*4882a593Smuzhiyun&i2c2 { 680*4882a593Smuzhiyun status = "okay"; 681*4882a593Smuzhiyun 682*4882a593Smuzhiyun gslx680@40 { 683*4882a593Smuzhiyun compatible = "gslX6801"; 684*4882a593Smuzhiyun reg = <0x40>; 685*4882a593Smuzhiyun screen_max_x = <1920>; 686*4882a593Smuzhiyun screen_max_y = <1200>; 687*4882a593Smuzhiyun power-supply = <&vcc_lcd>; 688*4882a593Smuzhiyun touch-gpio = <&gpio0 12 IRQ_TYPE_LEVEL_LOW>; 689*4882a593Smuzhiyun reset-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; 690*4882a593Smuzhiyun status = "okay"; 691*4882a593Smuzhiyun }; 692*4882a593Smuzhiyun 693*4882a593Smuzhiyun}; 694*4882a593Smuzhiyun 695*4882a593Smuzhiyun&i2c3 { 696*4882a593Smuzhiyun status = "okay"; 697*4882a593Smuzhiyun}; 698*4882a593Smuzhiyun 699*4882a593Smuzhiyun&i2s_8ch { 700*4882a593Smuzhiyun status = "okay"; 701*4882a593Smuzhiyun rockchip,i2s-broken-burst-len; 702*4882a593Smuzhiyun rockchip,playback-channels = <8>; 703*4882a593Smuzhiyun rockchip,capture-channels = <2>; 704*4882a593Smuzhiyun #sound-dai-cells = <0>; 705*4882a593Smuzhiyun pinctrl-names = "default"; 706*4882a593Smuzhiyun pinctrl-0 = <&i2s_2ch_bus>; 707*4882a593Smuzhiyun}; 708*4882a593Smuzhiyun 709*4882a593Smuzhiyun&io_domains { 710*4882a593Smuzhiyun status = "okay"; 711*4882a593Smuzhiyun 712*4882a593Smuzhiyun audio-supply = <&vcca_18>; 713*4882a593Smuzhiyun dvp-supply = <&vcc_18>; 714*4882a593Smuzhiyun flash0-supply = <&vcc18_flash>; 715*4882a593Smuzhiyun gpio30-supply = <&vcc_io>; 716*4882a593Smuzhiyun gpio1830-supply = <&vcc_io>; 717*4882a593Smuzhiyun sdcard-supply = <&vccio_sd>; 718*4882a593Smuzhiyun wifi-supply = <&vcc_io>; 719*4882a593Smuzhiyun}; 720*4882a593Smuzhiyun 721*4882a593Smuzhiyun&pmu_io_domains { 722*4882a593Smuzhiyun status = "okay"; 723*4882a593Smuzhiyun 724*4882a593Smuzhiyun pmu-supply = <&vcc_io>; 725*4882a593Smuzhiyun vop-supply = <&vcca_33>; 726*4882a593Smuzhiyun}; 727*4882a593Smuzhiyun 728*4882a593Smuzhiyun&pwm0 { 729*4882a593Smuzhiyun status = "okay"; 730*4882a593Smuzhiyun}; 731*4882a593Smuzhiyun 732*4882a593Smuzhiyun&pwm3 { 733*4882a593Smuzhiyun status = "okay"; 734*4882a593Smuzhiyun}; 735*4882a593Smuzhiyun 736*4882a593Smuzhiyun&uart0 { 737*4882a593Smuzhiyun pinctrl-names = "default"; 738*4882a593Smuzhiyun pinctrl-0 = <&uart0_xfer &uart0_cts>; 739*4882a593Smuzhiyun status = "okay"; 740*4882a593Smuzhiyun}; 741*4882a593Smuzhiyun 742*4882a593Smuzhiyun&uart2 { 743*4882a593Smuzhiyun status = "disabled"; 744*4882a593Smuzhiyun}; 745*4882a593Smuzhiyun 746*4882a593Smuzhiyun&saradc { 747*4882a593Smuzhiyun status = "okay"; 748*4882a593Smuzhiyun}; 749*4882a593Smuzhiyun 750*4882a593Smuzhiyun&u2phy { 751*4882a593Smuzhiyun status = "okay"; 752*4882a593Smuzhiyun 753*4882a593Smuzhiyun u2phy_otg: otg-port { 754*4882a593Smuzhiyun status = "okay"; 755*4882a593Smuzhiyun vbus-supply = <&vcc_otg_vbus>; 756*4882a593Smuzhiyun }; 757*4882a593Smuzhiyun 758*4882a593Smuzhiyun u2phy_host: host-port { 759*4882a593Smuzhiyun status = "okay"; 760*4882a593Smuzhiyun }; 761*4882a593Smuzhiyun}; 762*4882a593Smuzhiyun 763*4882a593Smuzhiyun&usb_host0_ehci { 764*4882a593Smuzhiyun status = "okay"; 765*4882a593Smuzhiyun}; 766*4882a593Smuzhiyun 767*4882a593Smuzhiyun&usb_host0_ohci { 768*4882a593Smuzhiyun status = "okay"; 769*4882a593Smuzhiyun}; 770*4882a593Smuzhiyun 771*4882a593Smuzhiyun&edp { 772*4882a593Smuzhiyun status = "disabled"; 773*4882a593Smuzhiyun force-hpd; 774*4882a593Smuzhiyun 775*4882a593Smuzhiyun ports { 776*4882a593Smuzhiyun port@1 { 777*4882a593Smuzhiyun reg = <1>; 778*4882a593Smuzhiyun 779*4882a593Smuzhiyun edp_out: endpoint { 780*4882a593Smuzhiyun remote-endpoint = <&panel_in>; 781*4882a593Smuzhiyun }; 782*4882a593Smuzhiyun }; 783*4882a593Smuzhiyun }; 784*4882a593Smuzhiyun}; 785*4882a593Smuzhiyun 786*4882a593Smuzhiyun&dsi { 787*4882a593Smuzhiyun status = "okay"; 788*4882a593Smuzhiyun 789*4882a593Smuzhiyun panel@0 { 790*4882a593Smuzhiyun compatible = "sitronix,st7703", "simple-panel-dsi"; 791*4882a593Smuzhiyun reg = <0>; 792*4882a593Smuzhiyun backlight = <&backlight>; 793*4882a593Smuzhiyun power-supply = <&vcc_lcd>; 794*4882a593Smuzhiyun prepare-delay-ms = <2>; 795*4882a593Smuzhiyun reset-delay-ms = <1>; 796*4882a593Smuzhiyun init-delay-ms = <20>; 797*4882a593Smuzhiyun enable-delay-ms = <120>; 798*4882a593Smuzhiyun disable-delay-ms = <50>; 799*4882a593Smuzhiyun unprepare-delay-ms = <20>; 800*4882a593Smuzhiyun 801*4882a593Smuzhiyun width-mm = <68>; 802*4882a593Smuzhiyun height-mm = <121>; 803*4882a593Smuzhiyun 804*4882a593Smuzhiyun dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 805*4882a593Smuzhiyun MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; 806*4882a593Smuzhiyun dsi,format = <MIPI_DSI_FMT_RGB888>; 807*4882a593Smuzhiyun dsi,lanes = <4>; 808*4882a593Smuzhiyun 809*4882a593Smuzhiyun display-timings { 810*4882a593Smuzhiyun native-mode = <&st7703_timing>; 811*4882a593Smuzhiyun 812*4882a593Smuzhiyun st7703_timing: timing0 { 813*4882a593Smuzhiyun clock-frequency = <160000000>; 814*4882a593Smuzhiyun hactive = <1200>; 815*4882a593Smuzhiyun vactive = <1920>; 816*4882a593Smuzhiyun hback-porch = <60>; 817*4882a593Smuzhiyun hfront-porch = <80>; 818*4882a593Smuzhiyun vback-porch = <25>; 819*4882a593Smuzhiyun vfront-porch = <35>; 820*4882a593Smuzhiyun hsync-len = <1>; 821*4882a593Smuzhiyun vsync-len = <1>; 822*4882a593Smuzhiyun hsync-active = <0>; 823*4882a593Smuzhiyun vsync-active = <0>; 824*4882a593Smuzhiyun de-active = <0>; 825*4882a593Smuzhiyun pixelclk-active = <0>; 826*4882a593Smuzhiyun }; 827*4882a593Smuzhiyun }; 828*4882a593Smuzhiyun 829*4882a593Smuzhiyun ports { 830*4882a593Smuzhiyun #address-cells = <1>; 831*4882a593Smuzhiyun #size-cells = <0>; 832*4882a593Smuzhiyun 833*4882a593Smuzhiyun port@0 { 834*4882a593Smuzhiyun reg = <0>; 835*4882a593Smuzhiyun panel_in_dsi: endpoint { 836*4882a593Smuzhiyun remote-endpoint = <&dsi_out_panel>; 837*4882a593Smuzhiyun }; 838*4882a593Smuzhiyun }; 839*4882a593Smuzhiyun }; 840*4882a593Smuzhiyun }; 841*4882a593Smuzhiyun 842*4882a593Smuzhiyun ports { 843*4882a593Smuzhiyun #address-cells = <1>; 844*4882a593Smuzhiyun #size-cells = <0>; 845*4882a593Smuzhiyun 846*4882a593Smuzhiyun port@1 { 847*4882a593Smuzhiyun reg = <1>; 848*4882a593Smuzhiyun dsi_out_panel: endpoint { 849*4882a593Smuzhiyun remote-endpoint = <&panel_in_dsi>; 850*4882a593Smuzhiyun }; 851*4882a593Smuzhiyun }; 852*4882a593Smuzhiyun }; 853*4882a593Smuzhiyun}; 854*4882a593Smuzhiyun 855*4882a593Smuzhiyun&video_phy { 856*4882a593Smuzhiyun status = "okay"; 857*4882a593Smuzhiyun}; 858*4882a593Smuzhiyun 859*4882a593Smuzhiyun&route_dsi { 860*4882a593Smuzhiyun status = "okay"; 861*4882a593Smuzhiyun}; 862*4882a593Smuzhiyun 863*4882a593Smuzhiyun&tsadc { 864*4882a593Smuzhiyun tsadc-supply = <&vdd_cpu>; 865*4882a593Smuzhiyun status = "okay"; 866*4882a593Smuzhiyun}; 867*4882a593Smuzhiyun 868*4882a593Smuzhiyun&gmac { 869*4882a593Smuzhiyun phy-supply = <&vcc_phy>; 870*4882a593Smuzhiyun phy-mode = "rgmii"; 871*4882a593Smuzhiyun clock_in_out = "input"; 872*4882a593Smuzhiyun snps,reset-gpio = <&gpio3 11 GPIO_ACTIVE_LOW>; 873*4882a593Smuzhiyun snps,reset-active-low; 874*4882a593Smuzhiyun snps,reset-delays-us = <0 10000 50000>; 875*4882a593Smuzhiyun assigned-clocks = <&cru SCLK_MAC>; 876*4882a593Smuzhiyun assigned-clock-parents = <&ext_gmac>; 877*4882a593Smuzhiyun pinctrl-names = "default"; 878*4882a593Smuzhiyun pinctrl-0 = <&rgmii_pins>; 879*4882a593Smuzhiyun tx_delay = <0x28>; 880*4882a593Smuzhiyun rx_delay = <0x11>; 881*4882a593Smuzhiyun status = "okay"; 882*4882a593Smuzhiyun}; 883*4882a593Smuzhiyun 884*4882a593Smuzhiyun&hdmi { 885*4882a593Smuzhiyun #sound-dai-cells = <0>; 886*4882a593Smuzhiyun status = "okay"; 887*4882a593Smuzhiyun}; 888*4882a593Smuzhiyun 889*4882a593Smuzhiyun&route_hdmi { 890*4882a593Smuzhiyun status = "okay"; 891*4882a593Smuzhiyun}; 892*4882a593Smuzhiyun 893*4882a593Smuzhiyun&pinctrl { 894*4882a593Smuzhiyun camera { 895*4882a593Smuzhiyun camera_pwr: camera-pwr { 896*4882a593Smuzhiyun rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 897*4882a593Smuzhiyun }; 898*4882a593Smuzhiyun }; 899*4882a593Smuzhiyun 900*4882a593Smuzhiyun lcd { 901*4882a593Smuzhiyun lcd_pwr: lcd-pwr { 902*4882a593Smuzhiyun rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; 903*4882a593Smuzhiyun }; 904*4882a593Smuzhiyun }; 905*4882a593Smuzhiyun 906*4882a593Smuzhiyun headphone { 907*4882a593Smuzhiyun hp_det: hp-det { 908*4882a593Smuzhiyun rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; 909*4882a593Smuzhiyun }; 910*4882a593Smuzhiyun }; 911*4882a593Smuzhiyun 912*4882a593Smuzhiyun i2s { 913*4882a593Smuzhiyun i2s_2ch_bus: i2s-2ch-bus { 914*4882a593Smuzhiyun rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, 915*4882a593Smuzhiyun <2 RK_PB5 1 &pcfg_pull_none>, 916*4882a593Smuzhiyun <2 RK_PB6 1 &pcfg_pull_none>, 917*4882a593Smuzhiyun <2 RK_PB7 1 &pcfg_pull_none>, 918*4882a593Smuzhiyun <2 RK_PC0 1 &pcfg_pull_none>; 919*4882a593Smuzhiyun }; 920*4882a593Smuzhiyun }; 921*4882a593Smuzhiyun 922*4882a593Smuzhiyun pmic { 923*4882a593Smuzhiyun pmic_sleep: pmic-sleep { 924*4882a593Smuzhiyun rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; 925*4882a593Smuzhiyun }; 926*4882a593Smuzhiyun 927*4882a593Smuzhiyun pmic_int: pmic-int { 928*4882a593Smuzhiyun rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; 929*4882a593Smuzhiyun }; 930*4882a593Smuzhiyun }; 931*4882a593Smuzhiyun 932*4882a593Smuzhiyun mpu6500 { 933*4882a593Smuzhiyun mpu6500_irq_gpio: mpu6500-irq-gpio { 934*4882a593Smuzhiyun rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; 935*4882a593Smuzhiyun }; 936*4882a593Smuzhiyun }; 937*4882a593Smuzhiyun 938*4882a593Smuzhiyun ak8963 { 939*4882a593Smuzhiyun ak8963_irq_gpio: ak8963_irq_gpio { 940*4882a593Smuzhiyun rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; 941*4882a593Smuzhiyun }; 942*4882a593Smuzhiyun }; 943*4882a593Smuzhiyun 944*4882a593Smuzhiyun dc_det { 945*4882a593Smuzhiyun dc_irq_gpio: dc-irq-gpio { 946*4882a593Smuzhiyun rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; 947*4882a593Smuzhiyun }; 948*4882a593Smuzhiyun }; 949*4882a593Smuzhiyun 950*4882a593Smuzhiyun sdio-pwrseq { 951*4882a593Smuzhiyun wifi_enable_h: wifi-enable-h { 952*4882a593Smuzhiyun rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; 953*4882a593Smuzhiyun }; 954*4882a593Smuzhiyun }; 955*4882a593Smuzhiyun 956*4882a593Smuzhiyun usb { 957*4882a593Smuzhiyun otg_vbus_drv: otg-vbus-drv { 958*4882a593Smuzhiyun rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 959*4882a593Smuzhiyun }; 960*4882a593Smuzhiyun }; 961*4882a593Smuzhiyun 962*4882a593Smuzhiyun wireless-bluetooth { 963*4882a593Smuzhiyun uart0_rts_gpio: uart0-rts-gpio { 964*4882a593Smuzhiyun rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; 965*4882a593Smuzhiyun }; 966*4882a593Smuzhiyun }; 967*4882a593Smuzhiyun 968*4882a593Smuzhiyun rk-modem { 969*4882a593Smuzhiyun lte_vbat: lte-vbat { 970*4882a593Smuzhiyun rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; 971*4882a593Smuzhiyun }; 972*4882a593Smuzhiyun 973*4882a593Smuzhiyun lte_power_en: lte-power-en { 974*4882a593Smuzhiyun rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; 975*4882a593Smuzhiyun }; 976*4882a593Smuzhiyun 977*4882a593Smuzhiyun lte_reset: lte-reset { 978*4882a593Smuzhiyun rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; 979*4882a593Smuzhiyun }; 980*4882a593Smuzhiyun }; 981*4882a593Smuzhiyun}; 982*4882a593Smuzhiyun 983