xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm64/rockchip/rk1808-evb-x4-second.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/dts-v1/;
7*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h>
8*4882a593Smuzhiyun#include "rk1808-evb.dtsi"
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun/ {
11*4882a593Smuzhiyun	model = "Rockchip RK1808 EVB X4 Board";
12*4882a593Smuzhiyun	compatible = "rockchip,rk1808-evb-x4", "rockchip,rk1808";
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun	chosen {
15*4882a593Smuzhiyun		bootargs = "earlycon=uart8250,mmio32,0xff550000 console=ttyFIQ0 dump_initrd init=/init kpti=0";
16*4882a593Smuzhiyun	};
17*4882a593Smuzhiyun};
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun&adc_key {
20*4882a593Smuzhiyun	power-key {
21*4882a593Smuzhiyun		linux,code = <KEY_POWER>;
22*4882a593Smuzhiyun		label = "power key";
23*4882a593Smuzhiyun		press-threshold-microvolt = <18000>;
24*4882a593Smuzhiyun	};
25*4882a593Smuzhiyun};
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun/delete-node/ &backlight;
28*4882a593Smuzhiyun/delete-node/ &vcc1v8_dvp;
29*4882a593Smuzhiyun/delete-node/ &vdd1v5_dvp;
30*4882a593Smuzhiyun/delete-node/ &vcc2v8_dvp;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun&cif {
33*4882a593Smuzhiyun	status = "okay";
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun	port {
36*4882a593Smuzhiyun		cif_in: endpoint@0 {
37*4882a593Smuzhiyun			remote-endpoint = <&dphy_rx_out>;
38*4882a593Smuzhiyun			data-lanes = <1 2 3 4>;
39*4882a593Smuzhiyun		};
40*4882a593Smuzhiyun	};
41*4882a593Smuzhiyun};
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun&cif_mmu {
44*4882a593Smuzhiyun	status = "okay";
45*4882a593Smuzhiyun};
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun&cru {
48*4882a593Smuzhiyun	assigned-clocks =
49*4882a593Smuzhiyun		<&cru PLL_GPLL>, <&cru PLL_CPLL>,
50*4882a593Smuzhiyun		<&cru PLL_PPLL>, <&cru ARMCLK>,
51*4882a593Smuzhiyun		<&cru MSCLK_PERI>, <&cru LSCLK_PERI>,
52*4882a593Smuzhiyun		<&cru HSCLK_BUS_PRE>, <&cru MSCLK_BUS_PRE>,
53*4882a593Smuzhiyun		<&cru LSCLK_BUS_PRE>, <&cru DCLK_VOPRAW>;
54*4882a593Smuzhiyun	assigned-clock-rates =
55*4882a593Smuzhiyun		<1188000000>, <1000000000>,
56*4882a593Smuzhiyun		<100000000>, <816000000>,
57*4882a593Smuzhiyun		<200000000>, <100000000>,
58*4882a593Smuzhiyun		<300000000>, <200000000>,
59*4882a593Smuzhiyun		<100000000>, <80000000>;
60*4882a593Smuzhiyun};
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun&csi_tx {
63*4882a593Smuzhiyun	status = "okay";
64*4882a593Smuzhiyun	csi-tx-bypass-mode = <1>;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun	panel@0 {
67*4882a593Smuzhiyun		compatible = "simple-panel-dsi";
68*4882a593Smuzhiyun		reg = <0>;
69*4882a593Smuzhiyun		dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
70*4882a593Smuzhiyun			      MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET |
71*4882a593Smuzhiyun			      MIPI_DSI_CLOCK_NON_CONTINUOUS)>;
72*4882a593Smuzhiyun		dsi,format = <MIPI_CSI_FMT_RAW8>;
73*4882a593Smuzhiyun		dsi,lanes = <4>;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun		display-timings {
76*4882a593Smuzhiyun			native-mode = <&timing_1280x3_720>;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun			timing_1280x3_720: timing-1280x3-720 {
79*4882a593Smuzhiyun				clock-frequency = <80000000>;
80*4882a593Smuzhiyun				hactive = <3840>;
81*4882a593Smuzhiyun				vactive = <720>;
82*4882a593Smuzhiyun				hfront-porch = <1200>;
83*4882a593Smuzhiyun				hsync-len = <500>;
84*4882a593Smuzhiyun				hback-porch = <30>;
85*4882a593Smuzhiyun				vfront-porch = <40>;
86*4882a593Smuzhiyun				vsync-len = <20>;
87*4882a593Smuzhiyun				vback-porch = <40>;
88*4882a593Smuzhiyun				hsync-active = <0>;
89*4882a593Smuzhiyun				vsync-active = <0>;
90*4882a593Smuzhiyun				de-active = <0>;
91*4882a593Smuzhiyun				pixelclk-active = <0>;
92*4882a593Smuzhiyun			};
93*4882a593Smuzhiyun			timing_4k: timing-4k {
94*4882a593Smuzhiyun				clock-frequency = <250000000>;
95*4882a593Smuzhiyun				hactive = <3840>;
96*4882a593Smuzhiyun				vactive = <2160>;
97*4882a593Smuzhiyun				hfront-porch = <1500>;
98*4882a593Smuzhiyun				hsync-len = <500>;
99*4882a593Smuzhiyun				hback-porch = <30>;
100*4882a593Smuzhiyun				vfront-porch = <40>;
101*4882a593Smuzhiyun				vsync-len = <20>;
102*4882a593Smuzhiyun				vback-porch = <40>;
103*4882a593Smuzhiyun				hsync-active = <0>;
104*4882a593Smuzhiyun				vsync-active = <0>;
105*4882a593Smuzhiyun				de-active = <0>;
106*4882a593Smuzhiyun				pixelclk-active = <0>;
107*4882a593Smuzhiyun			};
108*4882a593Smuzhiyun			timing_4096: timing-4096 {
109*4882a593Smuzhiyun				clock-frequency = <100000000>;
110*4882a593Smuzhiyun				hactive = <4096>;
111*4882a593Smuzhiyun				vactive = <2048>;
112*4882a593Smuzhiyun				hfront-porch = <1500>;
113*4882a593Smuzhiyun				hsync-len = <500>;
114*4882a593Smuzhiyun				hback-porch = <30>;
115*4882a593Smuzhiyun				vfront-porch = <40>;
116*4882a593Smuzhiyun				vsync-len = <20>;
117*4882a593Smuzhiyun				vback-porch = <40>;
118*4882a593Smuzhiyun				hsync-active = <0>;
119*4882a593Smuzhiyun				vsync-active = <0>;
120*4882a593Smuzhiyun				de-active = <0>;
121*4882a593Smuzhiyun				pixelclk-active = <0>;
122*4882a593Smuzhiyun			};
123*4882a593Smuzhiyun			timing_1920x3_1080: timing-1920x3-1080 {
124*4882a593Smuzhiyun				clock-frequency = <250000000>;
125*4882a593Smuzhiyun				hactive = <5760>;
126*4882a593Smuzhiyun				vactive = <1080>;
127*4882a593Smuzhiyun				hfront-porch = <1500>;
128*4882a593Smuzhiyun				hsync-len = <70>;
129*4882a593Smuzhiyun				hback-porch = <30>;
130*4882a593Smuzhiyun				vfront-porch = <40>;
131*4882a593Smuzhiyun				vsync-len = <20>;
132*4882a593Smuzhiyun				vback-porch = <40>;
133*4882a593Smuzhiyun				hsync-active = <0>;
134*4882a593Smuzhiyun				vsync-active = <0>;
135*4882a593Smuzhiyun				de-active = <0>;
136*4882a593Smuzhiyun				pixelclk-active = <0>;
137*4882a593Smuzhiyun			};
138*4882a593Smuzhiyun		};
139*4882a593Smuzhiyun	};
140*4882a593Smuzhiyun};
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun&display_subsystem {
143*4882a593Smuzhiyun	status = "okay";
144*4882a593Smuzhiyun};
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun&emmc {
147*4882a593Smuzhiyun	status = "disabled";
148*4882a593Smuzhiyun};
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun&gmac {
151*4882a593Smuzhiyun	status = "disabled";
152*4882a593Smuzhiyun};
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun&i2c0 {
155*4882a593Smuzhiyun	status = "okay";
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun	vcamera@30 {
158*4882a593Smuzhiyun		compatible = "rockchip,virtual-camera";
159*4882a593Smuzhiyun		reg = <0x30>;
160*4882a593Smuzhiyun		width = <3840>;
161*4882a593Smuzhiyun		height = <720>;
162*4882a593Smuzhiyun		bus-format = <MEDIA_BUS_FMT_SBGGR8_1X8>;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun		port {
165*4882a593Smuzhiyun			vcamera_out: endpoint {
166*4882a593Smuzhiyun				remote-endpoint = <&dphy_rx_in>;
167*4882a593Smuzhiyun				link-frequencies = /bits/ 64 <320000000>;
168*4882a593Smuzhiyun			};
169*4882a593Smuzhiyun		};
170*4882a593Smuzhiyun	};
171*4882a593Smuzhiyun};
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun&i2c1 {
174*4882a593Smuzhiyun	status = "disabled";
175*4882a593Smuzhiyun};
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun&i2c4 {
178*4882a593Smuzhiyun	status = "disabled";
179*4882a593Smuzhiyun};
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun&mipi_dphy {
182*4882a593Smuzhiyun	status = "okay";
183*4882a593Smuzhiyun};
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun&mipi_dphy_rx {
186*4882a593Smuzhiyun	status = "okay";
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun	ports {
189*4882a593Smuzhiyun		#address-cells = <1>;
190*4882a593Smuzhiyun		#size-cells = <0>;
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun		port@0 {
193*4882a593Smuzhiyun			reg = <0>;
194*4882a593Smuzhiyun			#address-cells = <1>;
195*4882a593Smuzhiyun			#size-cells = <0>;
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun			dphy_rx_in: endpoint@1 {
198*4882a593Smuzhiyun				reg = <1>;
199*4882a593Smuzhiyun				remote-endpoint = <&vcamera_out>;
200*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
201*4882a593Smuzhiyun			};
202*4882a593Smuzhiyun		};
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun		port@1 {
205*4882a593Smuzhiyun			reg = <1>;
206*4882a593Smuzhiyun			#address-cells = <1>;
207*4882a593Smuzhiyun			#size-cells = <0>;
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun			dphy_rx_out: endpoint@0 {
210*4882a593Smuzhiyun				reg = <0>;
211*4882a593Smuzhiyun				remote-endpoint = <&cif_in>;
212*4882a593Smuzhiyun			};
213*4882a593Smuzhiyun		};
214*4882a593Smuzhiyun	};
215*4882a593Smuzhiyun};
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun&rk809_codec {
218*4882a593Smuzhiyun	status = "disabled";
219*4882a593Smuzhiyun};
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun&rk_rga {
222*4882a593Smuzhiyun	status = "okay";
223*4882a593Smuzhiyun};
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun&route_csi {
226*4882a593Smuzhiyun	status = "disabled";
227*4882a593Smuzhiyun};
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun&sdmmc {
230*4882a593Smuzhiyun	status = "disabled";
231*4882a593Smuzhiyun};
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun&sdio {
234*4882a593Smuzhiyun	status = "disabled";
235*4882a593Smuzhiyun};
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun&sfc {
238*4882a593Smuzhiyun	status = "okay";
239*4882a593Smuzhiyun};
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun&uart4 {
242*4882a593Smuzhiyun	status = "disabled";
243*4882a593Smuzhiyun};
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun&wireless_bluetooth {
246*4882a593Smuzhiyun	status = "disabled";
247*4882a593Smuzhiyun};
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun&wireless_wlan {
250*4882a593Smuzhiyun	status = "disabled";
251*4882a593Smuzhiyun};
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun&tsadc {
254*4882a593Smuzhiyun	rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
255*4882a593Smuzhiyun	rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
256*4882a593Smuzhiyun	pinctrl-names = "init", "default";
257*4882a593Smuzhiyun	pinctrl-0 = <&tsadc_otp_gpio>;
258*4882a593Smuzhiyun	pinctrl-1 = <&tsadc_otp_out>;
259*4882a593Smuzhiyun	status = "okay";
260*4882a593Smuzhiyun};
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun&vop_raw {
263*4882a593Smuzhiyun	status = "okay";
264*4882a593Smuzhiyun};
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun&vopr_mmu {
267*4882a593Smuzhiyun	status = "okay";
268*4882a593Smuzhiyun};
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun&vpu_mmu {
271*4882a593Smuzhiyun	status = "okay";
272*4882a593Smuzhiyun};
273