xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm64/rockchip/px30-evb-ddr3-v10.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2017-2019 Fuzhou Rockchip Electronics Co., Ltd
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
7*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h>
8*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
9*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h>
10*4882a593Smuzhiyun#include <dt-bindings/sensor-dev.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun/ {
13*4882a593Smuzhiyun	adc-keys {
14*4882a593Smuzhiyun		compatible = "adc-keys";
15*4882a593Smuzhiyun		io-channels = <&saradc 2>;
16*4882a593Smuzhiyun		io-channel-names = "buttons";
17*4882a593Smuzhiyun		poll-interval = <100>;
18*4882a593Smuzhiyun		keyup-threshold-microvolt = <1800000>;
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun		esc-key {
21*4882a593Smuzhiyun			linux,code = <KEY_ESC>;
22*4882a593Smuzhiyun			label = "esc";
23*4882a593Smuzhiyun			press-threshold-microvolt = <1310000>;
24*4882a593Smuzhiyun		};
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun		home-key {
27*4882a593Smuzhiyun			linux,code = <KEY_HOME>;
28*4882a593Smuzhiyun			label = "home";
29*4882a593Smuzhiyun			press-threshold-microvolt = <624000>;
30*4882a593Smuzhiyun		};
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun		menu-key {
33*4882a593Smuzhiyun			linux,code = <KEY_MENU>;
34*4882a593Smuzhiyun			label = "menu";
35*4882a593Smuzhiyun			press-threshold-microvolt = <987000>;
36*4882a593Smuzhiyun		};
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun		vol-down-key {
39*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEDOWN>;
40*4882a593Smuzhiyun			label = "volume down";
41*4882a593Smuzhiyun			press-threshold-microvolt = <300000>;
42*4882a593Smuzhiyun		};
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun		vol-up-key {
45*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
46*4882a593Smuzhiyun			label = "volume up";
47*4882a593Smuzhiyun			press-threshold-microvolt = <17000>;
48*4882a593Smuzhiyun		};
49*4882a593Smuzhiyun	};
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun	backlight: backlight {
52*4882a593Smuzhiyun		compatible = "pwm-backlight";
53*4882a593Smuzhiyun		pwms = <&pwm1 0 25000 0>;
54*4882a593Smuzhiyun		brightness-levels = <
55*4882a593Smuzhiyun			  0   1   2   3   4   5   6   7
56*4882a593Smuzhiyun			  8   9  10  11  12  13  14  15
57*4882a593Smuzhiyun			 16  17  18  19  20  21  22  23
58*4882a593Smuzhiyun			 24  25  26  27  28  29  30  31
59*4882a593Smuzhiyun			 32  33  34  35  36  37  38  39
60*4882a593Smuzhiyun			 40  41  42  43  44  45  46  47
61*4882a593Smuzhiyun			 48  49  50  51  52  53  54  55
62*4882a593Smuzhiyun			 56  57  58  59  60  61  62  63
63*4882a593Smuzhiyun			 64  65  66  67  68  69  70  71
64*4882a593Smuzhiyun			 72  73  74  75  76  77  78  79
65*4882a593Smuzhiyun			 80  81  82  83  84  85  86  87
66*4882a593Smuzhiyun			 88  89  90  91  92  93  94  95
67*4882a593Smuzhiyun			 96  97  98  99 100 101 102 103
68*4882a593Smuzhiyun			104 105 106 107 108 109 110 111
69*4882a593Smuzhiyun			112 113 114 115 116 117 118 119
70*4882a593Smuzhiyun			120 121 122 123 124 125 126 127
71*4882a593Smuzhiyun			128 129 130 131 132 133 134 135
72*4882a593Smuzhiyun			136 137 138 139 140 141 142 143
73*4882a593Smuzhiyun			144 145 146 147 148 149 150 151
74*4882a593Smuzhiyun			152 153 154 155 156 157 158 159
75*4882a593Smuzhiyun			160 161 162 163 164 165 166 167
76*4882a593Smuzhiyun			168 169 170 171 172 173 174 175
77*4882a593Smuzhiyun			176 177 178 179 180 181 182 183
78*4882a593Smuzhiyun			184 185 186 187 188 189 190 191
79*4882a593Smuzhiyun			192 193 194 195 196 197 198 199
80*4882a593Smuzhiyun			200 201 202 203 204 205 206 207
81*4882a593Smuzhiyun			208 209 210 211 212 213 214 215
82*4882a593Smuzhiyun			216 217 218 219 220 221 222 223
83*4882a593Smuzhiyun			224 225 226 227 228 229 230 231
84*4882a593Smuzhiyun			232 233 234 235 236 237 238 239
85*4882a593Smuzhiyun			240 241 242 243 244 245 246 247
86*4882a593Smuzhiyun			248 249 250 251 252 253 254 255>;
87*4882a593Smuzhiyun		default-brightness-level = <200>;
88*4882a593Smuzhiyun	};
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun	charge-animation {
91*4882a593Smuzhiyun		compatible = "rockchip,uboot-charge";
92*4882a593Smuzhiyun		rockchip,uboot-charge-on = <0>;
93*4882a593Smuzhiyun		rockchip,android-charge-on = <1>;
94*4882a593Smuzhiyun		rockchip,uboot-low-power-voltage = <3500>;
95*4882a593Smuzhiyun		rockchip,screen-on-voltage = <3600>;
96*4882a593Smuzhiyun		status = "okay";
97*4882a593Smuzhiyun	};
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun	rk809_sound: rk809-sound {
100*4882a593Smuzhiyun		status = "okay";
101*4882a593Smuzhiyun		compatible = "rockchip,multicodecs-card";
102*4882a593Smuzhiyun		rockchip,card-name = "rockchip-rk809";
103*4882a593Smuzhiyun		hp-det-gpio = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>;
104*4882a593Smuzhiyun		io-channels = <&saradc 1>;
105*4882a593Smuzhiyun		io-channel-names = "adc-detect";
106*4882a593Smuzhiyun		keyup-threshold-microvolt = <1800000>;
107*4882a593Smuzhiyun		poll-interval = <100>;
108*4882a593Smuzhiyun		rockchip,format = "i2s";
109*4882a593Smuzhiyun		rockchip,mclk-fs = <256>;
110*4882a593Smuzhiyun		rockchip,cpu = <&i2s1_2ch>;
111*4882a593Smuzhiyun		rockchip,codec = <&rk809_codec>;
112*4882a593Smuzhiyun		pinctrl-names = "default";
113*4882a593Smuzhiyun		pinctrl-0 = <&hp_det>;
114*4882a593Smuzhiyun		play-pause-key {
115*4882a593Smuzhiyun			label = "playpause";
116*4882a593Smuzhiyun			linux,code = <KEY_PLAYPAUSE>;
117*4882a593Smuzhiyun			press-threshold-microvolt = <2000>;
118*4882a593Smuzhiyun		};
119*4882a593Smuzhiyun	};
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun	sdio_pwrseq: sdio-pwrseq {
122*4882a593Smuzhiyun		compatible = "mmc-pwrseq-simple";
123*4882a593Smuzhiyun		/*clocks = <&rk809 1>;*/
124*4882a593Smuzhiyun		/*clock-names = "ext_clock";*/
125*4882a593Smuzhiyun		pinctrl-names = "default";
126*4882a593Smuzhiyun		pinctrl-0 = <&wifi_enable_h>;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun		/*
129*4882a593Smuzhiyun		 * On the module itself this is one of these (depending
130*4882a593Smuzhiyun		 * on the actual card populated):
131*4882a593Smuzhiyun		 * - SDIO_RESET_L_WL_REG_ON
132*4882a593Smuzhiyun		 * - PDN (power down when low)
133*4882a593Smuzhiyun		 */
134*4882a593Smuzhiyun		reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */
135*4882a593Smuzhiyun	};
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun	test-power {
138*4882a593Smuzhiyun		status = "okay";
139*4882a593Smuzhiyun	};
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun	vcc_phy: vcc-phy-regulator {
142*4882a593Smuzhiyun		compatible = "regulator-fixed";
143*4882a593Smuzhiyun		regulator-name = "vcc_phy";
144*4882a593Smuzhiyun		regulator-always-on;
145*4882a593Smuzhiyun		regulator-boot-on;
146*4882a593Smuzhiyun	};
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun	vcc5v0_sys: vccsys {
149*4882a593Smuzhiyun		compatible = "regulator-fixed";
150*4882a593Smuzhiyun		regulator-name = "vcc5v0_sys";
151*4882a593Smuzhiyun		regulator-always-on;
152*4882a593Smuzhiyun		regulator-boot-on;
153*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
154*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
155*4882a593Smuzhiyun	};
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun	wireless-wlan {
158*4882a593Smuzhiyun		compatible = "wlan-platdata";
159*4882a593Smuzhiyun		wifi_chip_type = "AP6210";
160*4882a593Smuzhiyun		WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>;
161*4882a593Smuzhiyun		WIFI,poweren_gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
162*4882a593Smuzhiyun		status = "okay";
163*4882a593Smuzhiyun	};
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun	wireless_bluetooth: wireless-bluetooth {
166*4882a593Smuzhiyun		compatible = "bluetooth-platdata";
167*4882a593Smuzhiyun		clocks = <&rk809 1>;
168*4882a593Smuzhiyun		clock-names = "ext_clock";
169*4882a593Smuzhiyun		uart_rts_gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>;
170*4882a593Smuzhiyun		pinctrl-names = "default","rts_gpio";
171*4882a593Smuzhiyun		pinctrl-0 = <&uart1_rts>;
172*4882a593Smuzhiyun		pinctrl-1 = <&uart1_rts_gpio>;
173*4882a593Smuzhiyun		BT,reset_gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
174*4882a593Smuzhiyun		BT,wake_gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
175*4882a593Smuzhiyun		BT,wake_host_irq = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
176*4882a593Smuzhiyun		status = "okay";
177*4882a593Smuzhiyun	};
178*4882a593Smuzhiyun};
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun&display_subsystem {
181*4882a593Smuzhiyun	status = "okay";
182*4882a593Smuzhiyun};
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun&dsi_in_vopb {
185*4882a593Smuzhiyun	status = "okay";
186*4882a593Smuzhiyun};
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun&dsi_in_vopl {
189*4882a593Smuzhiyun	status = "disabled";
190*4882a593Smuzhiyun};
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun&route_dsi {
193*4882a593Smuzhiyun	connect = <&vopb_out_dsi>;
194*4882a593Smuzhiyun	status = "okay";
195*4882a593Smuzhiyun};
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun&bus_apll {
198*4882a593Smuzhiyun	bus-supply = <&vdd_logic>;
199*4882a593Smuzhiyun	status = "okay";
200*4882a593Smuzhiyun};
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun&cpu0 {
203*4882a593Smuzhiyun	cpu-supply = <&vdd_arm>;
204*4882a593Smuzhiyun};
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun&dfi {
207*4882a593Smuzhiyun	status = "okay";
208*4882a593Smuzhiyun};
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun&dmc {
211*4882a593Smuzhiyun	center-supply = <&vdd_logic>;
212*4882a593Smuzhiyun	status = "okay";
213*4882a593Smuzhiyun};
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun&emmc {
216*4882a593Smuzhiyun	bus-width = <8>;
217*4882a593Smuzhiyun	cap-mmc-highspeed;
218*4882a593Smuzhiyun	mmc-hs200-1_8v;
219*4882a593Smuzhiyun	no-sdio;
220*4882a593Smuzhiyun	no-sd;
221*4882a593Smuzhiyun	disable-wp;
222*4882a593Smuzhiyun	non-removable;
223*4882a593Smuzhiyun	num-slots = <1>;
224*4882a593Smuzhiyun	status = "okay";
225*4882a593Smuzhiyun};
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun&gmac {
228*4882a593Smuzhiyun	phy-supply = <&vcc_phy>;
229*4882a593Smuzhiyun	clock_in_out = "input";
230*4882a593Smuzhiyun	assigned-clocks = <&cru SCLK_GMAC>;
231*4882a593Smuzhiyun	assigned-clock-parents = <&gmac_clkin>;
232*4882a593Smuzhiyun	pinctrl-names = "default";
233*4882a593Smuzhiyun	pinctrl-0 = <&rmii_pins &mac_refclk>;
234*4882a593Smuzhiyun	snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>;
235*4882a593Smuzhiyun	snps,reset-active-low;
236*4882a593Smuzhiyun	snps,reset-delays-us = <0 50000 50000>;
237*4882a593Smuzhiyun	status = "okay";
238*4882a593Smuzhiyun};
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun&gpu {
241*4882a593Smuzhiyun	mali-supply = <&vdd_logic>;
242*4882a593Smuzhiyun	status = "okay";
243*4882a593Smuzhiyun};
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun&i2c0 {
246*4882a593Smuzhiyun	status = "okay";
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun	rk809: pmic@20 {
249*4882a593Smuzhiyun		compatible = "rockchip,rk809";
250*4882a593Smuzhiyun		reg = <0x20>;
251*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
252*4882a593Smuzhiyun		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
253*4882a593Smuzhiyun		pinctrl-names = "default", "pmic-sleep",
254*4882a593Smuzhiyun				"pmic-power-off", "pmic-reset";
255*4882a593Smuzhiyun		pinctrl-0 = <&pmic_int>;
256*4882a593Smuzhiyun		pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
257*4882a593Smuzhiyun		pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
258*4882a593Smuzhiyun		pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>;
259*4882a593Smuzhiyun		rockchip,system-power-controller;
260*4882a593Smuzhiyun		wakeup-source;
261*4882a593Smuzhiyun		#clock-cells = <1>;
262*4882a593Smuzhiyun		clock-output-names = "rk808-clkout1", "rk808-clkout2";
263*4882a593Smuzhiyun		//fb-inner-reg-idxs = <2>;
264*4882a593Smuzhiyun		/* 1: rst regs (default in codes), 0: rst the pmic */
265*4882a593Smuzhiyun		pmic-reset-func = <1>;
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun		vcc1-supply = <&vcc5v0_sys>;
268*4882a593Smuzhiyun		vcc2-supply = <&vcc5v0_sys>;
269*4882a593Smuzhiyun		vcc3-supply = <&vcc5v0_sys>;
270*4882a593Smuzhiyun		vcc4-supply = <&vcc5v0_sys>;
271*4882a593Smuzhiyun		vcc5-supply = <&vcc3v3_sys>;
272*4882a593Smuzhiyun		vcc6-supply = <&vcc3v3_sys>;
273*4882a593Smuzhiyun		vcc7-supply = <&vcc3v3_sys>;
274*4882a593Smuzhiyun		vcc8-supply = <&vcc3v3_sys>;
275*4882a593Smuzhiyun		vcc9-supply = <&vcc5v0_sys>;
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun		pwrkey {
278*4882a593Smuzhiyun			status = "okay";
279*4882a593Smuzhiyun		};
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun		pinctrl_rk8xx: pinctrl_rk8xx {
282*4882a593Smuzhiyun			gpio-controller;
283*4882a593Smuzhiyun			#gpio-cells = <2>;
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun			rk817_slppin_null: rk817_slppin_null {
286*4882a593Smuzhiyun				pins = "gpio_slp";
287*4882a593Smuzhiyun				function = "pin_fun0";
288*4882a593Smuzhiyun			};
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun			rk817_slppin_slp: rk817_slppin_slp {
291*4882a593Smuzhiyun				pins = "gpio_slp";
292*4882a593Smuzhiyun				function = "pin_fun1";
293*4882a593Smuzhiyun			};
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun			rk817_slppin_pwrdn: rk817_slppin_pwrdn {
296*4882a593Smuzhiyun				pins = "gpio_slp";
297*4882a593Smuzhiyun				function = "pin_fun2";
298*4882a593Smuzhiyun			};
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun			rk817_slppin_rst: rk817_slppin_rst {
301*4882a593Smuzhiyun				pins = "gpio_slp";
302*4882a593Smuzhiyun				function = "pin_fun3";
303*4882a593Smuzhiyun			};
304*4882a593Smuzhiyun		};
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun		regulators {
307*4882a593Smuzhiyun			vdd_logic: DCDC_REG1 {
308*4882a593Smuzhiyun				regulator-always-on;
309*4882a593Smuzhiyun				regulator-boot-on;
310*4882a593Smuzhiyun				regulator-min-microvolt = <850000>;
311*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
312*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
313*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
314*4882a593Smuzhiyun				regulator-name = "vdd_logic";
315*4882a593Smuzhiyun				regulator-state-mem {
316*4882a593Smuzhiyun					regulator-on-in-suspend;
317*4882a593Smuzhiyun					regulator-suspend-microvolt = <950000>;
318*4882a593Smuzhiyun				};
319*4882a593Smuzhiyun			};
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun			vdd_arm: DCDC_REG2 {
322*4882a593Smuzhiyun				regulator-always-on;
323*4882a593Smuzhiyun				regulator-boot-on;
324*4882a593Smuzhiyun				regulator-min-microvolt = <850000>;
325*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
326*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
327*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
328*4882a593Smuzhiyun				regulator-name = "vdd_arm";
329*4882a593Smuzhiyun				regulator-state-mem {
330*4882a593Smuzhiyun					regulator-off-in-suspend;
331*4882a593Smuzhiyun					regulator-suspend-microvolt = <950000>;
332*4882a593Smuzhiyun				};
333*4882a593Smuzhiyun			};
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun			vcc_ddr: DCDC_REG3 {
336*4882a593Smuzhiyun				regulator-always-on;
337*4882a593Smuzhiyun				regulator-boot-on;
338*4882a593Smuzhiyun				regulator-name = "vcc_ddr";
339*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
340*4882a593Smuzhiyun				regulator-state-mem {
341*4882a593Smuzhiyun					regulator-on-in-suspend;
342*4882a593Smuzhiyun				};
343*4882a593Smuzhiyun			};
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun			vcc_3v0: DCDC_REG4 {
346*4882a593Smuzhiyun				regulator-always-on;
347*4882a593Smuzhiyun				regulator-boot-on;
348*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
349*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
350*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
351*4882a593Smuzhiyun				regulator-name = "vcc_3v0";
352*4882a593Smuzhiyun				regulator-state-mem {
353*4882a593Smuzhiyun					regulator-on-in-suspend;
354*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
355*4882a593Smuzhiyun				};
356*4882a593Smuzhiyun			};
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun			vcc_1v0: LDO_REG1 {
359*4882a593Smuzhiyun				regulator-always-on;
360*4882a593Smuzhiyun				regulator-boot-on;
361*4882a593Smuzhiyun				regulator-min-microvolt = <1000000>;
362*4882a593Smuzhiyun				regulator-max-microvolt = <1000000>;
363*4882a593Smuzhiyun				regulator-name = "vcc_1v0";
364*4882a593Smuzhiyun				regulator-state-mem {
365*4882a593Smuzhiyun					regulator-on-in-suspend;
366*4882a593Smuzhiyun					regulator-suspend-microvolt = <1000000>;
367*4882a593Smuzhiyun				};
368*4882a593Smuzhiyun			};
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun			vcc1v8_soc: LDO_REG2 {
371*4882a593Smuzhiyun				regulator-always-on;
372*4882a593Smuzhiyun				regulator-boot-on;
373*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
374*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun				regulator-name = "vcc1v8_soc";
377*4882a593Smuzhiyun				regulator-state-mem {
378*4882a593Smuzhiyun					regulator-on-in-suspend;
379*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
380*4882a593Smuzhiyun				};
381*4882a593Smuzhiyun			};
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun			vdd1v0_soc: LDO_REG3 {
384*4882a593Smuzhiyun				regulator-always-on;
385*4882a593Smuzhiyun				regulator-boot-on;
386*4882a593Smuzhiyun				regulator-min-microvolt = <1000000>;
387*4882a593Smuzhiyun				regulator-max-microvolt = <1000000>;
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun				regulator-name = "vcc1v0_soc";
390*4882a593Smuzhiyun				regulator-state-mem {
391*4882a593Smuzhiyun					regulator-on-in-suspend;
392*4882a593Smuzhiyun					regulator-suspend-microvolt = <1000000>;
393*4882a593Smuzhiyun				};
394*4882a593Smuzhiyun			};
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun			vcc3v0_pmu: LDO_REG4 {
397*4882a593Smuzhiyun				regulator-always-on;
398*4882a593Smuzhiyun				regulator-boot-on;
399*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
400*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun				regulator-name = "vcc3v0_pmu";
403*4882a593Smuzhiyun				regulator-state-mem {
404*4882a593Smuzhiyun					regulator-on-in-suspend;
405*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun				};
408*4882a593Smuzhiyun			};
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun			vccio_sd: LDO_REG5 {
411*4882a593Smuzhiyun				regulator-always-on;
412*4882a593Smuzhiyun				regulator-boot-on;
413*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
414*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun				regulator-name = "vccio_sd";
417*4882a593Smuzhiyun				regulator-state-mem {
418*4882a593Smuzhiyun					regulator-on-in-suspend;
419*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
420*4882a593Smuzhiyun				};
421*4882a593Smuzhiyun			};
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun			vcc_sd: LDO_REG6 {
424*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
425*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun				regulator-name = "vcc_sd";
428*4882a593Smuzhiyun				regulator-state-mem {
429*4882a593Smuzhiyun					regulator-on-in-suspend;
430*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun				};
433*4882a593Smuzhiyun			};
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun			vcc2v8_dvp: LDO_REG7 {
436*4882a593Smuzhiyun				regulator-always-on;
437*4882a593Smuzhiyun				regulator-boot-on;
438*4882a593Smuzhiyun				regulator-min-microvolt = <2800000>;
439*4882a593Smuzhiyun				regulator-max-microvolt = <2800000>;
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun				regulator-name = "vcc2v8_dvp";
442*4882a593Smuzhiyun				regulator-state-mem {
443*4882a593Smuzhiyun					regulator-off-in-suspend;
444*4882a593Smuzhiyun					regulator-suspend-microvolt = <2800000>;
445*4882a593Smuzhiyun				};
446*4882a593Smuzhiyun			};
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun			vcc1v8_dvp: LDO_REG8 {
449*4882a593Smuzhiyun				regulator-always-on;
450*4882a593Smuzhiyun				regulator-boot-on;
451*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
452*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun				regulator-name = "vcc1v8_dvp";
455*4882a593Smuzhiyun				regulator-state-mem {
456*4882a593Smuzhiyun					regulator-on-in-suspend;
457*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
458*4882a593Smuzhiyun				};
459*4882a593Smuzhiyun			};
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun			vdd1v5_dvp: LDO_REG9 {
462*4882a593Smuzhiyun				regulator-always-on;
463*4882a593Smuzhiyun				regulator-boot-on;
464*4882a593Smuzhiyun				regulator-min-microvolt = <1500000>;
465*4882a593Smuzhiyun				regulator-max-microvolt = <1500000>;
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun				regulator-name = "vdd1v5_dvp";
468*4882a593Smuzhiyun				regulator-state-mem {
469*4882a593Smuzhiyun					regulator-off-in-suspend;
470*4882a593Smuzhiyun					regulator-suspend-microvolt = <1500000>;
471*4882a593Smuzhiyun				};
472*4882a593Smuzhiyun			};
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun			vcc3v3_sys: DCDC_REG5 {
475*4882a593Smuzhiyun				regulator-always-on;
476*4882a593Smuzhiyun				regulator-boot-on;
477*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
478*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
479*4882a593Smuzhiyun				regulator-name = "vcc3v3_sys";
480*4882a593Smuzhiyun				regulator-state-mem {
481*4882a593Smuzhiyun					regulator-on-in-suspend;
482*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
483*4882a593Smuzhiyun				};
484*4882a593Smuzhiyun			};
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun			vcc5v0_host: SWITCH_REG2 {
487*4882a593Smuzhiyun				regulator-always-on;
488*4882a593Smuzhiyun				regulator-boot-on;
489*4882a593Smuzhiyun				regulator-name = "vcc5v0_host";
490*4882a593Smuzhiyun			};
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun			vcc3v3_lcd: SWITCH_REG1 {
493*4882a593Smuzhiyun				regulator-boot-on;
494*4882a593Smuzhiyun				regulator-name = "vcc3v3_lcd";
495*4882a593Smuzhiyun			};
496*4882a593Smuzhiyun		};
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun		rk809_codec: codec {
499*4882a593Smuzhiyun			#sound-dai-cells = <0>;
500*4882a593Smuzhiyun			compatible = "rockchip,rk809-codec", "rockchip,rk817-codec";
501*4882a593Smuzhiyun			clocks = <&cru SCLK_I2S1_OUT>;
502*4882a593Smuzhiyun			clock-names = "mclk";
503*4882a593Smuzhiyun			pinctrl-names = "default";
504*4882a593Smuzhiyun			pinctrl-0 = <&i2s1_2ch_mclk>;
505*4882a593Smuzhiyun			hp-volume = <20>;
506*4882a593Smuzhiyun			spk-volume = <3>;
507*4882a593Smuzhiyun			status = "okay";
508*4882a593Smuzhiyun		};
509*4882a593Smuzhiyun	};
510*4882a593Smuzhiyun};
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun&i2c1 {
513*4882a593Smuzhiyun	status = "okay";
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun	sensor@f {
516*4882a593Smuzhiyun		status = "okay";
517*4882a593Smuzhiyun		compatible = "ak8963";
518*4882a593Smuzhiyun		reg = <0x0f>;
519*4882a593Smuzhiyun		type = <SENSOR_TYPE_COMPASS>;
520*4882a593Smuzhiyun		irq_enable = <0>;
521*4882a593Smuzhiyun		poll_delay_ms = <30>;
522*4882a593Smuzhiyun		layout = <1>;
523*4882a593Smuzhiyun		reprobe_en = <1>;
524*4882a593Smuzhiyun	};
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun	gt1x: gt1x@14 {
527*4882a593Smuzhiyun		compatible = "goodix,gt1x";
528*4882a593Smuzhiyun		reg = <0x14>;
529*4882a593Smuzhiyun		power-supply = <&vcc3v3_lcd>;
530*4882a593Smuzhiyun		goodix,rst-gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
531*4882a593Smuzhiyun		goodix,irq-gpio = <&gpio0 RK_PA5 IRQ_TYPE_LEVEL_LOW>;
532*4882a593Smuzhiyun	};
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun	sensor@4c {
535*4882a593Smuzhiyun		status = "okay";
536*4882a593Smuzhiyun		compatible = "gs_mma7660";
537*4882a593Smuzhiyun		reg = <0x4c>;
538*4882a593Smuzhiyun		type = <SENSOR_TYPE_ACCEL>;
539*4882a593Smuzhiyun		irq-gpio = <&gpio0 RK_PB7 IRQ_TYPE_LEVEL_LOW>;
540*4882a593Smuzhiyun		irq_enable = <0>;
541*4882a593Smuzhiyun		poll_delay_ms = <30>;
542*4882a593Smuzhiyun		layout = <8>;
543*4882a593Smuzhiyun		reprobe_en = <1>;
544*4882a593Smuzhiyun	};
545*4882a593Smuzhiyun};
546*4882a593Smuzhiyun
547*4882a593Smuzhiyun&i2c2 {
548*4882a593Smuzhiyun	status = "okay";
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun	clock-frequency = <100000>;
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun	/* These are relatively safe rise/fall times; TODO: measure */
553*4882a593Smuzhiyun	i2c-scl-falling-time-ns = <50>;
554*4882a593Smuzhiyun	i2c-scl-rising-time-ns = <300>;
555*4882a593Smuzhiyun
556*4882a593Smuzhiyun	ov5695: ov5695@36 {
557*4882a593Smuzhiyun		compatible = "ovti,ov5695";
558*4882a593Smuzhiyun		reg = <0x36>;
559*4882a593Smuzhiyun		clocks = <&cru SCLK_CIF_OUT>;
560*4882a593Smuzhiyun		clock-names = "xvclk";
561*4882a593Smuzhiyun		/*reset-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;*/
562*4882a593Smuzhiyun		pwdn-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;
563*4882a593Smuzhiyun		pinctrl-names = "default";
564*4882a593Smuzhiyun		pinctrl-0 = <&cif_clkout_m0>;
565*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
566*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
567*4882a593Smuzhiyun		rockchip,camera-module-name = "TongJu";
568*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "CHT842-MD";
569*4882a593Smuzhiyun		port {
570*4882a593Smuzhiyun			ucam_out: endpoint {
571*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ucam>;
572*4882a593Smuzhiyun				data-lanes = <1 2>;
573*4882a593Smuzhiyun			};
574*4882a593Smuzhiyun		};
575*4882a593Smuzhiyun	};
576*4882a593Smuzhiyun};
577*4882a593Smuzhiyun
578*4882a593Smuzhiyun&i2s1_2ch {
579*4882a593Smuzhiyun	status = "okay";
580*4882a593Smuzhiyun	#sound-dai-cells = <0>;
581*4882a593Smuzhiyun};
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun&io_domains {
584*4882a593Smuzhiyun	status = "okay";
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun	vccio1-supply = <&vcc1v8_soc>;
587*4882a593Smuzhiyun	vccio2-supply = <&vccio_sd>;
588*4882a593Smuzhiyun	vccio3-supply = <&vcc_3v0>;
589*4882a593Smuzhiyun	vccio4-supply = <&vcc3v0_pmu>;
590*4882a593Smuzhiyun	vccio5-supply = <&vcc_3v0>;
591*4882a593Smuzhiyun};
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun&isp_mmu {
594*4882a593Smuzhiyun	status = "okay";
595*4882a593Smuzhiyun};
596*4882a593Smuzhiyun
597*4882a593Smuzhiyun&mipi_dphy_rx0 {
598*4882a593Smuzhiyun	status = "okay";
599*4882a593Smuzhiyun
600*4882a593Smuzhiyun	ports {
601*4882a593Smuzhiyun		#address-cells = <1>;
602*4882a593Smuzhiyun		#size-cells = <0>;
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun		port@0 {
605*4882a593Smuzhiyun			reg = <0>;
606*4882a593Smuzhiyun			#address-cells = <1>;
607*4882a593Smuzhiyun			#size-cells = <0>;
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun			mipi_in_ucam: endpoint@1 {
610*4882a593Smuzhiyun				reg = <1>;
611*4882a593Smuzhiyun				remote-endpoint = <&ucam_out>;
612*4882a593Smuzhiyun				data-lanes = <1 2>;
613*4882a593Smuzhiyun			};
614*4882a593Smuzhiyun		};
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun		port@1 {
617*4882a593Smuzhiyun			reg = <1>;
618*4882a593Smuzhiyun			#address-cells = <1>;
619*4882a593Smuzhiyun			#size-cells = <0>;
620*4882a593Smuzhiyun
621*4882a593Smuzhiyun			dphy_rx0_out: endpoint@0 {
622*4882a593Smuzhiyun				reg = <0>;
623*4882a593Smuzhiyun				remote-endpoint = <&isp0_mipi_in>;
624*4882a593Smuzhiyun			};
625*4882a593Smuzhiyun		};
626*4882a593Smuzhiyun	};
627*4882a593Smuzhiyun};
628*4882a593Smuzhiyun
629*4882a593Smuzhiyun&nandc0 {
630*4882a593Smuzhiyun	status = "okay";
631*4882a593Smuzhiyun};
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun&pinctrl {
634*4882a593Smuzhiyun	headphone {
635*4882a593Smuzhiyun		hp_det: hp-det {
636*4882a593Smuzhiyun			rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
637*4882a593Smuzhiyun		};
638*4882a593Smuzhiyun	};
639*4882a593Smuzhiyun
640*4882a593Smuzhiyun	pmic {
641*4882a593Smuzhiyun		pmic_int: pmic_int {
642*4882a593Smuzhiyun			rockchip,pins =
643*4882a593Smuzhiyun				<0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
644*4882a593Smuzhiyun		};
645*4882a593Smuzhiyun
646*4882a593Smuzhiyun		soc_slppin_gpio: soc_slppin_gpio {
647*4882a593Smuzhiyun			rockchip,pins =
648*4882a593Smuzhiyun				<0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>;
649*4882a593Smuzhiyun		};
650*4882a593Smuzhiyun
651*4882a593Smuzhiyun		soc_slppin_slp: soc_slppin_slp {
652*4882a593Smuzhiyun			rockchip,pins =
653*4882a593Smuzhiyun				<0 RK_PA4 1 &pcfg_pull_none>;
654*4882a593Smuzhiyun		};
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun		soc_slppin_rst: soc_slppin_rst {
657*4882a593Smuzhiyun			rockchip,pins =
658*4882a593Smuzhiyun				<0 RK_PA4 2 &pcfg_pull_none>;
659*4882a593Smuzhiyun		};
660*4882a593Smuzhiyun	};
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun	sdio-pwrseq {
663*4882a593Smuzhiyun		wifi_enable_h: wifi-enable-h {
664*4882a593Smuzhiyun			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
665*4882a593Smuzhiyun		};
666*4882a593Smuzhiyun	};
667*4882a593Smuzhiyun};
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun&pmu_io_domains {
670*4882a593Smuzhiyun	status = "okay";
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun	pmuio1-supply = <&vcc3v0_pmu>;
673*4882a593Smuzhiyun	pmuio2-supply = <&vcc3v0_pmu>;
674*4882a593Smuzhiyun};
675*4882a593Smuzhiyun
676*4882a593Smuzhiyun&pwm1 {
677*4882a593Smuzhiyun	status = "okay";
678*4882a593Smuzhiyun};
679*4882a593Smuzhiyun
680*4882a593Smuzhiyun&rk_rga {
681*4882a593Smuzhiyun	status = "okay";
682*4882a593Smuzhiyun};
683*4882a593Smuzhiyun
684*4882a593Smuzhiyun&rkisp1 {
685*4882a593Smuzhiyun	status = "okay";
686*4882a593Smuzhiyun
687*4882a593Smuzhiyun	port {
688*4882a593Smuzhiyun		#address-cells = <1>;
689*4882a593Smuzhiyun		#size-cells = <0>;
690*4882a593Smuzhiyun
691*4882a593Smuzhiyun		isp0_mipi_in: endpoint@0 {
692*4882a593Smuzhiyun			reg = <0>;
693*4882a593Smuzhiyun			remote-endpoint = <&dphy_rx0_out>;
694*4882a593Smuzhiyun		};
695*4882a593Smuzhiyun	};
696*4882a593Smuzhiyun};
697*4882a593Smuzhiyun
698*4882a593Smuzhiyun&rockchip_suspend {
699*4882a593Smuzhiyun	status = "okay";
700*4882a593Smuzhiyun	rockchip,sleep-debug-en = <1>;
701*4882a593Smuzhiyun};
702*4882a593Smuzhiyun
703*4882a593Smuzhiyun&saradc {
704*4882a593Smuzhiyun	status = "okay";
705*4882a593Smuzhiyun	vref-supply = <&vcc1v8_soc>;
706*4882a593Smuzhiyun};
707*4882a593Smuzhiyun
708*4882a593Smuzhiyun&sdmmc {
709*4882a593Smuzhiyun	bus-width = <4>;
710*4882a593Smuzhiyun	cap-mmc-highspeed;
711*4882a593Smuzhiyun	cap-sd-highspeed;
712*4882a593Smuzhiyun	no-sdio;
713*4882a593Smuzhiyun	no-mmc;
714*4882a593Smuzhiyun	card-detect-delay = <800>;
715*4882a593Smuzhiyun	ignore-pm-notify;
716*4882a593Smuzhiyun	/*cd-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; [> CD GPIO <]*/
717*4882a593Smuzhiyun	sd-uhs-sdr12;
718*4882a593Smuzhiyun	sd-uhs-sdr25;
719*4882a593Smuzhiyun	sd-uhs-sdr50;
720*4882a593Smuzhiyun	sd-uhs-sdr104;
721*4882a593Smuzhiyun	vqmmc-supply = <&vccio_sd>;
722*4882a593Smuzhiyun	vmmc-supply = <&vcc_sd>;
723*4882a593Smuzhiyun	status = "okay";
724*4882a593Smuzhiyun};
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun&sdio {
727*4882a593Smuzhiyun	bus-width = <4>;
728*4882a593Smuzhiyun	cap-sd-highspeed;
729*4882a593Smuzhiyun	no-sd;
730*4882a593Smuzhiyun	no-mmc;
731*4882a593Smuzhiyun	ignore-pm-notify;
732*4882a593Smuzhiyun	keep-power-in-suspend;
733*4882a593Smuzhiyun	non-removable;
734*4882a593Smuzhiyun	mmc-pwrseq = <&sdio_pwrseq>;
735*4882a593Smuzhiyun	sd-uhs-sdr104;
736*4882a593Smuzhiyun	status = "okay";
737*4882a593Smuzhiyun};
738*4882a593Smuzhiyun
739*4882a593Smuzhiyun&tsadc {
740*4882a593Smuzhiyun	pinctrl-names = "gpio", "otpout";
741*4882a593Smuzhiyun	pinctrl-0 = <&tsadc_otp_pin>;
742*4882a593Smuzhiyun	pinctrl-1 = <&tsadc_otp_out>;
743*4882a593Smuzhiyun	status = "okay";
744*4882a593Smuzhiyun};
745*4882a593Smuzhiyun
746*4882a593Smuzhiyun&uart1 {
747*4882a593Smuzhiyun	pinctrl-names = "default";
748*4882a593Smuzhiyun	pinctrl-0 = <&uart1_xfer &uart1_cts>;
749*4882a593Smuzhiyun	status = "okay";
750*4882a593Smuzhiyun};
751*4882a593Smuzhiyun
752*4882a593Smuzhiyun&u2phy {
753*4882a593Smuzhiyun	status = "okay";
754*4882a593Smuzhiyun
755*4882a593Smuzhiyun	u2phy_host: host-port {
756*4882a593Smuzhiyun		status = "okay";
757*4882a593Smuzhiyun	};
758*4882a593Smuzhiyun
759*4882a593Smuzhiyun	u2phy_otg: otg-port {
760*4882a593Smuzhiyun		status = "okay";
761*4882a593Smuzhiyun	};
762*4882a593Smuzhiyun};
763*4882a593Smuzhiyun
764*4882a593Smuzhiyun&usb20_otg {
765*4882a593Smuzhiyun	status = "okay";
766*4882a593Smuzhiyun};
767*4882a593Smuzhiyun
768*4882a593Smuzhiyun&usb_host0_ehci {
769*4882a593Smuzhiyun	status = "okay";
770*4882a593Smuzhiyun};
771*4882a593Smuzhiyun
772*4882a593Smuzhiyun&usb_host0_ohci {
773*4882a593Smuzhiyun	status = "okay";
774*4882a593Smuzhiyun};
775*4882a593Smuzhiyun
776*4882a593Smuzhiyun&vopb {
777*4882a593Smuzhiyun	status = "okay";
778*4882a593Smuzhiyun};
779*4882a593Smuzhiyun
780*4882a593Smuzhiyun&vopb_mmu {
781*4882a593Smuzhiyun	status = "okay";
782*4882a593Smuzhiyun};
783*4882a593Smuzhiyun
784*4882a593Smuzhiyun&vopl {
785*4882a593Smuzhiyun	status = "okay";
786*4882a593Smuzhiyun};
787*4882a593Smuzhiyun
788*4882a593Smuzhiyun&vopl_mmu {
789*4882a593Smuzhiyun	status = "okay";
790*4882a593Smuzhiyun};
791*4882a593Smuzhiyun
792*4882a593Smuzhiyun&mpp_srv {
793*4882a593Smuzhiyun	status = "okay";
794*4882a593Smuzhiyun};
795*4882a593Smuzhiyun
796*4882a593Smuzhiyun&vdpu {
797*4882a593Smuzhiyun	status = "okay";
798*4882a593Smuzhiyun};
799*4882a593Smuzhiyun
800*4882a593Smuzhiyun&vepu {
801*4882a593Smuzhiyun	status = "okay";
802*4882a593Smuzhiyun};
803*4882a593Smuzhiyun
804*4882a593Smuzhiyun&vpu_mmu {
805*4882a593Smuzhiyun	status = "okay";
806*4882a593Smuzhiyun};
807*4882a593Smuzhiyun
808*4882a593Smuzhiyun&hevc {
809*4882a593Smuzhiyun	status = "okay";
810*4882a593Smuzhiyun};
811*4882a593Smuzhiyun
812*4882a593Smuzhiyun&hevc_mmu {
813*4882a593Smuzhiyun	status = "okay";
814*4882a593Smuzhiyun};
815