1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun#include <dt-bindings/clock/rk618-cru.h> 8*4882a593Smuzhiyun#include "px30-ad-r35-mb.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun&dmc { 11*4882a593Smuzhiyun auto-freq-en = <0>; 12*4882a593Smuzhiyun}; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun&i2c0 { 15*4882a593Smuzhiyun status = "okay"; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun rk618@50 { 18*4882a593Smuzhiyun compatible = "rockchip,rk618"; 19*4882a593Smuzhiyun reg = <0x50>; 20*4882a593Smuzhiyun pinctrl-names = "default"; 21*4882a593Smuzhiyun pinctrl-0 = <&i2s1_2ch_mclk>; 22*4882a593Smuzhiyun clocks = <&cru SCLK_I2S1_OUT>; 23*4882a593Smuzhiyun clock-names = "clkin"; 24*4882a593Smuzhiyun assigned-clocks = <&cru SCLK_I2S1_OUT>; 25*4882a593Smuzhiyun assigned-clock-rates = <11289600>; 26*4882a593Smuzhiyun reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; 27*4882a593Smuzhiyun status = "okay"; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun clock: cru { 30*4882a593Smuzhiyun compatible = "rockchip,rk618-cru"; 31*4882a593Smuzhiyun clocks = <&cru SCLK_I2S1_OUT>, <&cru DCLK_VOPL>; 32*4882a593Smuzhiyun clock-names = "clkin", "lcdc0_dclkp"; 33*4882a593Smuzhiyun assigned-clocks = <&clock SCALER_PLLIN_CLK>, 34*4882a593Smuzhiyun <&clock VIF_PLLIN_CLK>, 35*4882a593Smuzhiyun <&clock SCALER_CLK>, 36*4882a593Smuzhiyun <&clock VIF0_PRE_CLK>, 37*4882a593Smuzhiyun <&clock CODEC_CLK>, 38*4882a593Smuzhiyun <&clock DITHER_CLK>; 39*4882a593Smuzhiyun assigned-clock-parents = <&cru SCLK_I2S1_OUT>, 40*4882a593Smuzhiyun <&clock LCDC0_CLK>, 41*4882a593Smuzhiyun <&clock SCALER_PLL_CLK>, 42*4882a593Smuzhiyun <&clock VIF_PLL_CLK>, 43*4882a593Smuzhiyun <&cru SCLK_I2S1_OUT>, 44*4882a593Smuzhiyun <&clock VIF0_CLK>; 45*4882a593Smuzhiyun #clock-cells = <1>; 46*4882a593Smuzhiyun status = "okay"; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun hdmi { 50*4882a593Smuzhiyun compatible = "rockchip,rk618-hdmi"; 51*4882a593Smuzhiyun clocks = <&clock HDMI_CLK>; 52*4882a593Smuzhiyun clock-names = "hdmi"; 53*4882a593Smuzhiyun assigned-clocks = <&clock HDMI_CLK>; 54*4882a593Smuzhiyun assigned-clock-parents = <&clock VIF0_CLK>; 55*4882a593Smuzhiyun interrupt-parent = <&gpio2>; 56*4882a593Smuzhiyun interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; 57*4882a593Smuzhiyun status = "okay"; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun ports { 60*4882a593Smuzhiyun #address-cells = <1>; 61*4882a593Smuzhiyun #size-cells = <0>; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun port@0 { 64*4882a593Smuzhiyun reg = <0>; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun hdmi_in_rgb: endpoint { 67*4882a593Smuzhiyun remote-endpoint = <&rgb_out_hdmi>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun}; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun&vopl { 76*4882a593Smuzhiyun assigned-clocks = <&cru PLL_NPLL>; 77*4882a593Smuzhiyun assigned-clock-rates = <1188000000>; 78*4882a593Smuzhiyun}; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun&rgb { 81*4882a593Smuzhiyun status = "okay"; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun ports { 84*4882a593Smuzhiyun port@1 { 85*4882a593Smuzhiyun reg = <1>; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun rgb_out_hdmi: endpoint { 88*4882a593Smuzhiyun remote-endpoint = <&hdmi_in_rgb>; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun}; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun&rgb_in_vopb { 95*4882a593Smuzhiyun status = "disabled"; 96*4882a593Smuzhiyun}; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun&rgb_in_vopl { 99*4882a593Smuzhiyun status = "okay"; 100*4882a593Smuzhiyun}; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun&route_rgb { 103*4882a593Smuzhiyun connect = <&vopl_out_rgb>; 104*4882a593Smuzhiyun status = "okay"; 105*4882a593Smuzhiyun}; 106