1*4882a593Smuzhiyun/dts-v1/; 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 4*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h> 5*4882a593Smuzhiyun#include <dt-bindings/input/rk-input.h> 6*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h> 7*4882a593Smuzhiyun#include <dt-bindings/display/rockchip_vop.h> 8*4882a593Smuzhiyun#include <dt-bindings/display/media-bus-format.h> 9*4882a593Smuzhiyun#include "rk3568.dtsi" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun model = "Forlinx OK-x-U40 Board"; 13*4882a593Smuzhiyun compatible = "forlinx,ok3568", "rockchip,rk3568-evb1-ddr4-v10", "rockchip,rk3568"; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun forlinx_control { 16*4882a593Smuzhiyun status = "disabled"; 17*4882a593Smuzhiyun video-hdmi = "hdmi"; 18*4882a593Smuzhiyun video-mipi-edp = "mipi"; 19*4882a593Smuzhiyun video-lvds-rgb = "lvds"; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun leds: leds { 23*4882a593Smuzhiyun compatible = "gpio-leds"; 24*4882a593Smuzhiyun work_led: work { 25*4882a593Smuzhiyun gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; 26*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* backlight */ 31*4882a593Smuzhiyun dsi1_backlight: dsi1-backlight { 32*4882a593Smuzhiyun compatible = "pwm-backlight"; 33*4882a593Smuzhiyun pwms = <&pwm14 0 20000 0>; 34*4882a593Smuzhiyun brightness-levels = < 35*4882a593Smuzhiyun 0 20 20 21 21 22 22 23 36*4882a593Smuzhiyun 23 24 24 25 25 26 26 27 37*4882a593Smuzhiyun 27 28 28 29 29 30 30 31 38*4882a593Smuzhiyun 31 32 32 33 33 34 34 35 39*4882a593Smuzhiyun 35 36 36 37 37 38 38 39 40*4882a593Smuzhiyun 40 41 42 43 44 45 46 47 41*4882a593Smuzhiyun 48 49 50 51 52 53 54 55 42*4882a593Smuzhiyun 56 57 58 59 60 61 62 63 43*4882a593Smuzhiyun 64 65 66 67 68 69 70 71 44*4882a593Smuzhiyun 72 73 74 75 76 77 78 79 45*4882a593Smuzhiyun 80 81 82 83 84 85 86 87 46*4882a593Smuzhiyun 88 89 90 91 92 93 94 95 47*4882a593Smuzhiyun 96 97 98 99 100 101 102 103 48*4882a593Smuzhiyun 104 105 106 107 108 109 110 111 49*4882a593Smuzhiyun 112 113 114 115 116 117 118 119 50*4882a593Smuzhiyun 120 121 122 123 124 125 126 127 51*4882a593Smuzhiyun 128 129 130 131 132 133 134 135 52*4882a593Smuzhiyun 136 137 138 139 140 141 142 143 53*4882a593Smuzhiyun 144 145 146 147 148 149 150 151 54*4882a593Smuzhiyun 152 153 154 155 156 157 158 159 55*4882a593Smuzhiyun 160 161 162 163 164 165 166 167 56*4882a593Smuzhiyun 168 169 170 171 172 173 174 175 57*4882a593Smuzhiyun 176 177 178 179 180 181 182 183 58*4882a593Smuzhiyun 184 185 186 187 188 189 190 191 59*4882a593Smuzhiyun 192 193 194 195 196 197 198 199 60*4882a593Smuzhiyun 200 201 202 203 204 205 206 207 61*4882a593Smuzhiyun 208 209 210 211 212 213 214 215 62*4882a593Smuzhiyun 216 217 218 219 220 221 222 223 63*4882a593Smuzhiyun 224 225 226 227 228 229 230 231 64*4882a593Smuzhiyun 232 233 234 235 236 237 238 239 65*4882a593Smuzhiyun 240 241 242 243 244 245 246 247 66*4882a593Smuzhiyun 248 249 250 251 252 253 254 255 67*4882a593Smuzhiyun >; 68*4882a593Smuzhiyun default-brightness-level = <200>; 69*4882a593Smuzhiyun is-forlinx; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun lvds_backlight: lvds-backlight { 73*4882a593Smuzhiyun compatible = "pwm-backlight"; 74*4882a593Smuzhiyun pwms = <&pwm3 0 20000 0>; 75*4882a593Smuzhiyun brightness-levels = < 76*4882a593Smuzhiyun 0 20 20 21 21 22 22 23 77*4882a593Smuzhiyun 23 24 24 25 25 26 26 27 78*4882a593Smuzhiyun 27 28 28 29 29 30 30 31 79*4882a593Smuzhiyun 31 32 32 33 33 34 34 35 80*4882a593Smuzhiyun 35 36 36 37 37 38 38 39 81*4882a593Smuzhiyun 40 41 42 43 44 45 46 47 82*4882a593Smuzhiyun 48 49 50 51 52 53 54 55 83*4882a593Smuzhiyun 56 57 58 59 60 61 62 63 84*4882a593Smuzhiyun 64 65 66 67 68 69 70 71 85*4882a593Smuzhiyun 72 73 74 75 76 77 78 79 86*4882a593Smuzhiyun 80 81 82 83 84 85 86 87 87*4882a593Smuzhiyun 88 89 90 91 92 93 94 95 88*4882a593Smuzhiyun 96 97 98 99 100 101 102 103 89*4882a593Smuzhiyun 104 105 106 107 108 109 110 111 90*4882a593Smuzhiyun 112 113 114 115 116 117 118 119 91*4882a593Smuzhiyun 120 121 122 123 124 125 126 127 92*4882a593Smuzhiyun 128 129 130 131 132 133 134 135 93*4882a593Smuzhiyun 136 137 138 139 140 141 142 143 94*4882a593Smuzhiyun 144 145 146 147 148 149 150 151 95*4882a593Smuzhiyun 152 153 154 155 156 157 158 159 96*4882a593Smuzhiyun 160 161 162 163 164 165 166 167 97*4882a593Smuzhiyun 168 169 170 171 172 173 174 175 98*4882a593Smuzhiyun 176 177 178 179 180 181 182 183 99*4882a593Smuzhiyun 184 185 186 187 188 189 190 191 100*4882a593Smuzhiyun 192 193 194 195 196 197 198 199 101*4882a593Smuzhiyun 200 201 202 203 204 205 206 207 102*4882a593Smuzhiyun 208 209 210 211 212 213 214 215 103*4882a593Smuzhiyun 216 217 218 219 220 221 222 223 104*4882a593Smuzhiyun 224 225 226 227 228 229 230 231 105*4882a593Smuzhiyun 232 233 234 235 236 237 238 239 106*4882a593Smuzhiyun 240 241 242 243 244 245 246 247 107*4882a593Smuzhiyun 248 249 250 251 252 253 254 255 108*4882a593Smuzhiyun >; 109*4882a593Smuzhiyun default-brightness-level = <200>; 110*4882a593Smuzhiyun is-forlinx; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun rgb_backlight: rgb-backlight { 114*4882a593Smuzhiyun compatible = "pwm-backlight"; 115*4882a593Smuzhiyun pwms = <&pwm5 0 20000 0>; 116*4882a593Smuzhiyun brightness-levels = < 117*4882a593Smuzhiyun 0 20 20 21 21 22 22 23 118*4882a593Smuzhiyun 23 24 24 25 25 26 26 27 119*4882a593Smuzhiyun 27 28 28 29 29 30 30 31 120*4882a593Smuzhiyun 31 32 32 33 33 34 34 35 121*4882a593Smuzhiyun 35 36 36 37 37 38 38 39 122*4882a593Smuzhiyun 40 41 42 43 44 45 46 47 123*4882a593Smuzhiyun 48 49 50 51 52 53 54 55 124*4882a593Smuzhiyun 56 57 58 59 60 61 62 63 125*4882a593Smuzhiyun 64 65 66 67 68 69 70 71 126*4882a593Smuzhiyun 72 73 74 75 76 77 78 79 127*4882a593Smuzhiyun 80 81 82 83 84 85 86 87 128*4882a593Smuzhiyun 88 89 90 91 92 93 94 95 129*4882a593Smuzhiyun 96 97 98 99 100 101 102 103 130*4882a593Smuzhiyun 104 105 106 107 108 109 110 111 131*4882a593Smuzhiyun 112 113 114 115 116 117 118 119 132*4882a593Smuzhiyun 120 121 122 123 124 125 126 127 133*4882a593Smuzhiyun 128 129 130 131 132 133 134 135 134*4882a593Smuzhiyun 136 137 138 139 140 141 142 143 135*4882a593Smuzhiyun 144 145 146 147 148 149 150 151 136*4882a593Smuzhiyun 152 153 154 155 156 157 158 159 137*4882a593Smuzhiyun 160 161 162 163 164 165 166 167 138*4882a593Smuzhiyun 168 169 170 171 172 173 174 175 139*4882a593Smuzhiyun 176 177 178 179 180 181 182 183 140*4882a593Smuzhiyun 184 185 186 187 188 189 190 191 141*4882a593Smuzhiyun 192 193 194 195 196 197 198 199 142*4882a593Smuzhiyun 200 201 202 203 204 205 206 207 143*4882a593Smuzhiyun 208 209 210 211 212 213 214 215 144*4882a593Smuzhiyun 216 217 218 219 220 221 222 223 145*4882a593Smuzhiyun 224 225 226 227 228 229 230 231 146*4882a593Smuzhiyun 232 233 234 235 236 237 238 239 147*4882a593Smuzhiyun 240 241 242 243 244 245 246 247 148*4882a593Smuzhiyun 248 249 250 251 252 253 254 255 149*4882a593Smuzhiyun >; 150*4882a593Smuzhiyun default-brightness-level = <200>; 151*4882a593Smuzhiyun is-forlinx; 152*4882a593Smuzhiyun }; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun edp_backlight: edp-backlight { 155*4882a593Smuzhiyun compatible = "pwm-backlight"; 156*4882a593Smuzhiyun pwms = <&pwm4 0 20000 0>; 157*4882a593Smuzhiyun brightness-levels = < 158*4882a593Smuzhiyun 0 20 20 21 21 22 22 23 159*4882a593Smuzhiyun 23 24 24 25 25 26 26 27 160*4882a593Smuzhiyun 27 28 28 29 29 30 30 31 161*4882a593Smuzhiyun 31 32 32 33 33 34 34 35 162*4882a593Smuzhiyun 35 36 36 37 37 38 38 39 163*4882a593Smuzhiyun 40 41 42 43 44 45 46 47 164*4882a593Smuzhiyun 48 49 50 51 52 53 54 55 165*4882a593Smuzhiyun 56 57 58 59 60 61 62 63 166*4882a593Smuzhiyun 64 65 66 67 68 69 70 71 167*4882a593Smuzhiyun 72 73 74 75 76 77 78 79 168*4882a593Smuzhiyun 80 81 82 83 84 85 86 87 169*4882a593Smuzhiyun 88 89 90 91 92 93 94 95 170*4882a593Smuzhiyun 96 97 98 99 100 101 102 103 171*4882a593Smuzhiyun 104 105 106 107 108 109 110 111 172*4882a593Smuzhiyun 112 113 114 115 116 117 118 119 173*4882a593Smuzhiyun 120 121 122 123 124 125 126 127 174*4882a593Smuzhiyun 128 129 130 131 132 133 134 135 175*4882a593Smuzhiyun 136 137 138 139 140 141 142 143 176*4882a593Smuzhiyun 144 145 146 147 148 149 150 151 177*4882a593Smuzhiyun 152 153 154 155 156 157 158 159 178*4882a593Smuzhiyun 160 161 162 163 164 165 166 167 179*4882a593Smuzhiyun 168 169 170 171 172 173 174 175 180*4882a593Smuzhiyun 176 177 178 179 180 181 182 183 181*4882a593Smuzhiyun 184 185 186 187 188 189 190 191 182*4882a593Smuzhiyun 192 193 194 195 196 197 198 199 183*4882a593Smuzhiyun 200 201 202 203 204 205 206 207 184*4882a593Smuzhiyun 208 209 210 211 212 213 214 215 185*4882a593Smuzhiyun 216 217 218 219 220 221 222 223 186*4882a593Smuzhiyun 224 225 226 227 228 229 230 231 187*4882a593Smuzhiyun 232 233 234 235 236 237 238 239 188*4882a593Smuzhiyun 240 241 242 243 244 245 246 247 189*4882a593Smuzhiyun 248 249 250 251 252 253 254 255 190*4882a593Smuzhiyun >; 191*4882a593Smuzhiyun default-brightness-level = <200>; 192*4882a593Smuzhiyun }; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun /* panel */ 195*4882a593Smuzhiyun edp-panel { 196*4882a593Smuzhiyun compatible = "simple-panel"; 197*4882a593Smuzhiyun prepare-delay-ms = <120>; 198*4882a593Smuzhiyun enable-delay-ms = <120>; 199*4882a593Smuzhiyun unprepare-delay-ms = <120>; 200*4882a593Smuzhiyun disable-delay-ms = <120>; 201*4882a593Smuzhiyun backlight = <&edp_backlight>; 202*4882a593Smuzhiyun enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun port { 205*4882a593Smuzhiyun panel_in_edp: endpoint { 206*4882a593Smuzhiyun remote-endpoint = <&edp_out_panel>; 207*4882a593Smuzhiyun }; 208*4882a593Smuzhiyun }; 209*4882a593Smuzhiyun }; 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun lvds-panel { 212*4882a593Smuzhiyun compatible = "simple-panel"; 213*4882a593Smuzhiyun backlight = <&lvds_backlight>; 214*4882a593Smuzhiyun power-supply = <&vcc5v_lvds_en>; 215*4882a593Smuzhiyun enable-delay-ms = <20>; 216*4882a593Smuzhiyun prepare-delay-ms = <20>; 217*4882a593Smuzhiyun unprepare-delay-ms = <20>; 218*4882a593Smuzhiyun disable-delay-ms = <20>; 219*4882a593Smuzhiyun bus-format = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>; 220*4882a593Smuzhiyun width-mm = <152>; 221*4882a593Smuzhiyun height-mm = <91>; 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun display-timings { 224*4882a593Smuzhiyun native-mode = <&lvds_1280x800>; 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun lvds_1280x800: timing0 { 227*4882a593Smuzhiyun clock-frequency = <71000000>; 228*4882a593Smuzhiyun hactive = <1280>; 229*4882a593Smuzhiyun vactive = <800>; 230*4882a593Smuzhiyun hback-porch = <10>; 231*4882a593Smuzhiyun hfront-porch = <140>; 232*4882a593Smuzhiyun hsync-len = <10>; 233*4882a593Smuzhiyun vback-porch = <1>; 234*4882a593Smuzhiyun vfront-porch = <2>; 235*4882a593Smuzhiyun vsync-len = <20>; 236*4882a593Smuzhiyun hsync-active = <0>; 237*4882a593Smuzhiyun vsync-active = <1>; 238*4882a593Smuzhiyun de-active = <1>; 239*4882a593Smuzhiyun pixelclk-active = <0>; 240*4882a593Smuzhiyun }; 241*4882a593Smuzhiyun }; 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun ports { 244*4882a593Smuzhiyun #address-cells = <1>; 245*4882a593Smuzhiyun #size-cells = <0>; 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun port@0 { 248*4882a593Smuzhiyun reg = <0>; 249*4882a593Smuzhiyun dual-lvds-even-pixels; 250*4882a593Smuzhiyun panel_in_lvds: endpoint { 251*4882a593Smuzhiyun remote-endpoint = <&lvds_out_panel>; 252*4882a593Smuzhiyun }; 253*4882a593Smuzhiyun }; 254*4882a593Smuzhiyun }; 255*4882a593Smuzhiyun }; 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun rgb-panel { 258*4882a593Smuzhiyun compatible = "simple-panel"; 259*4882a593Smuzhiyun backlight = <&rgb_backlight>; 260*4882a593Smuzhiyun bus-format = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>; 261*4882a593Smuzhiyun enable-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun display-timings { 264*4882a593Smuzhiyun native-mode = <&rgb_1024x600>; 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun rgb_1024x600: timing0 { 267*4882a593Smuzhiyun clock-frequency = <51200000>; 268*4882a593Smuzhiyun hactive = <1024>; 269*4882a593Smuzhiyun vactive = <600>; 270*4882a593Smuzhiyun hfront-porch = <160>; 271*4882a593Smuzhiyun hback-porch = <320>; 272*4882a593Smuzhiyun hsync-len = <1>; 273*4882a593Smuzhiyun vback-porch = <35>; 274*4882a593Smuzhiyun vfront-porch = <12>; 275*4882a593Smuzhiyun vsync-len = <1>; 276*4882a593Smuzhiyun hsync-active = <0>; 277*4882a593Smuzhiyun vsync-active = <0>; 278*4882a593Smuzhiyun de-active = <1>; 279*4882a593Smuzhiyun pixelclk-active = <1>; 280*4882a593Smuzhiyun }; 281*4882a593Smuzhiyun }; 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun ports { 284*4882a593Smuzhiyun #address-cells = <1>; 285*4882a593Smuzhiyun #size-cells = <0>; 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun port@0 { 288*4882a593Smuzhiyun reg = <0>; 289*4882a593Smuzhiyun panel_in_rgb: endpoint { 290*4882a593Smuzhiyun remote-endpoint = <&rgb_out_panel>; 291*4882a593Smuzhiyun }; 292*4882a593Smuzhiyun }; 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun }; 295*4882a593Smuzhiyun }; 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun hdmi_sound: hdmi-sound { 298*4882a593Smuzhiyun status = "okay"; 299*4882a593Smuzhiyun compatible = "rockchip,hdmi"; 300*4882a593Smuzhiyun rockchip,mclk-fs = <128>; 301*4882a593Smuzhiyun rockchip,card-name = "rockchip,hdmi"; 302*4882a593Smuzhiyun rockchip,cpu = <&i2s0_8ch>; 303*4882a593Smuzhiyun rockchip,codec = <&hdmi>; 304*4882a593Smuzhiyun rockchip,jack-det; 305*4882a593Smuzhiyun }; 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun pdmics: dummy-codec { 308*4882a593Smuzhiyun status = "disabled"; 309*4882a593Smuzhiyun compatible = "rockchip,dummy-codec"; 310*4882a593Smuzhiyun #sound-dai-cells = <0>; 311*4882a593Smuzhiyun }; 312*4882a593Smuzhiyun 313*4882a593Smuzhiyun pdm_mic_array: pdm-mic-array { 314*4882a593Smuzhiyun status = "disabled"; 315*4882a593Smuzhiyun compatible = "simple-audio-card"; 316*4882a593Smuzhiyun simple-audio-card,name = "rockchip,pdm-mic-array"; 317*4882a593Smuzhiyun simple-audio-card,cpu { 318*4882a593Smuzhiyun sound-dai = <&pdm>; 319*4882a593Smuzhiyun }; 320*4882a593Smuzhiyun simple-audio-card,codec { 321*4882a593Smuzhiyun sound-dai = <&pdmics>; 322*4882a593Smuzhiyun }; 323*4882a593Smuzhiyun }; 324*4882a593Smuzhiyun 325*4882a593Smuzhiyun audiopwmout_diff: audiopwmout-diff { 326*4882a593Smuzhiyun status = "disabled"; 327*4882a593Smuzhiyun compatible = "simple-audio-card"; 328*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 329*4882a593Smuzhiyun simple-audio-card,name = "rockchip,audiopwmout-diff"; 330*4882a593Smuzhiyun simple-audio-card,mclk-fs = <256>; 331*4882a593Smuzhiyun simple-audio-card,bitclock-master = <&master>; 332*4882a593Smuzhiyun simple-audio-card,frame-master = <&master>; 333*4882a593Smuzhiyun simple-audio-card,cpu { 334*4882a593Smuzhiyun sound-dai = <&i2s3_2ch>; 335*4882a593Smuzhiyun }; 336*4882a593Smuzhiyun master: simple-audio-card,codec { 337*4882a593Smuzhiyun sound-dai = <&dig_acodec>; 338*4882a593Smuzhiyun }; 339*4882a593Smuzhiyun }; 340*4882a593Smuzhiyun 341*4882a593Smuzhiyun rk809_sound: rk809-sound { 342*4882a593Smuzhiyun status = "okay"; 343*4882a593Smuzhiyun compatible = "rockchip,multicodecs-card"; 344*4882a593Smuzhiyun rockchip,card-name = "rockchip-rk809"; 345*4882a593Smuzhiyun hp-det-gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; 346*4882a593Smuzhiyun rockchip,format = "i2s"; 347*4882a593Smuzhiyun rockchip,mclk-fs = <256>; 348*4882a593Smuzhiyun rockchip,cpu = <&i2s1_8ch>; 349*4882a593Smuzhiyun rockchip,codec = <&rk809_codec>; 350*4882a593Smuzhiyun pinctrl-names = "default"; 351*4882a593Smuzhiyun pinctrl-0 = <&hp_det>; 352*4882a593Smuzhiyun 353*4882a593Smuzhiyun }; 354*4882a593Smuzhiyun 355*4882a593Smuzhiyun spdif-sound { 356*4882a593Smuzhiyun status = "disabled"; 357*4882a593Smuzhiyun compatible = "simple-audio-card"; 358*4882a593Smuzhiyun simple-audio-card,name = "ROCKCHIP,SPDIF"; 359*4882a593Smuzhiyun simple-audio-card,cpu { 360*4882a593Smuzhiyun sound-dai = <&spdif_8ch>; 361*4882a593Smuzhiyun }; 362*4882a593Smuzhiyun simple-audio-card,codec { 363*4882a593Smuzhiyun sound-dai = <&spdif_out>; 364*4882a593Smuzhiyun }; 365*4882a593Smuzhiyun }; 366*4882a593Smuzhiyun 367*4882a593Smuzhiyun spdif_out: spdif-out { 368*4882a593Smuzhiyun status = "disabled"; 369*4882a593Smuzhiyun compatible = "linux,spdif-dit"; 370*4882a593Smuzhiyun #sound-dai-cells = <0>; 371*4882a593Smuzhiyun }; 372*4882a593Smuzhiyun 373*4882a593Smuzhiyun vcc12v: vcc-12v { 374*4882a593Smuzhiyun compatible = "regulator-fixed"; 375*4882a593Smuzhiyun regulator-name = "vcc12v"; 376*4882a593Smuzhiyun regulator-always-on; 377*4882a593Smuzhiyun regulator-boot-on; 378*4882a593Smuzhiyun regulator-min-microvolt = <12000000>; 379*4882a593Smuzhiyun regulator-max-microvolt = <12000000>; 380*4882a593Smuzhiyun }; 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun vcc5v0_sys: vcc5v0-sys { 383*4882a593Smuzhiyun compatible = "regulator-fixed"; 384*4882a593Smuzhiyun regulator-name = "vcc5v0_sys"; 385*4882a593Smuzhiyun regulator-always-on; 386*4882a593Smuzhiyun regulator-boot-on; 387*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 388*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 389*4882a593Smuzhiyun vin-supply = <&vcc12v>; 390*4882a593Smuzhiyun }; 391*4882a593Smuzhiyun 392*4882a593Smuzhiyun vcc3v3_sys: vcc3v3-sys { 393*4882a593Smuzhiyun compatible = "regulator-fixed"; 394*4882a593Smuzhiyun regulator-name = "vcc3v3_sys"; 395*4882a593Smuzhiyun regulator-always-on; 396*4882a593Smuzhiyun regulator-boot-on; 397*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 398*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 399*4882a593Smuzhiyun vin-supply = <&vcc5v0_sys>; 400*4882a593Smuzhiyun }; 401*4882a593Smuzhiyun 402*4882a593Smuzhiyun //for main board 403*4882a593Smuzhiyun vcc3v3: vcc-3v3 { 404*4882a593Smuzhiyun compatible = "regulator-fixed"; 405*4882a593Smuzhiyun regulator-name = "vcc3v3"; 406*4882a593Smuzhiyun regulator-always-on; 407*4882a593Smuzhiyun regulator-boot-on; 408*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 409*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 410*4882a593Smuzhiyun vin-supply = <&vcc5v0_sys>; 411*4882a593Smuzhiyun }; 412*4882a593Smuzhiyun 413*4882a593Smuzhiyun vcc1v8: vcc-1v8 { 414*4882a593Smuzhiyun compatible = "regulator-fixed"; 415*4882a593Smuzhiyun regulator-name = "vcc1v8"; 416*4882a593Smuzhiyun regulator-always-on; 417*4882a593Smuzhiyun regulator-boot-on; 418*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 419*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 420*4882a593Smuzhiyun vin-supply = <&vcc3v3>; 421*4882a593Smuzhiyun }; 422*4882a593Smuzhiyun 423*4882a593Smuzhiyun vcc1v2: vcc-1v2 { 424*4882a593Smuzhiyun compatible = "regulator-fixed"; 425*4882a593Smuzhiyun regulator-name = "vcc1v2"; 426*4882a593Smuzhiyun regulator-always-on; 427*4882a593Smuzhiyun regulator-boot-on; 428*4882a593Smuzhiyun regulator-min-microvolt = <1200000>; 429*4882a593Smuzhiyun regulator-max-microvolt = <1200000>; 430*4882a593Smuzhiyun vin-supply = <&vcc3v3>; 431*4882a593Smuzhiyun }; 432*4882a593Smuzhiyun 433*4882a593Smuzhiyun vcc2v8: vcc-2v8 { 434*4882a593Smuzhiyun compatible = "regulator-fixed"; 435*4882a593Smuzhiyun regulator-name = "vcc2v8"; 436*4882a593Smuzhiyun regulator-always-on; 437*4882a593Smuzhiyun regulator-boot-on; 438*4882a593Smuzhiyun regulator-min-microvolt = <2800000>; 439*4882a593Smuzhiyun regulator-max-microvolt = <2800000>; 440*4882a593Smuzhiyun vin-supply = <&vcc3v3>; 441*4882a593Smuzhiyun }; 442*4882a593Smuzhiyun 443*4882a593Smuzhiyun vcc5v_lvds_en: vcc5v-lvds-en { 444*4882a593Smuzhiyun compatible = "regulator-fixed"; 445*4882a593Smuzhiyun regulator-name = "vcc5v_lvds_en"; 446*4882a593Smuzhiyun regulator-boot-on; 447*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 448*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 449*4882a593Smuzhiyun enable-active-high; 450*4882a593Smuzhiyun gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; 451*4882a593Smuzhiyun vin-supply = <&vcc5v0_sys>; 452*4882a593Smuzhiyun 453*4882a593Smuzhiyun regulator-state-mem { 454*4882a593Smuzhiyun regulator-off-in-suspend; 455*4882a593Smuzhiyun }; 456*4882a593Smuzhiyun }; 457*4882a593Smuzhiyun 458*4882a593Smuzhiyun vcc3v3_s: vcc-3v3-s { 459*4882a593Smuzhiyun compatible = "regulator-fixed"; 460*4882a593Smuzhiyun regulator-name = "vcc3v3_s"; 461*4882a593Smuzhiyun regulator-always-on; 462*4882a593Smuzhiyun regulator-boot-on; 463*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 464*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 465*4882a593Smuzhiyun gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; 466*4882a593Smuzhiyun vin-supply = <&vcc3v3>; 467*4882a593Smuzhiyun }; 468*4882a593Smuzhiyun 469*4882a593Smuzhiyun sdio_pwrseq: sdio-pwrseq { 470*4882a593Smuzhiyun compatible = "mmc-pwrseq-simple"; 471*4882a593Smuzhiyun clocks = <&rk809 1>; 472*4882a593Smuzhiyun clock-names = "ext_clock"; 473*4882a593Smuzhiyun 474*4882a593Smuzhiyun /* 475*4882a593Smuzhiyun * On the module itself this is one of these (depending 476*4882a593Smuzhiyun * on the actual card populated): 477*4882a593Smuzhiyun * - SDIO_RESET_L_WL_REG_ON 478*4882a593Smuzhiyun * - PDN (power down when low) 479*4882a593Smuzhiyun */ 480*4882a593Smuzhiyun post-power-on-delay-ms = <200>; 481*4882a593Smuzhiyun reset-gpios = <&extio EXTIO_GPIO_P27 GPIO_ACTIVE_LOW>; 482*4882a593Smuzhiyun }; 483*4882a593Smuzhiyun 484*4882a593Smuzhiyun vcc2v5_sys: vcc2v5-ddr { 485*4882a593Smuzhiyun compatible = "regulator-fixed"; 486*4882a593Smuzhiyun regulator-name = "vcc2v5-sys"; 487*4882a593Smuzhiyun regulator-always-on; 488*4882a593Smuzhiyun regulator-boot-on; 489*4882a593Smuzhiyun regulator-min-microvolt = <2500000>; 490*4882a593Smuzhiyun regulator-max-microvolt = <2500000>; 491*4882a593Smuzhiyun vin-supply = <&vcc3v3_sys>; 492*4882a593Smuzhiyun }; 493*4882a593Smuzhiyun 494*4882a593Smuzhiyun 4g-rst { 495*4882a593Smuzhiyun compatible = "regulator-fixed"; 496*4882a593Smuzhiyun regulator-name = "4g-rst"; 497*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 498*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 499*4882a593Smuzhiyun gpio = <&extio EXTIO_GPIO_P14 GPIO_ACTIVE_LOW>; 500*4882a593Smuzhiyun enable-active-low; 501*4882a593Smuzhiyun regulator-boot-on; 502*4882a593Smuzhiyun regulator-always-on; 503*4882a593Smuzhiyun status = "okay"; 504*4882a593Smuzhiyun }; 505*4882a593Smuzhiyun 506*4882a593Smuzhiyun 4g-pwr { 507*4882a593Smuzhiyun compatible = "regulator-fixed"; 508*4882a593Smuzhiyun regulator-name = "4g-pwr"; 509*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 510*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 511*4882a593Smuzhiyun gpio = <&extio EXTIO_GPIO_P11 GPIO_ACTIVE_HIGH>; 512*4882a593Smuzhiyun enable-active-high; 513*4882a593Smuzhiyun regulator-boot-on; 514*4882a593Smuzhiyun regulator-always-on; 515*4882a593Smuzhiyun status = "okay"; 516*4882a593Smuzhiyun }; 517*4882a593Smuzhiyun 518*4882a593Smuzhiyun debug: debug@fd904000 { 519*4882a593Smuzhiyun compatible = "rockchip,debug"; 520*4882a593Smuzhiyun reg = <0x0 0xfd904000 0x0 0x1000>, 521*4882a593Smuzhiyun <0x0 0xfd905000 0x0 0x1000>, 522*4882a593Smuzhiyun <0x0 0xfd906000 0x0 0x1000>, 523*4882a593Smuzhiyun <0x0 0xfd907000 0x0 0x1000>; 524*4882a593Smuzhiyun }; 525*4882a593Smuzhiyun 526*4882a593Smuzhiyun cspmu: cspmu@fd90c000 { 527*4882a593Smuzhiyun compatible = "rockchip,cspmu"; 528*4882a593Smuzhiyun reg = <0x0 0xfd90c000 0x0 0x1000>, 529*4882a593Smuzhiyun <0x0 0xfd90d000 0x0 0x1000>, 530*4882a593Smuzhiyun <0x0 0xfd90e000 0x0 0x1000>, 531*4882a593Smuzhiyun <0x0 0xfd90f000 0x0 0x1000>; 532*4882a593Smuzhiyun }; 533*4882a593Smuzhiyun 534*4882a593Smuzhiyun adc_keys: adc-keys { 535*4882a593Smuzhiyun compatible = "adc-keys"; 536*4882a593Smuzhiyun io-channels = <&saradc 0>; 537*4882a593Smuzhiyun io-channel-names = "buttons"; 538*4882a593Smuzhiyun keyup-threshold-microvolt = <1800000>; 539*4882a593Smuzhiyun poll-interval = <100>; 540*4882a593Smuzhiyun 541*4882a593Smuzhiyun vol-up-key { 542*4882a593Smuzhiyun label = "volume up"; 543*4882a593Smuzhiyun linux,code = <KEY_VOLUMEUP>; 544*4882a593Smuzhiyun press-threshold-microvolt = <729000>; 545*4882a593Smuzhiyun }; 546*4882a593Smuzhiyun 547*4882a593Smuzhiyun vol-down-key { 548*4882a593Smuzhiyun label = "volume down"; 549*4882a593Smuzhiyun linux,code = <KEY_VOLUMEDOWN>; 550*4882a593Smuzhiyun press-threshold-microvolt = <1080000>; 551*4882a593Smuzhiyun }; 552*4882a593Smuzhiyun 553*4882a593Smuzhiyun menu-key { 554*4882a593Smuzhiyun label = "menu"; 555*4882a593Smuzhiyun linux,code = <KEY_MENU>; 556*4882a593Smuzhiyun press-threshold-microvolt = <1286000>; 557*4882a593Smuzhiyun }; 558*4882a593Smuzhiyun 559*4882a593Smuzhiyun enter-key { 560*4882a593Smuzhiyun label = "enter"; 561*4882a593Smuzhiyun linux,code = <KEY_ENTER>; 562*4882a593Smuzhiyun press-threshold-microvolt = <1409000>; 563*4882a593Smuzhiyun }; 564*4882a593Smuzhiyun 565*4882a593Smuzhiyun home-key { 566*4882a593Smuzhiyun label = "home"; 567*4882a593Smuzhiyun linux,code = <KEY_HOME>; 568*4882a593Smuzhiyun press-threshold-microvolt = <1495000>; 569*4882a593Smuzhiyun }; 570*4882a593Smuzhiyun }; 571*4882a593Smuzhiyun 572*4882a593Smuzhiyun wakeup-keys { 573*4882a593Smuzhiyun compatible = "gpio-keys"; 574*4882a593Smuzhiyun pinctrl-names = "default"; 575*4882a593Smuzhiyun pinctrl-0 = <&wakeup_keys>; 576*4882a593Smuzhiyun 577*4882a593Smuzhiyun wakeup-k6 { 578*4882a593Smuzhiyun label = "wakeup"; 579*4882a593Smuzhiyun linux,code = <KEY_WAKEUP>; 580*4882a593Smuzhiyun gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_LOW>; 581*4882a593Smuzhiyun gpio-key,wakeup; 582*4882a593Smuzhiyun }; 583*4882a593Smuzhiyun }; 584*4882a593Smuzhiyun 585*4882a593Smuzhiyun fiq-debugger { 586*4882a593Smuzhiyun compatible = "rockchip,fiq-debugger"; 587*4882a593Smuzhiyun rockchip,serial-id = <2>; 588*4882a593Smuzhiyun rockchip,wake-irq = <0>; 589*4882a593Smuzhiyun /* If enable uart uses irq instead of fiq */ 590*4882a593Smuzhiyun rockchip,irq-mode-enable = <1>; 591*4882a593Smuzhiyun rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ 592*4882a593Smuzhiyun interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_LOW>; 593*4882a593Smuzhiyun pinctrl-names = "default"; 594*4882a593Smuzhiyun pinctrl-0 = <&uart2m0_xfer>; 595*4882a593Smuzhiyun status = "okay"; 596*4882a593Smuzhiyun }; 597*4882a593Smuzhiyun 598*4882a593Smuzhiyun ext_cam_clk: external-camera-clock { 599*4882a593Smuzhiyun compatible = "fixed-clock"; 600*4882a593Smuzhiyun clock-frequency = <24000000>; 601*4882a593Smuzhiyun clock-output-names = "CLK_CAMERA_24MHZ"; 602*4882a593Smuzhiyun #clock-cells = <0>; 603*4882a593Smuzhiyun }; 604*4882a593Smuzhiyun}; 605*4882a593Smuzhiyun 606*4882a593Smuzhiyun&reserved_memory { 607*4882a593Smuzhiyun ramoops: ramoops@110000 { 608*4882a593Smuzhiyun compatible = "ramoops"; 609*4882a593Smuzhiyun reg = <0x0 0x110000 0x0 0xf0000>; 610*4882a593Smuzhiyun record-size = <0x20000>; 611*4882a593Smuzhiyun console-size = <0x80000>; 612*4882a593Smuzhiyun ftrace-size = <0x00000>; 613*4882a593Smuzhiyun pmsg-size = <0x50000>; 614*4882a593Smuzhiyun }; 615*4882a593Smuzhiyun}; 616*4882a593Smuzhiyun 617*4882a593Smuzhiyun&rng { 618*4882a593Smuzhiyun status = "okay"; 619*4882a593Smuzhiyun}; 620*4882a593Smuzhiyun 621*4882a593Smuzhiyun&rockchip_suspend { 622*4882a593Smuzhiyun status = "okay"; 623*4882a593Smuzhiyun}; 624*4882a593Smuzhiyun 625*4882a593Smuzhiyun&bus_npu { 626*4882a593Smuzhiyun bus-supply = <&vdd_logic>; 627*4882a593Smuzhiyun pvtm-supply = <&vdd_cpu>; 628*4882a593Smuzhiyun status = "okay"; 629*4882a593Smuzhiyun}; 630*4882a593Smuzhiyun 631*4882a593Smuzhiyun&cpu0 { 632*4882a593Smuzhiyun cpu-supply = <&vdd_cpu>; 633*4882a593Smuzhiyun}; 634*4882a593Smuzhiyun 635*4882a593Smuzhiyun&dfi { 636*4882a593Smuzhiyun status = "okay"; 637*4882a593Smuzhiyun}; 638*4882a593Smuzhiyun 639*4882a593Smuzhiyun&dmc { 640*4882a593Smuzhiyun center-supply = <&vdd_logic>; 641*4882a593Smuzhiyun status = "okay"; 642*4882a593Smuzhiyun}; 643*4882a593Smuzhiyun 644*4882a593Smuzhiyun&gpu { 645*4882a593Smuzhiyun mali-supply = <&vdd_gpu>; 646*4882a593Smuzhiyun status = "okay"; 647*4882a593Smuzhiyun}; 648*4882a593Smuzhiyun 649*4882a593Smuzhiyun&i2c0 { 650*4882a593Smuzhiyun status = "okay"; 651*4882a593Smuzhiyun 652*4882a593Smuzhiyun vdd_cpu: tcs4525@1c { 653*4882a593Smuzhiyun compatible = "tcs,tcs452x"; 654*4882a593Smuzhiyun reg = <0x1c>; 655*4882a593Smuzhiyun vin-supply = <&vcc5v0_sys>; 656*4882a593Smuzhiyun regulator-compatible = "fan53555-reg"; 657*4882a593Smuzhiyun regulator-name = "vdd_cpu"; 658*4882a593Smuzhiyun regulator-min-microvolt = <712500>; 659*4882a593Smuzhiyun regulator-max-microvolt = <1390000>; 660*4882a593Smuzhiyun regulator-init-microvolt = <900000>; 661*4882a593Smuzhiyun regulator-ramp-delay = <2300>; 662*4882a593Smuzhiyun fcs,suspend-voltage-selector = <1>; 663*4882a593Smuzhiyun regulator-boot-on; 664*4882a593Smuzhiyun regulator-always-on; 665*4882a593Smuzhiyun regulator-state-mem { 666*4882a593Smuzhiyun regulator-off-in-suspend; 667*4882a593Smuzhiyun }; 668*4882a593Smuzhiyun }; 669*4882a593Smuzhiyun 670*4882a593Smuzhiyun rk809: pmic@20 { 671*4882a593Smuzhiyun compatible = "rockchip,rk809"; 672*4882a593Smuzhiyun reg = <0x20>; 673*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 674*4882a593Smuzhiyun interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 675*4882a593Smuzhiyun 676*4882a593Smuzhiyun pinctrl-names = "default", "pmic-sleep", 677*4882a593Smuzhiyun "pmic-power-off", "pmic-reset"; 678*4882a593Smuzhiyun pinctrl-0 = <&pmic_int>; 679*4882a593Smuzhiyun pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; 680*4882a593Smuzhiyun pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; 681*4882a593Smuzhiyun pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; 682*4882a593Smuzhiyun 683*4882a593Smuzhiyun rockchip,system-power-controller; 684*4882a593Smuzhiyun wakeup-source; 685*4882a593Smuzhiyun #clock-cells = <1>; 686*4882a593Smuzhiyun clock-output-names = "rk808-clkout1", "rk808-clkout2"; 687*4882a593Smuzhiyun //fb-inner-reg-idxs = <2>; 688*4882a593Smuzhiyun /* 1: rst regs (default in codes), 0: rst the pmic */ 689*4882a593Smuzhiyun pmic-reset-func = <0>; 690*4882a593Smuzhiyun /* not save the PMIC_POWER_EN register in uboot */ 691*4882a593Smuzhiyun not-save-power-en = <1>; 692*4882a593Smuzhiyun 693*4882a593Smuzhiyun vcc1-supply = <&vcc3v3_sys>; 694*4882a593Smuzhiyun vcc2-supply = <&vcc3v3_sys>; 695*4882a593Smuzhiyun vcc3-supply = <&vcc3v3_sys>; 696*4882a593Smuzhiyun vcc4-supply = <&vcc3v3_sys>; 697*4882a593Smuzhiyun vcc5-supply = <&vcc3v3_sys>; 698*4882a593Smuzhiyun vcc6-supply = <&vcc3v3_sys>; 699*4882a593Smuzhiyun vcc7-supply = <&vcc3v3_sys>; 700*4882a593Smuzhiyun vcc8-supply = <&vcc3v3_sys>; 701*4882a593Smuzhiyun vcc9-supply = <&vcc3v3_sys>; 702*4882a593Smuzhiyun 703*4882a593Smuzhiyun pwrkey { 704*4882a593Smuzhiyun status = "okay"; 705*4882a593Smuzhiyun }; 706*4882a593Smuzhiyun 707*4882a593Smuzhiyun pinctrl_rk8xx: pinctrl_rk8xx { 708*4882a593Smuzhiyun gpio-controller; 709*4882a593Smuzhiyun #gpio-cells = <2>; 710*4882a593Smuzhiyun 711*4882a593Smuzhiyun rk817_slppin_null: rk817_slppin_null { 712*4882a593Smuzhiyun pins = "gpio_slp"; 713*4882a593Smuzhiyun function = "pin_fun0"; 714*4882a593Smuzhiyun }; 715*4882a593Smuzhiyun 716*4882a593Smuzhiyun rk817_slppin_slp: rk817_slppin_slp { 717*4882a593Smuzhiyun pins = "gpio_slp"; 718*4882a593Smuzhiyun function = "pin_fun1"; 719*4882a593Smuzhiyun }; 720*4882a593Smuzhiyun 721*4882a593Smuzhiyun rk817_slppin_pwrdn: rk817_slppin_pwrdn { 722*4882a593Smuzhiyun pins = "gpio_slp"; 723*4882a593Smuzhiyun function = "pin_fun2"; 724*4882a593Smuzhiyun }; 725*4882a593Smuzhiyun 726*4882a593Smuzhiyun rk817_slppin_rst: rk817_slppin_rst { 727*4882a593Smuzhiyun pins = "gpio_slp"; 728*4882a593Smuzhiyun function = "pin_fun3"; 729*4882a593Smuzhiyun }; 730*4882a593Smuzhiyun }; 731*4882a593Smuzhiyun 732*4882a593Smuzhiyun regulators { 733*4882a593Smuzhiyun vdd_logic: DCDC_REG1 { 734*4882a593Smuzhiyun regulator-always-on; 735*4882a593Smuzhiyun regulator-boot-on; 736*4882a593Smuzhiyun regulator-min-microvolt = <500000>; 737*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 738*4882a593Smuzhiyun regulator-init-microvolt = <900000>; 739*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 740*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 741*4882a593Smuzhiyun regulator-name = "vdd_logic"; 742*4882a593Smuzhiyun regulator-state-mem { 743*4882a593Smuzhiyun regulator-off-in-suspend; 744*4882a593Smuzhiyun }; 745*4882a593Smuzhiyun }; 746*4882a593Smuzhiyun 747*4882a593Smuzhiyun vdd_gpu: DCDC_REG2 { 748*4882a593Smuzhiyun regulator-always-on; 749*4882a593Smuzhiyun regulator-boot-on; 750*4882a593Smuzhiyun regulator-min-microvolt = <500000>; 751*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 752*4882a593Smuzhiyun regulator-init-microvolt = <900000>; 753*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 754*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 755*4882a593Smuzhiyun regulator-name = "vdd_gpu"; 756*4882a593Smuzhiyun regulator-state-mem { 757*4882a593Smuzhiyun regulator-off-in-suspend; 758*4882a593Smuzhiyun }; 759*4882a593Smuzhiyun }; 760*4882a593Smuzhiyun 761*4882a593Smuzhiyun vcc_ddr: DCDC_REG3 { 762*4882a593Smuzhiyun regulator-always-on; 763*4882a593Smuzhiyun regulator-boot-on; 764*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 765*4882a593Smuzhiyun regulator-name = "vcc_ddr"; 766*4882a593Smuzhiyun regulator-state-mem { 767*4882a593Smuzhiyun regulator-on-in-suspend; 768*4882a593Smuzhiyun }; 769*4882a593Smuzhiyun }; 770*4882a593Smuzhiyun 771*4882a593Smuzhiyun vdd_npu: DCDC_REG4 { 772*4882a593Smuzhiyun regulator-always-on; 773*4882a593Smuzhiyun regulator-boot-on; 774*4882a593Smuzhiyun regulator-min-microvolt = <500000>; 775*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 776*4882a593Smuzhiyun regulator-init-microvolt = <900000>; 777*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 778*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 779*4882a593Smuzhiyun regulator-name = "vdd_npu"; 780*4882a593Smuzhiyun regulator-state-mem { 781*4882a593Smuzhiyun regulator-off-in-suspend; 782*4882a593Smuzhiyun }; 783*4882a593Smuzhiyun }; 784*4882a593Smuzhiyun 785*4882a593Smuzhiyun vdda0v9_image: LDO_REG1 { 786*4882a593Smuzhiyun regulator-boot-on; 787*4882a593Smuzhiyun regulator-always-on; 788*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 789*4882a593Smuzhiyun regulator-max-microvolt = <900000>; 790*4882a593Smuzhiyun regulator-name = "vdda0v9_image"; 791*4882a593Smuzhiyun regulator-state-mem { 792*4882a593Smuzhiyun regulator-off-in-suspend; 793*4882a593Smuzhiyun }; 794*4882a593Smuzhiyun }; 795*4882a593Smuzhiyun 796*4882a593Smuzhiyun vdda_0v9: LDO_REG2 { 797*4882a593Smuzhiyun regulator-always-on; 798*4882a593Smuzhiyun regulator-boot-on; 799*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 800*4882a593Smuzhiyun regulator-max-microvolt = <900000>; 801*4882a593Smuzhiyun regulator-name = "vdda_0v9"; 802*4882a593Smuzhiyun regulator-state-mem { 803*4882a593Smuzhiyun regulator-off-in-suspend; 804*4882a593Smuzhiyun }; 805*4882a593Smuzhiyun }; 806*4882a593Smuzhiyun 807*4882a593Smuzhiyun vdda0v9_pmu: LDO_REG3 { 808*4882a593Smuzhiyun regulator-always-on; 809*4882a593Smuzhiyun regulator-boot-on; 810*4882a593Smuzhiyun regulator-min-microvolt = <900000>; 811*4882a593Smuzhiyun regulator-max-microvolt = <900000>; 812*4882a593Smuzhiyun regulator-name = "vdda0v9_pmu"; 813*4882a593Smuzhiyun regulator-state-mem { 814*4882a593Smuzhiyun regulator-on-in-suspend; 815*4882a593Smuzhiyun regulator-suspend-microvolt = <900000>; 816*4882a593Smuzhiyun }; 817*4882a593Smuzhiyun }; 818*4882a593Smuzhiyun 819*4882a593Smuzhiyun vccio_acodec: LDO_REG4 { 820*4882a593Smuzhiyun regulator-always-on; 821*4882a593Smuzhiyun regulator-boot-on; 822*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 823*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 824*4882a593Smuzhiyun regulator-name = "vccio_acodec"; 825*4882a593Smuzhiyun regulator-state-mem { 826*4882a593Smuzhiyun regulator-off-in-suspend; 827*4882a593Smuzhiyun }; 828*4882a593Smuzhiyun }; 829*4882a593Smuzhiyun 830*4882a593Smuzhiyun vccio_sd: LDO_REG5 { 831*4882a593Smuzhiyun regulator-always-on; 832*4882a593Smuzhiyun regulator-boot-on; 833*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 834*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 835*4882a593Smuzhiyun regulator-name = "vccio_sd"; 836*4882a593Smuzhiyun regulator-state-mem { 837*4882a593Smuzhiyun regulator-off-in-suspend; 838*4882a593Smuzhiyun }; 839*4882a593Smuzhiyun }; 840*4882a593Smuzhiyun 841*4882a593Smuzhiyun vcc3v3_pmu: LDO_REG6 { 842*4882a593Smuzhiyun regulator-always-on; 843*4882a593Smuzhiyun regulator-boot-on; 844*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 845*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 846*4882a593Smuzhiyun regulator-name = "vcc3v3_pmu"; 847*4882a593Smuzhiyun regulator-state-mem { 848*4882a593Smuzhiyun regulator-on-in-suspend; 849*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 850*4882a593Smuzhiyun }; 851*4882a593Smuzhiyun }; 852*4882a593Smuzhiyun 853*4882a593Smuzhiyun vcca_1v8: LDO_REG7 { 854*4882a593Smuzhiyun regulator-always-on; 855*4882a593Smuzhiyun regulator-boot-on; 856*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 857*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 858*4882a593Smuzhiyun regulator-name = "vcca_1v8"; 859*4882a593Smuzhiyun regulator-state-mem { 860*4882a593Smuzhiyun regulator-off-in-suspend; 861*4882a593Smuzhiyun }; 862*4882a593Smuzhiyun }; 863*4882a593Smuzhiyun 864*4882a593Smuzhiyun vcca1v8_pmu: LDO_REG8 { 865*4882a593Smuzhiyun regulator-always-on; 866*4882a593Smuzhiyun regulator-boot-on; 867*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 868*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 869*4882a593Smuzhiyun regulator-name = "vcca1v8_pmu"; 870*4882a593Smuzhiyun regulator-state-mem { 871*4882a593Smuzhiyun regulator-on-in-suspend; 872*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 873*4882a593Smuzhiyun }; 874*4882a593Smuzhiyun }; 875*4882a593Smuzhiyun 876*4882a593Smuzhiyun vcca1v8_image: LDO_REG9 { 877*4882a593Smuzhiyun regulator-always-on; 878*4882a593Smuzhiyun regulator-boot-on; 879*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 880*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 881*4882a593Smuzhiyun regulator-name = "vcca1v8_image"; 882*4882a593Smuzhiyun regulator-state-mem { 883*4882a593Smuzhiyun regulator-off-in-suspend; 884*4882a593Smuzhiyun }; 885*4882a593Smuzhiyun }; 886*4882a593Smuzhiyun 887*4882a593Smuzhiyun vcc_1v8: DCDC_REG5 { 888*4882a593Smuzhiyun regulator-always-on; 889*4882a593Smuzhiyun regulator-boot-on; 890*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 891*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 892*4882a593Smuzhiyun regulator-name = "vcc_1v8"; 893*4882a593Smuzhiyun regulator-state-mem { 894*4882a593Smuzhiyun regulator-off-in-suspend; 895*4882a593Smuzhiyun }; 896*4882a593Smuzhiyun }; 897*4882a593Smuzhiyun 898*4882a593Smuzhiyun vcc_3v3: SWITCH_REG1 { 899*4882a593Smuzhiyun regulator-always-on; 900*4882a593Smuzhiyun regulator-boot-on; 901*4882a593Smuzhiyun regulator-name = "vcc_3v3"; 902*4882a593Smuzhiyun regulator-state-mem { 903*4882a593Smuzhiyun regulator-off-in-suspend; 904*4882a593Smuzhiyun }; 905*4882a593Smuzhiyun }; 906*4882a593Smuzhiyun 907*4882a593Smuzhiyun vcc3v3_sd: SWITCH_REG2 { 908*4882a593Smuzhiyun regulator-always-on; 909*4882a593Smuzhiyun regulator-boot-on; 910*4882a593Smuzhiyun regulator-name = "vcc3v3_sd"; 911*4882a593Smuzhiyun regulator-state-mem { 912*4882a593Smuzhiyun regulator-off-in-suspend; 913*4882a593Smuzhiyun }; 914*4882a593Smuzhiyun }; 915*4882a593Smuzhiyun }; 916*4882a593Smuzhiyun 917*4882a593Smuzhiyun rk809_codec: codec { 918*4882a593Smuzhiyun #sound-dai-cells = <0>; 919*4882a593Smuzhiyun compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; 920*4882a593Smuzhiyun clocks = <&cru I2S1_MCLKOUT>; 921*4882a593Smuzhiyun clock-names = "mclk"; 922*4882a593Smuzhiyun assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; 923*4882a593Smuzhiyun assigned-clock-rates = <12288000>; 924*4882a593Smuzhiyun assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; 925*4882a593Smuzhiyun pinctrl-names = "default"; 926*4882a593Smuzhiyun pinctrl-0 = <&i2s1m0_mclk>; 927*4882a593Smuzhiyun hp-volume = <3>; 928*4882a593Smuzhiyun spk-volume = <3>; 929*4882a593Smuzhiyun mic-in-differential; 930*4882a593Smuzhiyun status = "okay"; 931*4882a593Smuzhiyun }; 932*4882a593Smuzhiyun }; 933*4882a593Smuzhiyun}; 934*4882a593Smuzhiyun 935*4882a593Smuzhiyun&i2s0_8ch { 936*4882a593Smuzhiyun status = "okay"; 937*4882a593Smuzhiyun}; 938*4882a593Smuzhiyun 939*4882a593Smuzhiyun&i2s1_8ch { 940*4882a593Smuzhiyun status = "okay"; 941*4882a593Smuzhiyun rockchip,clk-trcm = <1>; 942*4882a593Smuzhiyun pinctrl-names = "default"; 943*4882a593Smuzhiyun pinctrl-0 = <&i2s1m0_sclktx 944*4882a593Smuzhiyun &i2s1m0_lrcktx 945*4882a593Smuzhiyun &i2s1m0_sdi0 946*4882a593Smuzhiyun &i2s1m0_sdo0>; 947*4882a593Smuzhiyun}; 948*4882a593Smuzhiyun 949*4882a593Smuzhiyun&iep { 950*4882a593Smuzhiyun status = "okay"; 951*4882a593Smuzhiyun}; 952*4882a593Smuzhiyun 953*4882a593Smuzhiyun&iep_mmu { 954*4882a593Smuzhiyun status = "okay"; 955*4882a593Smuzhiyun}; 956*4882a593Smuzhiyun 957*4882a593Smuzhiyun&jpegd { 958*4882a593Smuzhiyun status = "okay"; 959*4882a593Smuzhiyun}; 960*4882a593Smuzhiyun 961*4882a593Smuzhiyun&jpegd_mmu { 962*4882a593Smuzhiyun status = "okay"; 963*4882a593Smuzhiyun}; 964*4882a593Smuzhiyun 965*4882a593Smuzhiyun&mpp_srv { 966*4882a593Smuzhiyun status = "okay"; 967*4882a593Smuzhiyun}; 968*4882a593Smuzhiyun 969*4882a593Smuzhiyun&nandc0 { 970*4882a593Smuzhiyun #address-cells = <1>; 971*4882a593Smuzhiyun #size-cells = <0>; 972*4882a593Smuzhiyun status = "okay"; 973*4882a593Smuzhiyun 974*4882a593Smuzhiyun nand@0 { 975*4882a593Smuzhiyun reg = <0>; 976*4882a593Smuzhiyun nand-bus-width = <8>; 977*4882a593Smuzhiyun nand-ecc-mode = "hw"; 978*4882a593Smuzhiyun nand-ecc-strength = <16>; 979*4882a593Smuzhiyun nand-ecc-step-size = <1024>; 980*4882a593Smuzhiyun }; 981*4882a593Smuzhiyun}; 982*4882a593Smuzhiyun 983*4882a593Smuzhiyun /* 984*4882a593Smuzhiyun * There are 10 independent IO domains in RK3566/RK3568, including PMUIO[0:2] and VCCIO[1:7]. 985*4882a593Smuzhiyun * 1/ PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured; 986*4882a593Smuzhiyun * 2/ PMUIO2 and VCCIO1,VCCIO[3:7] domains require that their hardware power supply voltages 987*4882a593Smuzhiyun * must be consistent with the software configuration correspondingly 988*4882a593Smuzhiyun * a/ When the hardware IO level is connected to 1.8V, the software voltage configuration 989*4882a593Smuzhiyun * should also be configured to 1.8V accordingly; 990*4882a593Smuzhiyun * b/ When the hardware IO level is connected to 3.3V, the software voltage configuration 991*4882a593Smuzhiyun * should also be configured to 3.3V accordingly; 992*4882a593Smuzhiyun * 3/ VCCIO2 voltage control selection (0xFDC20140) 993*4882a593Smuzhiyun * BIT[0]: 0x0: from GPIO_0A7 (default) 994*4882a593Smuzhiyun * BIT[0]: 0x1: from GRF 995*4882a593Smuzhiyun * Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7: 996*4882a593Smuzhiyun * L:VCCIO2 must supply 3.3V 997*4882a593Smuzhiyun * H:VCCIO2 must supply 1.8V 998*4882a593Smuzhiyun */ 999*4882a593Smuzhiyun&pmu_io_domains { 1000*4882a593Smuzhiyun status = "okay"; 1001*4882a593Smuzhiyun pmuio1-supply = <&vcc3v3_pmu>; 1002*4882a593Smuzhiyun pmuio2-supply = <&vcc3v3_pmu>; 1003*4882a593Smuzhiyun vccio1-supply = <&vccio_acodec>; 1004*4882a593Smuzhiyun vccio3-supply = <&vccio_sd>; 1005*4882a593Smuzhiyun vccio4-supply = <&vcc_1v8>; 1006*4882a593Smuzhiyun vccio5-supply = <&vcc_3v3>; 1007*4882a593Smuzhiyun vccio6-supply = <&vcc_1v8>; 1008*4882a593Smuzhiyun vccio7-supply = <&vcc_3v3>; 1009*4882a593Smuzhiyun}; 1010*4882a593Smuzhiyun 1011*4882a593Smuzhiyun&rk_rga { 1012*4882a593Smuzhiyun status = "okay"; 1013*4882a593Smuzhiyun}; 1014*4882a593Smuzhiyun 1015*4882a593Smuzhiyun&rkvdec { 1016*4882a593Smuzhiyun status = "okay"; 1017*4882a593Smuzhiyun}; 1018*4882a593Smuzhiyun 1019*4882a593Smuzhiyun&rkvdec_mmu { 1020*4882a593Smuzhiyun status = "okay"; 1021*4882a593Smuzhiyun}; 1022*4882a593Smuzhiyun 1023*4882a593Smuzhiyun&rkvenc { 1024*4882a593Smuzhiyun venc-supply = <&vdd_logic>; 1025*4882a593Smuzhiyun status = "okay"; 1026*4882a593Smuzhiyun}; 1027*4882a593Smuzhiyun 1028*4882a593Smuzhiyun&rkvenc_mmu { 1029*4882a593Smuzhiyun status = "okay"; 1030*4882a593Smuzhiyun}; 1031*4882a593Smuzhiyun 1032*4882a593Smuzhiyun&rknpu { 1033*4882a593Smuzhiyun rknpu-supply = <&vdd_npu>; 1034*4882a593Smuzhiyun status = "okay"; 1035*4882a593Smuzhiyun}; 1036*4882a593Smuzhiyun 1037*4882a593Smuzhiyun&rknpu_mmu { 1038*4882a593Smuzhiyun status = "okay"; 1039*4882a593Smuzhiyun}; 1040*4882a593Smuzhiyun 1041*4882a593Smuzhiyun&sdhci { 1042*4882a593Smuzhiyun bus-width = <8>; 1043*4882a593Smuzhiyun supports-emmc; 1044*4882a593Smuzhiyun non-removable; 1045*4882a593Smuzhiyun max-frequency = <200000000>; 1046*4882a593Smuzhiyun status = "okay"; 1047*4882a593Smuzhiyun}; 1048*4882a593Smuzhiyun 1049*4882a593Smuzhiyun&sfc { 1050*4882a593Smuzhiyun status = "okay"; 1051*4882a593Smuzhiyun pinctrl-names = "default"; 1052*4882a593Smuzhiyun pinctrl-0 = <&fspi_pins>; 1053*4882a593Smuzhiyun flash: m25p80@0 { 1054*4882a593Smuzhiyun #address-cells = <1>; 1055*4882a593Smuzhiyun #size-cells = <1>; 1056*4882a593Smuzhiyun compatible = "spansion,m25p80", "jedec,spi-nor"; 1057*4882a593Smuzhiyun reg = <0>; 1058*4882a593Smuzhiyun spi-max-frequency = <40000000>; 1059*4882a593Smuzhiyun m25p,fast-read; 1060*4882a593Smuzhiyun }; 1061*4882a593Smuzhiyun}; 1062*4882a593Smuzhiyun 1063*4882a593Smuzhiyun&spdif_8ch { 1064*4882a593Smuzhiyun status = "disabled"; 1065*4882a593Smuzhiyun pinctrl-names = "default"; 1066*4882a593Smuzhiyun pinctrl-0 = <&spdifm1_tx>; 1067*4882a593Smuzhiyun}; 1068*4882a593Smuzhiyun 1069*4882a593Smuzhiyun&tsadc { 1070*4882a593Smuzhiyun status = "okay"; 1071*4882a593Smuzhiyun}; 1072*4882a593Smuzhiyun 1073*4882a593Smuzhiyun&vad { 1074*4882a593Smuzhiyun rockchip,audio-src = <&i2s1_8ch>; 1075*4882a593Smuzhiyun rockchip,buffer-time-ms = <128>; 1076*4882a593Smuzhiyun rockchip,det-channel = <0>; 1077*4882a593Smuzhiyun rockchip,mode = <0>; 1078*4882a593Smuzhiyun}; 1079*4882a593Smuzhiyun 1080*4882a593Smuzhiyun&vdpu { 1081*4882a593Smuzhiyun status = "okay"; 1082*4882a593Smuzhiyun}; 1083*4882a593Smuzhiyun 1084*4882a593Smuzhiyun&vdpu_mmu { 1085*4882a593Smuzhiyun status = "okay"; 1086*4882a593Smuzhiyun}; 1087*4882a593Smuzhiyun 1088*4882a593Smuzhiyun&vepu { 1089*4882a593Smuzhiyun status = "okay"; 1090*4882a593Smuzhiyun}; 1091*4882a593Smuzhiyun 1092*4882a593Smuzhiyun&vepu_mmu { 1093*4882a593Smuzhiyun status = "okay"; 1094*4882a593Smuzhiyun}; 1095*4882a593Smuzhiyun 1096*4882a593Smuzhiyun&xin32k { 1097*4882a593Smuzhiyun status = "disabled"; 1098*4882a593Smuzhiyun}; 1099*4882a593Smuzhiyun 1100*4882a593Smuzhiyun/* TF card */ 1101*4882a593Smuzhiyun&sdmmc0 { 1102*4882a593Smuzhiyun max-frequency = <150000000>; 1103*4882a593Smuzhiyun supports-sd; 1104*4882a593Smuzhiyun bus-width = <4>; 1105*4882a593Smuzhiyun cap-mmc-highspeed; 1106*4882a593Smuzhiyun cap-sd-highspeed; 1107*4882a593Smuzhiyun disable-wp; 1108*4882a593Smuzhiyun sd-uhs-sdr104; 1109*4882a593Smuzhiyun vmmc-supply = <&vcc3v3_sd>; 1110*4882a593Smuzhiyun vqmmc-supply = <&vccio_sd>; 1111*4882a593Smuzhiyun pinctrl-names = "default"; 1112*4882a593Smuzhiyun pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; 1113*4882a593Smuzhiyun status = "okay"; 1114*4882a593Smuzhiyun}; 1115*4882a593Smuzhiyun 1116*4882a593Smuzhiyun/* WIFI */ 1117*4882a593Smuzhiyun&sdmmc2 { 1118*4882a593Smuzhiyun max-frequency = <150000000>; 1119*4882a593Smuzhiyun supports-sdio; 1120*4882a593Smuzhiyun bus-width = <4>; 1121*4882a593Smuzhiyun disable-wp; 1122*4882a593Smuzhiyun cap-sd-highspeed; 1123*4882a593Smuzhiyun cap-sdio-irq; 1124*4882a593Smuzhiyun keep-power-in-suspend; 1125*4882a593Smuzhiyun mmc-pwrseq = <&sdio_pwrseq>; 1126*4882a593Smuzhiyun non-removable; 1127*4882a593Smuzhiyun pinctrl-names = "default"; 1128*4882a593Smuzhiyun pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; 1129*4882a593Smuzhiyun sd-uhs-sdr104; 1130*4882a593Smuzhiyun status = "okay"; 1131*4882a593Smuzhiyun}; 1132*4882a593Smuzhiyun 1133*4882a593Smuzhiyun&saradc { 1134*4882a593Smuzhiyun status = "okay"; 1135*4882a593Smuzhiyun vref-supply = <&vcca_1v8>; 1136*4882a593Smuzhiyun}; 1137*4882a593Smuzhiyun 1138*4882a593Smuzhiyun/* TTL */ 1139*4882a593Smuzhiyun&uart0 { 1140*4882a593Smuzhiyun status = "okay"; 1141*4882a593Smuzhiyun}; 1142*4882a593Smuzhiyun 1143*4882a593Smuzhiyun/* Bluetooth */ 1144*4882a593Smuzhiyun&uart8 { 1145*4882a593Smuzhiyun status = "okay"; 1146*4882a593Smuzhiyun pinctrl-names = "default"; 1147*4882a593Smuzhiyun pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn &uart8m0_rtsn>; 1148*4882a593Smuzhiyun}; 1149*4882a593Smuzhiyun 1150*4882a593Smuzhiyun/* 485 */ 1151*4882a593Smuzhiyun&uart9 { 1152*4882a593Smuzhiyun status = "okay"; 1153*4882a593Smuzhiyun pinctrl-names = "default"; 1154*4882a593Smuzhiyun pinctrl-0 = <&uart9m1_xfer>; 1155*4882a593Smuzhiyun}; 1156*4882a593Smuzhiyun 1157*4882a593Smuzhiyun&can0 { 1158*4882a593Smuzhiyun assigned-clocks = <&cru CLK_CAN0>; 1159*4882a593Smuzhiyun assigned-clock-rates = <200000000>; 1160*4882a593Smuzhiyun pinctrl-names = "default"; 1161*4882a593Smuzhiyun pinctrl-0 = <&can0m0_pins>; 1162*4882a593Smuzhiyun status = "okay"; 1163*4882a593Smuzhiyun}; 1164*4882a593Smuzhiyun 1165*4882a593Smuzhiyun&can1 { 1166*4882a593Smuzhiyun assigned-clocks = <&cru CLK_CAN1>; 1167*4882a593Smuzhiyun assigned-clock-rates = <200000000>; 1168*4882a593Smuzhiyun pinctrl-names = "default"; 1169*4882a593Smuzhiyun pinctrl-0 = <&can1m1_pins>; 1170*4882a593Smuzhiyun status = "okay"; 1171*4882a593Smuzhiyun}; 1172*4882a593Smuzhiyun 1173*4882a593Smuzhiyun&gmac0 { 1174*4882a593Smuzhiyun phy-mode = "rgmii-rxid"; 1175*4882a593Smuzhiyun clock_in_out = "output"; 1176*4882a593Smuzhiyun 1177*4882a593Smuzhiyun snps,reset-gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; 1178*4882a593Smuzhiyun snps,reset-active-low; 1179*4882a593Smuzhiyun /* Reset time is 20ms, 100ms for rtl8211f */ 1180*4882a593Smuzhiyun snps,reset-delays-us = <0 20000 100000>; 1181*4882a593Smuzhiyun 1182*4882a593Smuzhiyun assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>, <&cru CLK_MAC0_OUT>; 1183*4882a593Smuzhiyun assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; 1184*4882a593Smuzhiyun assigned-clock-rates = <0>, <125000000>, <25000000>; 1185*4882a593Smuzhiyun 1186*4882a593Smuzhiyun pinctrl-names = "default"; 1187*4882a593Smuzhiyun pinctrl-0 = <&gmac0_miim 1188*4882a593Smuzhiyun &gmac0_tx_bus2 1189*4882a593Smuzhiyun &gmac0_rx_bus2 1190*4882a593Smuzhiyun &gmac0_rgmii_clk 1191*4882a593Smuzhiyun &gmac0_rgmii_bus>; 1192*4882a593Smuzhiyun 1193*4882a593Smuzhiyun tx_delay = <0x36>; 1194*4882a593Smuzhiyun/* rx_delay = <0x00>; */ 1195*4882a593Smuzhiyun 1196*4882a593Smuzhiyun phy-handle = <&rgmii_phy0>; 1197*4882a593Smuzhiyun status = "okay"; 1198*4882a593Smuzhiyun}; 1199*4882a593Smuzhiyun 1200*4882a593Smuzhiyun&gmac1 { 1201*4882a593Smuzhiyun phy-mode = "rgmii-rxid"; 1202*4882a593Smuzhiyun clock_in_out = "output"; 1203*4882a593Smuzhiyun 1204*4882a593Smuzhiyun snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; 1205*4882a593Smuzhiyun snps,reset-active-low; 1206*4882a593Smuzhiyun /* Reset time is 20ms, 100ms for rtl8211f */ 1207*4882a593Smuzhiyun snps,reset-delays-us = <0 20000 100000>; 1208*4882a593Smuzhiyun 1209*4882a593Smuzhiyun assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>, <&cru CLK_MAC1_OUT>; 1210*4882a593Smuzhiyun assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; 1211*4882a593Smuzhiyun assigned-clock-rates = <0>, <125000000>, <25000000>; 1212*4882a593Smuzhiyun 1213*4882a593Smuzhiyun pinctrl-names = "default"; 1214*4882a593Smuzhiyun pinctrl-0 = <&gmac1m1_miim 1215*4882a593Smuzhiyun &gmac1m1_tx_bus2 1216*4882a593Smuzhiyun &gmac1m1_rx_bus2 1217*4882a593Smuzhiyun &gmac1m1_rgmii_clk 1218*4882a593Smuzhiyun &gmac1m1_rgmii_bus>; 1219*4882a593Smuzhiyun 1220*4882a593Smuzhiyun tx_delay = <0x47>; 1221*4882a593Smuzhiyun/* rx_delay = <0x00>; */ 1222*4882a593Smuzhiyun 1223*4882a593Smuzhiyun phy-handle = <&rgmii_phy1>; 1224*4882a593Smuzhiyun status = "okay"; 1225*4882a593Smuzhiyun}; 1226*4882a593Smuzhiyun 1227*4882a593Smuzhiyun&mdio0 { 1228*4882a593Smuzhiyun rgmii_phy0: phy@0 { 1229*4882a593Smuzhiyun compatible = "ethernet-phy-ieee802.3-c22"; 1230*4882a593Smuzhiyun reg = <0x0>; 1231*4882a593Smuzhiyun clocks = <&cru CLK_MAC0_OUT>; 1232*4882a593Smuzhiyun }; 1233*4882a593Smuzhiyun}; 1234*4882a593Smuzhiyun 1235*4882a593Smuzhiyun&mdio1 { 1236*4882a593Smuzhiyun rgmii_phy1: phy@0 { 1237*4882a593Smuzhiyun compatible = "ethernet-phy-ieee802.3-c22"; 1238*4882a593Smuzhiyun reg = <0x0>; 1239*4882a593Smuzhiyun clocks = <&cru CLK_MAC1_OUT>; 1240*4882a593Smuzhiyun }; 1241*4882a593Smuzhiyun}; 1242*4882a593Smuzhiyun 1243*4882a593Smuzhiyun&i2c2 { 1244*4882a593Smuzhiyun pinctrl-0 = <&i2c2m1_xfer>; 1245*4882a593Smuzhiyun status = "okay"; 1246*4882a593Smuzhiyun 1247*4882a593Smuzhiyun extio: pcal6524@22 { 1248*4882a593Smuzhiyun compatible = "nxp,pcal6524"; 1249*4882a593Smuzhiyun reg = <0x22>; 1250*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 1251*4882a593Smuzhiyun interrupts = <RK_PA0 IRQ_TYPE_EDGE_FALLING>; 1252*4882a593Smuzhiyun gpio-controller; 1253*4882a593Smuzhiyun pinctrl-0 = <&extio_int_gpio>; 1254*4882a593Smuzhiyun pinctrl-names = "default"; 1255*4882a593Smuzhiyun #gpio-cells = <2>; 1256*4882a593Smuzhiyun interrupt-controller; 1257*4882a593Smuzhiyun #interrupt-cells = <2>; 1258*4882a593Smuzhiyun status = "okay"; 1259*4882a593Smuzhiyun }; 1260*4882a593Smuzhiyun 1261*4882a593Smuzhiyun rx8010: rx8010@32 { 1262*4882a593Smuzhiyun compatible = "epson,rx8010"; 1263*4882a593Smuzhiyun reg = <0x32>; 1264*4882a593Smuzhiyun status = "okay"; 1265*4882a593Smuzhiyun }; 1266*4882a593Smuzhiyun 1267*4882a593Smuzhiyun pcf8563: pcf8563@51 { 1268*4882a593Smuzhiyun compatible = "nxp,pcf8563"; 1269*4882a593Smuzhiyun reg = <0x51>; 1270*4882a593Smuzhiyun status = "okay"; 1271*4882a593Smuzhiyun }; 1272*4882a593Smuzhiyun 1273*4882a593Smuzhiyun gt9xx_rgb: gt9xx-rgb@14 { 1274*4882a593Smuzhiyun compatible = "goodix,gt928"; 1275*4882a593Smuzhiyun reg = <0x14>; 1276*4882a593Smuzhiyun interrupt-parent = <&extio>; 1277*4882a593Smuzhiyun interrupts = <EXTIO_GPIO_P03 IRQ_TYPE_EDGE_FALLING>; 1278*4882a593Smuzhiyun irq-gpio = <&extio EXTIO_GPIO_P03 GPIO_ACTIVE_HIGH>; 1279*4882a593Smuzhiyun reset-gpio = <&extio EXTIO_GPIO_P02 GPIO_ACTIVE_HIGH>; 1280*4882a593Smuzhiyun touchscreen-size-x = <800>; 1281*4882a593Smuzhiyun touchscreen-size-y = <480>; 1282*4882a593Smuzhiyun touchscreen-inverted-x; 1283*4882a593Smuzhiyun touchscreen-inverted-y; 1284*4882a593Smuzhiyun uniq = "rgb"; 1285*4882a593Smuzhiyun status = "okay"; 1286*4882a593Smuzhiyun }; 1287*4882a593Smuzhiyun 1288*4882a593Smuzhiyun tsc2007_rgb: tsc2007-rgb@48 { 1289*4882a593Smuzhiyun compatible = "ti,tsc2007"; 1290*4882a593Smuzhiyun reg = <0x48>; 1291*4882a593Smuzhiyun interrupt-parent = <&extio>; 1292*4882a593Smuzhiyun interrupts = <EXTIO_GPIO_P04 IRQ_TYPE_EDGE_FALLING>; 1293*4882a593Smuzhiyun irq-gpio = <&extio EXTIO_GPIO_P04 GPIO_ACTIVE_LOW>; 1294*4882a593Smuzhiyun ti,x-plate-ohms = <180>; 1295*4882a593Smuzhiyun status = "okay"; 1296*4882a593Smuzhiyun }; 1297*4882a593Smuzhiyun}; 1298*4882a593Smuzhiyun 1299*4882a593Smuzhiyun/* usb2 comb phy0 */ 1300*4882a593Smuzhiyun&usb2phy0 { 1301*4882a593Smuzhiyun status = "okay"; 1302*4882a593Smuzhiyun}; 1303*4882a593Smuzhiyun 1304*4882a593Smuzhiyun/* usb2 comb phy0 port0 */ 1305*4882a593Smuzhiyun&u2phy0_otg { 1306*4882a593Smuzhiyun status = "okay"; 1307*4882a593Smuzhiyun}; 1308*4882a593Smuzhiyun 1309*4882a593Smuzhiyun/* usb2 comb phy0 port1 */ 1310*4882a593Smuzhiyun&u2phy0_host { 1311*4882a593Smuzhiyun status = "okay"; 1312*4882a593Smuzhiyun}; 1313*4882a593Smuzhiyun 1314*4882a593Smuzhiyun/* USB 3.0 OTG/SATA Combo PHY_0 */ 1315*4882a593Smuzhiyun&combphy0_us { 1316*4882a593Smuzhiyun status = "okay"; 1317*4882a593Smuzhiyun}; 1318*4882a593Smuzhiyun 1319*4882a593Smuzhiyun/* USB 3.0 OTG controller */ 1320*4882a593Smuzhiyun&usbdrd30 { 1321*4882a593Smuzhiyun status = "okay"; 1322*4882a593Smuzhiyun}; 1323*4882a593Smuzhiyun 1324*4882a593Smuzhiyun&usbdrd_dwc3 { 1325*4882a593Smuzhiyun extcon = <&usb2phy0>; 1326*4882a593Smuzhiyun status = "okay"; 1327*4882a593Smuzhiyun}; 1328*4882a593Smuzhiyun 1329*4882a593Smuzhiyun/* USB 3.0 Host/SATA/QSGMII Combo PHY_1 */ 1330*4882a593Smuzhiyun&combphy1_usq { 1331*4882a593Smuzhiyun status = "okay"; 1332*4882a593Smuzhiyun}; 1333*4882a593Smuzhiyun 1334*4882a593Smuzhiyun/* USB 3.0 Host_1 controller */ 1335*4882a593Smuzhiyun&usbhost30 { 1336*4882a593Smuzhiyun status = "okay"; 1337*4882a593Smuzhiyun}; 1338*4882a593Smuzhiyun 1339*4882a593Smuzhiyun&usbhost_dwc3 { 1340*4882a593Smuzhiyun status = "okay"; 1341*4882a593Smuzhiyun}; 1342*4882a593Smuzhiyun 1343*4882a593Smuzhiyun/* usb2 comb phy1 */ 1344*4882a593Smuzhiyun&usb2phy1 { 1345*4882a593Smuzhiyun status = "okay"; 1346*4882a593Smuzhiyun}; 1347*4882a593Smuzhiyun 1348*4882a593Smuzhiyun/* usb2 comb phy1 port0 */ 1349*4882a593Smuzhiyun&u2phy1_otg { 1350*4882a593Smuzhiyun status = "okay"; 1351*4882a593Smuzhiyun}; 1352*4882a593Smuzhiyun 1353*4882a593Smuzhiyun/* usb2 comb phy1 port1 */ 1354*4882a593Smuzhiyun&u2phy1_host { 1355*4882a593Smuzhiyun status = "okay"; 1356*4882a593Smuzhiyun}; 1357*4882a593Smuzhiyun 1358*4882a593Smuzhiyun/* usb2 host2 controller for high speed */ 1359*4882a593Smuzhiyun&usb_host0_ehci { 1360*4882a593Smuzhiyun status = "okay"; 1361*4882a593Smuzhiyun}; 1362*4882a593Smuzhiyun 1363*4882a593Smuzhiyun/* usb2 host2 controller for full/low speed */ 1364*4882a593Smuzhiyun&usb_host0_ohci { 1365*4882a593Smuzhiyun status = "okay"; 1366*4882a593Smuzhiyun}; 1367*4882a593Smuzhiyun 1368*4882a593Smuzhiyun/* usb2 host3 controller for high speed */ 1369*4882a593Smuzhiyun&usb_host1_ehci { 1370*4882a593Smuzhiyun status = "okay"; 1371*4882a593Smuzhiyun}; 1372*4882a593Smuzhiyun 1373*4882a593Smuzhiyun/* usb2 host3 controller for full/low speed */ 1374*4882a593Smuzhiyun&usb_host1_ohci { 1375*4882a593Smuzhiyun status = "okay"; 1376*4882a593Smuzhiyun}; 1377*4882a593Smuzhiyun 1378*4882a593Smuzhiyun/* PCIE Gen2 x 1 lane phy */ 1379*4882a593Smuzhiyun&combphy2_psq { 1380*4882a593Smuzhiyun status = "okay"; 1381*4882a593Smuzhiyun}; 1382*4882a593Smuzhiyun 1383*4882a593Smuzhiyun&pcie2x1 { 1384*4882a593Smuzhiyun reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; 1385*4882a593Smuzhiyun pinctrl-0 = <&pcie20m0_pins>; 1386*4882a593Smuzhiyun status = "okay"; 1387*4882a593Smuzhiyun}; 1388*4882a593Smuzhiyun 1389*4882a593Smuzhiyun/* PCIE Gen3 x 2 lane phy */ 1390*4882a593Smuzhiyun&pcie30phy { 1391*4882a593Smuzhiyun status = "okay"; 1392*4882a593Smuzhiyun}; 1393*4882a593Smuzhiyun 1394*4882a593Smuzhiyun&pcie3x2 { 1395*4882a593Smuzhiyun reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; 1396*4882a593Smuzhiyun pinctrl-0 = <&pcie30x2m0_pins>; 1397*4882a593Smuzhiyun status = "okay"; 1398*4882a593Smuzhiyun}; 1399*4882a593Smuzhiyun 1400*4882a593Smuzhiyun&pinctrl { 1401*4882a593Smuzhiyun wakeup { 1402*4882a593Smuzhiyun wakeup_keys: wakeup-keys { 1403*4882a593Smuzhiyun rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; 1404*4882a593Smuzhiyun }; 1405*4882a593Smuzhiyun }; 1406*4882a593Smuzhiyun 1407*4882a593Smuzhiyun extio { 1408*4882a593Smuzhiyun extio_int_gpio: extio-int-gpio { 1409*4882a593Smuzhiyun rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; 1410*4882a593Smuzhiyun }; 1411*4882a593Smuzhiyun 1412*4882a593Smuzhiyun extio_rst_gpio: extio-rst-gpio { 1413*4882a593Smuzhiyun rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 1414*4882a593Smuzhiyun }; 1415*4882a593Smuzhiyun }; 1416*4882a593Smuzhiyun 1417*4882a593Smuzhiyun headphone { 1418*4882a593Smuzhiyun hp_det: hp-det { 1419*4882a593Smuzhiyun rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 1420*4882a593Smuzhiyun }; 1421*4882a593Smuzhiyun }; 1422*4882a593Smuzhiyun 1423*4882a593Smuzhiyun pmic { 1424*4882a593Smuzhiyun pmic_int: pmic_int { 1425*4882a593Smuzhiyun rockchip,pins = 1426*4882a593Smuzhiyun <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; 1427*4882a593Smuzhiyun }; 1428*4882a593Smuzhiyun 1429*4882a593Smuzhiyun soc_slppin_gpio: soc_slppin_gpio { 1430*4882a593Smuzhiyun rockchip,pins = 1431*4882a593Smuzhiyun <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low_pull_down>; 1432*4882a593Smuzhiyun }; 1433*4882a593Smuzhiyun 1434*4882a593Smuzhiyun soc_slppin_slp: soc_slppin_slp { 1435*4882a593Smuzhiyun rockchip,pins = 1436*4882a593Smuzhiyun <0 RK_PA2 1 &pcfg_pull_up>; 1437*4882a593Smuzhiyun }; 1438*4882a593Smuzhiyun 1439*4882a593Smuzhiyun soc_slppin_rst: soc_slppin_rst { 1440*4882a593Smuzhiyun rockchip,pins = 1441*4882a593Smuzhiyun <0 RK_PA2 2 &pcfg_pull_none>; 1442*4882a593Smuzhiyun }; 1443*4882a593Smuzhiyun }; 1444*4882a593Smuzhiyun}; 1445*4882a593Smuzhiyun 1446*4882a593Smuzhiyun/* mipi dsi1 */ 1447*4882a593Smuzhiyun&dsi1 { 1448*4882a593Smuzhiyun status = "disabled"; 1449*4882a593Smuzhiyun //rockchip,lane-rate = <1000>; 1450*4882a593Smuzhiyun 1451*4882a593Smuzhiyun dsi1-panel { 1452*4882a593Smuzhiyun status = "okay"; 1453*4882a593Smuzhiyun compatible = "simple-panel-dsi"; 1454*4882a593Smuzhiyun reg = <0>; 1455*4882a593Smuzhiyun reset-delay-ms = <60>; 1456*4882a593Smuzhiyun enable-delay-ms = <60>; 1457*4882a593Smuzhiyun prepare-delay-ms = <60>; 1458*4882a593Smuzhiyun unprepare-delay-ms = <60>; 1459*4882a593Smuzhiyun disable-delay-ms = <60>; 1460*4882a593Smuzhiyun dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 1461*4882a593Smuzhiyun MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; 1462*4882a593Smuzhiyun dsi,format = <MIPI_DSI_FMT_RGB888>; 1463*4882a593Smuzhiyun dsi,lanes = <4>; 1464*4882a593Smuzhiyun panel-init-sequence = [ 1465*4882a593Smuzhiyun ]; 1466*4882a593Smuzhiyun 1467*4882a593Smuzhiyun panel-exit-sequence = [ 1468*4882a593Smuzhiyun ]; 1469*4882a593Smuzhiyun 1470*4882a593Smuzhiyun panel-width-mm = <68>; 1471*4882a593Smuzhiyun panel-height-mm = <121>; 1472*4882a593Smuzhiyun backlight = <&dsi1_backlight>; 1473*4882a593Smuzhiyun enable-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; 1474*4882a593Smuzhiyun 1475*4882a593Smuzhiyun display-timings { 1476*4882a593Smuzhiyun native-mode = <&dsi1_1024x600>; 1477*4882a593Smuzhiyun 1478*4882a593Smuzhiyun dsi1_1024x600: timing0 { 1479*4882a593Smuzhiyun clock-frequency = <45000000>; 1480*4882a593Smuzhiyun hactive = <1024>; 1481*4882a593Smuzhiyun vactive = <600>; 1482*4882a593Smuzhiyun hback-porch = <48>; 1483*4882a593Smuzhiyun hfront-porch = <40>; 1484*4882a593Smuzhiyun hsync-len = <48>; 1485*4882a593Smuzhiyun vback-porch = <48>; 1486*4882a593Smuzhiyun vfront-porch = <40>; 1487*4882a593Smuzhiyun vsync-len = <4>; 1488*4882a593Smuzhiyun hsync-active = <0>; 1489*4882a593Smuzhiyun vsync-active = <0>; 1490*4882a593Smuzhiyun de-active = <0>; 1491*4882a593Smuzhiyun pixelclk-active = <0>; 1492*4882a593Smuzhiyun }; 1493*4882a593Smuzhiyun }; 1494*4882a593Smuzhiyun 1495*4882a593Smuzhiyun ports { 1496*4882a593Smuzhiyun #address-cells = <1>; 1497*4882a593Smuzhiyun #size-cells = <0>; 1498*4882a593Smuzhiyun 1499*4882a593Smuzhiyun port@0 { 1500*4882a593Smuzhiyun reg = <0>; 1501*4882a593Smuzhiyun panel_in_dsi: endpoint { 1502*4882a593Smuzhiyun remote-endpoint = <&dsi_out_panel>; 1503*4882a593Smuzhiyun }; 1504*4882a593Smuzhiyun }; 1505*4882a593Smuzhiyun }; 1506*4882a593Smuzhiyun }; 1507*4882a593Smuzhiyun 1508*4882a593Smuzhiyun ports { 1509*4882a593Smuzhiyun #address-cells = <1>; 1510*4882a593Smuzhiyun #size-cells = <0>; 1511*4882a593Smuzhiyun 1512*4882a593Smuzhiyun port@1 { 1513*4882a593Smuzhiyun reg = <1>; 1514*4882a593Smuzhiyun dsi_out_panel: endpoint { 1515*4882a593Smuzhiyun remote-endpoint = <&panel_in_dsi>; 1516*4882a593Smuzhiyun }; 1517*4882a593Smuzhiyun }; 1518*4882a593Smuzhiyun }; 1519*4882a593Smuzhiyun 1520*4882a593Smuzhiyun}; 1521*4882a593Smuzhiyun 1522*4882a593Smuzhiyun&dsi1_in_vp0 { 1523*4882a593Smuzhiyun status = "disabled"; 1524*4882a593Smuzhiyun}; 1525*4882a593Smuzhiyun 1526*4882a593Smuzhiyun&dsi1_in_vp1 { 1527*4882a593Smuzhiyun status = "disabled"; 1528*4882a593Smuzhiyun}; 1529*4882a593Smuzhiyun 1530*4882a593Smuzhiyun&route_dsi1 { 1531*4882a593Smuzhiyun status = "disabled"; 1532*4882a593Smuzhiyun connect = <&vp1_out_dsi1>; 1533*4882a593Smuzhiyun}; 1534*4882a593Smuzhiyun 1535*4882a593Smuzhiyun/* edp */ 1536*4882a593Smuzhiyun&edp { 1537*4882a593Smuzhiyun status = "disabled"; 1538*4882a593Smuzhiyun pinctrl-names = "default"; 1539*4882a593Smuzhiyun pinctrl-0 = <&edpdpm0_pins>; 1540*4882a593Smuzhiyun 1541*4882a593Smuzhiyun ports { 1542*4882a593Smuzhiyun port@1 { 1543*4882a593Smuzhiyun reg = <1>; 1544*4882a593Smuzhiyun edp_out_panel: endpoint { 1545*4882a593Smuzhiyun remote-endpoint = <&panel_in_edp>; 1546*4882a593Smuzhiyun }; 1547*4882a593Smuzhiyun }; 1548*4882a593Smuzhiyun }; 1549*4882a593Smuzhiyun}; 1550*4882a593Smuzhiyun 1551*4882a593Smuzhiyun&edp_phy { 1552*4882a593Smuzhiyun status = "disabled"; 1553*4882a593Smuzhiyun}; 1554*4882a593Smuzhiyun 1555*4882a593Smuzhiyun&edp_in_vp0 { 1556*4882a593Smuzhiyun status = "disabled"; 1557*4882a593Smuzhiyun}; 1558*4882a593Smuzhiyun 1559*4882a593Smuzhiyun&edp_in_vp1 { 1560*4882a593Smuzhiyun status = "disabled"; 1561*4882a593Smuzhiyun}; 1562*4882a593Smuzhiyun 1563*4882a593Smuzhiyun&route_edp { 1564*4882a593Smuzhiyun status = "disabled"; 1565*4882a593Smuzhiyun connect = <&vp1_out_edp>; 1566*4882a593Smuzhiyun}; 1567*4882a593Smuzhiyun 1568*4882a593Smuzhiyun/* lvds */ 1569*4882a593Smuzhiyun&lvds { 1570*4882a593Smuzhiyun status = "disabled"; 1571*4882a593Smuzhiyun phys = <&video_phy0>; 1572*4882a593Smuzhiyun phy-names = "phy"; 1573*4882a593Smuzhiyun 1574*4882a593Smuzhiyun ports { 1575*4882a593Smuzhiyun port@1 { 1576*4882a593Smuzhiyun reg = <1>; 1577*4882a593Smuzhiyun lvds_out_panel: endpoint { 1578*4882a593Smuzhiyun remote-endpoint = <&panel_in_lvds>; 1579*4882a593Smuzhiyun }; 1580*4882a593Smuzhiyun }; 1581*4882a593Smuzhiyun }; 1582*4882a593Smuzhiyun}; 1583*4882a593Smuzhiyun 1584*4882a593Smuzhiyun&lvds_in_vp1 { 1585*4882a593Smuzhiyun status = "disabled"; 1586*4882a593Smuzhiyun}; 1587*4882a593Smuzhiyun 1588*4882a593Smuzhiyun&lvds_in_vp2 { 1589*4882a593Smuzhiyun status = "disabled"; 1590*4882a593Smuzhiyun}; 1591*4882a593Smuzhiyun 1592*4882a593Smuzhiyun&route_lvds { 1593*4882a593Smuzhiyun status = "disabled"; 1594*4882a593Smuzhiyun connect = <&vp2_out_lvds>; 1595*4882a593Smuzhiyun}; 1596*4882a593Smuzhiyun 1597*4882a593Smuzhiyun/* rgb */ 1598*4882a593Smuzhiyun&rgb { 1599*4882a593Smuzhiyun status = "disabled"; 1600*4882a593Smuzhiyun phys = <&video_phy0>; 1601*4882a593Smuzhiyun phy-names = "phy"; 1602*4882a593Smuzhiyun 1603*4882a593Smuzhiyun ports { 1604*4882a593Smuzhiyun port@1 { 1605*4882a593Smuzhiyun reg = <1>; 1606*4882a593Smuzhiyun rgb_out_panel: endpoint { 1607*4882a593Smuzhiyun remote-endpoint = <&panel_in_rgb>; 1608*4882a593Smuzhiyun }; 1609*4882a593Smuzhiyun }; 1610*4882a593Smuzhiyun }; 1611*4882a593Smuzhiyun}; 1612*4882a593Smuzhiyun 1613*4882a593Smuzhiyun&rgb_in_vp2 { 1614*4882a593Smuzhiyun status = "disabled"; 1615*4882a593Smuzhiyun}; 1616*4882a593Smuzhiyun 1617*4882a593Smuzhiyun&route_rgb { 1618*4882a593Smuzhiyun status = "disabled"; 1619*4882a593Smuzhiyun connect = <&vp2_out_rgb>; 1620*4882a593Smuzhiyun}; 1621*4882a593Smuzhiyun 1622*4882a593Smuzhiyun/* hdmi */ 1623*4882a593Smuzhiyun&hdmi { 1624*4882a593Smuzhiyun status = "disabled"; 1625*4882a593Smuzhiyun rockchip,phy-table = 1626*4882a593Smuzhiyun <92812500 0x8009 0x0000 0x0270>, 1627*4882a593Smuzhiyun <165000000 0x800b 0x0000 0x026d>, 1628*4882a593Smuzhiyun <185625000 0x800b 0x0000 0x01ed>, 1629*4882a593Smuzhiyun <297000000 0x800b 0x0000 0x01ad>, 1630*4882a593Smuzhiyun <594000000 0x8029 0x0000 0x0088>, 1631*4882a593Smuzhiyun <000000000 0x0000 0x0000 0x0000>; 1632*4882a593Smuzhiyun}; 1633*4882a593Smuzhiyun 1634*4882a593Smuzhiyun&hdmi_in_vp0 { 1635*4882a593Smuzhiyun status = "disabled"; 1636*4882a593Smuzhiyun}; 1637*4882a593Smuzhiyun 1638*4882a593Smuzhiyun&hdmi_in_vp1 { 1639*4882a593Smuzhiyun status = "disabled"; 1640*4882a593Smuzhiyun}; 1641*4882a593Smuzhiyun 1642*4882a593Smuzhiyun&route_hdmi { 1643*4882a593Smuzhiyun status = "disabled"; 1644*4882a593Smuzhiyun connect = <&vp0_out_hdmi>; 1645*4882a593Smuzhiyun}; 1646*4882a593Smuzhiyun 1647*4882a593Smuzhiyun/* lvds backlight */ 1648*4882a593Smuzhiyun&pwm3 { 1649*4882a593Smuzhiyun status = "okay"; 1650*4882a593Smuzhiyun}; 1651*4882a593Smuzhiyun 1652*4882a593Smuzhiyun/* edp backlight */ 1653*4882a593Smuzhiyun&pwm4 { 1654*4882a593Smuzhiyun status = "okay"; 1655*4882a593Smuzhiyun}; 1656*4882a593Smuzhiyun 1657*4882a593Smuzhiyun/* rgb backlight */ 1658*4882a593Smuzhiyun&pwm5 { 1659*4882a593Smuzhiyun status = "okay"; 1660*4882a593Smuzhiyun}; 1661*4882a593Smuzhiyun 1662*4882a593Smuzhiyun/* dsi1 backlight */ 1663*4882a593Smuzhiyun&pwm14 { 1664*4882a593Smuzhiyun status = "okay"; 1665*4882a593Smuzhiyun}; 1666*4882a593Smuzhiyun 1667*4882a593Smuzhiyun&i2c3 { 1668*4882a593Smuzhiyun status = "okay"; 1669*4882a593Smuzhiyun 1670*4882a593Smuzhiyun gt9xx_lvds: gt9xx@5d { 1671*4882a593Smuzhiyun compatible = "goodix,gt928"; 1672*4882a593Smuzhiyun reg = <0x5d>; 1673*4882a593Smuzhiyun interrupt-parent = <&extio>; 1674*4882a593Smuzhiyun interrupts = <EXTIO_GPIO_P00 IRQ_TYPE_EDGE_FALLING>; 1675*4882a593Smuzhiyun irq-gpio = <&extio EXTIO_GPIO_P00 GPIO_ACTIVE_HIGH>; 1676*4882a593Smuzhiyun reset-gpio = <&extio EXTIO_GPIO_P01 GPIO_ACTIVE_HIGH>; 1677*4882a593Smuzhiyun touchscreen-size-x = <1280>; 1678*4882a593Smuzhiyun touchscreen-size-y = <800>; 1679*4882a593Smuzhiyun touchscreen-swapped-x-y; 1680*4882a593Smuzhiyun uniq = "lvds"; 1681*4882a593Smuzhiyun status = "okay"; 1682*4882a593Smuzhiyun }; 1683*4882a593Smuzhiyun 1684*4882a593Smuzhiyun cam2_ov5645: cam2_ov5645@3c { 1685*4882a593Smuzhiyun status = "okay"; 1686*4882a593Smuzhiyun compatible = "ovti,ov5645"; 1687*4882a593Smuzhiyun reg = <0x3c>; 1688*4882a593Smuzhiyun clocks = <&ext_cam_clk>; 1689*4882a593Smuzhiyun clock-names = "xclk"; 1690*4882a593Smuzhiyun clock-frequency = <24000000>; 1691*4882a593Smuzhiyun 1692*4882a593Smuzhiyun reset-gpios = <&extio EXTIO_GPIO_P17 GPIO_ACTIVE_LOW>; 1693*4882a593Smuzhiyun enable-gpios = <&extio EXTIO_GPIO_P20 GPIO_ACTIVE_HIGH>; 1694*4882a593Smuzhiyun 1695*4882a593Smuzhiyun rockchip,camera-module-index = <1>; 1696*4882a593Smuzhiyun rockchip,camera-module-facing = "front"; 1697*4882a593Smuzhiyun rockchip,camera-module-name = "NC"; 1698*4882a593Smuzhiyun rockchip,camera-module-lens-name = "NC"; 1699*4882a593Smuzhiyun port { 1700*4882a593Smuzhiyun cam2_ov5645_out: endpoint { 1701*4882a593Smuzhiyun remote-endpoint = <&mipi_in_ucam2>; 1702*4882a593Smuzhiyun data-lanes = <1 2>; 1703*4882a593Smuzhiyun }; 1704*4882a593Smuzhiyun }; 1705*4882a593Smuzhiyun }; 1706*4882a593Smuzhiyun}; 1707*4882a593Smuzhiyun 1708*4882a593Smuzhiyun&i2c4 { 1709*4882a593Smuzhiyun status = "okay"; 1710*4882a593Smuzhiyun 1711*4882a593Smuzhiyun gt9xx_dsi: gt9xx@14 { 1712*4882a593Smuzhiyun compatible = "goodix,gt928"; 1713*4882a593Smuzhiyun reg = <0x14>; 1714*4882a593Smuzhiyun interrupt-parent = <&extio>; 1715*4882a593Smuzhiyun interrupts = <EXTIO_GPIO_P06 IRQ_TYPE_EDGE_FALLING>; 1716*4882a593Smuzhiyun irq-gpio = <&extio EXTIO_GPIO_P06 GPIO_ACTIVE_HIGH>; 1717*4882a593Smuzhiyun reset-gpio = <&extio EXTIO_GPIO_P05 GPIO_ACTIVE_HIGH>; 1718*4882a593Smuzhiyun touchscreen-size-x = <1024>; 1719*4882a593Smuzhiyun touchscreen-size-y = <600>; 1720*4882a593Smuzhiyun uniq = "dsi"; 1721*4882a593Smuzhiyun status = "okay"; 1722*4882a593Smuzhiyun }; 1723*4882a593Smuzhiyun 1724*4882a593Smuzhiyun polytouch: edt-ft5x06@38{ 1725*4882a593Smuzhiyun compatible = "edt,edt-ft5406", "edt,edt-ft5x06"; 1726*4882a593Smuzhiyun reg = <0x38>; 1727*4882a593Smuzhiyun interrupt-parent = <&extio>; 1728*4882a593Smuzhiyun interrupts = <EXTIO_GPIO_P06 IRQ_TYPE_EDGE_FALLING>; 1729*4882a593Smuzhiyun irq-gpio = <&extio EXTIO_GPIO_P06 GPIO_ACTIVE_HIGH>; 1730*4882a593Smuzhiyun reset-gpio = <&extio EXTIO_GPIO_P05 GPIO_ACTIVE_HIGH>; 1731*4882a593Smuzhiyun touchscreen-size-x = <1024>; 1732*4882a593Smuzhiyun touchscreen-size-y = <600>; 1733*4882a593Smuzhiyun status = "okay"; 1734*4882a593Smuzhiyun }; 1735*4882a593Smuzhiyun 1736*4882a593Smuzhiyun cam1_ov5645: cam1_ov5645@3c { 1737*4882a593Smuzhiyun status = "okay"; 1738*4882a593Smuzhiyun compatible = "ovti,ov5645"; 1739*4882a593Smuzhiyun reg = <0x3c>; 1740*4882a593Smuzhiyun clocks = <&ext_cam_clk>; 1741*4882a593Smuzhiyun clock-names = "xclk"; 1742*4882a593Smuzhiyun clock-frequency = <24000000>; 1743*4882a593Smuzhiyun 1744*4882a593Smuzhiyun reset-gpios = <&extio EXTIO_GPIO_P21 GPIO_ACTIVE_LOW>; 1745*4882a593Smuzhiyun enable-gpios = <&extio EXTIO_GPIO_P22 GPIO_ACTIVE_HIGH>; 1746*4882a593Smuzhiyun 1747*4882a593Smuzhiyun rockchip,camera-module-index = <0>; 1748*4882a593Smuzhiyun rockchip,camera-module-facing = "front"; 1749*4882a593Smuzhiyun rockchip,camera-module-name = "NC"; 1750*4882a593Smuzhiyun rockchip,camera-module-lens-name = "NC"; 1751*4882a593Smuzhiyun port { 1752*4882a593Smuzhiyun cam1_ov5645_out: endpoint { 1753*4882a593Smuzhiyun remote-endpoint = <&mipi_in_ucam1>; 1754*4882a593Smuzhiyun data-lanes = <1 2>; 1755*4882a593Smuzhiyun }; 1756*4882a593Smuzhiyun }; 1757*4882a593Smuzhiyun }; 1758*4882a593Smuzhiyun}; 1759*4882a593Smuzhiyun 1760*4882a593Smuzhiyun&vop { 1761*4882a593Smuzhiyun status = "okay"; 1762*4882a593Smuzhiyun assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; 1763*4882a593Smuzhiyun assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>, <&cru PLL_GPLL>; 1764*4882a593Smuzhiyun disable-win-move; 1765*4882a593Smuzhiyun}; 1766*4882a593Smuzhiyun 1767*4882a593Smuzhiyun&vop_mmu { 1768*4882a593Smuzhiyun status = "okay"; 1769*4882a593Smuzhiyun}; 1770*4882a593Smuzhiyun 1771*4882a593Smuzhiyun&vp0 { 1772*4882a593Smuzhiyun cursor-win-id = <ROCKCHIP_VOP2_CLUSTER0>; 1773*4882a593Smuzhiyun}; 1774*4882a593Smuzhiyun 1775*4882a593Smuzhiyun&vp1 { 1776*4882a593Smuzhiyun cursor-win-id = <ROCKCHIP_VOP2_CLUSTER1>; 1777*4882a593Smuzhiyun}; 1778*4882a593Smuzhiyun 1779*4882a593Smuzhiyun&video_phy0 { 1780*4882a593Smuzhiyun status = "okay"; 1781*4882a593Smuzhiyun}; 1782*4882a593Smuzhiyun 1783*4882a593Smuzhiyun&video_phy1 { 1784*4882a593Smuzhiyun status = "okay"; 1785*4882a593Smuzhiyun}; 1786*4882a593Smuzhiyun 1787*4882a593Smuzhiyun&csi2_dphy_hw { 1788*4882a593Smuzhiyun status = "okay"; 1789*4882a593Smuzhiyun}; 1790*4882a593Smuzhiyun 1791*4882a593Smuzhiyun&csi2_dphy1 { 1792*4882a593Smuzhiyun status = "okay"; 1793*4882a593Smuzhiyun 1794*4882a593Smuzhiyun ports { 1795*4882a593Smuzhiyun #address-cells = <1>; 1796*4882a593Smuzhiyun #size-cells = <0>; 1797*4882a593Smuzhiyun port@0 { 1798*4882a593Smuzhiyun reg = <0>; 1799*4882a593Smuzhiyun #address-cells = <1>; 1800*4882a593Smuzhiyun #size-cells = <0>; 1801*4882a593Smuzhiyun 1802*4882a593Smuzhiyun mipi_in_ucam1: endpoint@1 { 1803*4882a593Smuzhiyun reg = <1>; 1804*4882a593Smuzhiyun remote-endpoint = <&cam1_ov5645_out>; 1805*4882a593Smuzhiyun data-lanes = <1 2>; 1806*4882a593Smuzhiyun }; 1807*4882a593Smuzhiyun }; 1808*4882a593Smuzhiyun port@1 { 1809*4882a593Smuzhiyun reg = <1>; 1810*4882a593Smuzhiyun #address-cells = <1>; 1811*4882a593Smuzhiyun #size-cells = <0>; 1812*4882a593Smuzhiyun 1813*4882a593Smuzhiyun csidphy1_out: endpoint@0 { 1814*4882a593Smuzhiyun reg = <0>; 1815*4882a593Smuzhiyun remote-endpoint = <&isp0_in>; 1816*4882a593Smuzhiyun }; 1817*4882a593Smuzhiyun }; 1818*4882a593Smuzhiyun }; 1819*4882a593Smuzhiyun}; 1820*4882a593Smuzhiyun 1821*4882a593Smuzhiyun&rkisp { 1822*4882a593Smuzhiyun status = "okay"; 1823*4882a593Smuzhiyun}; 1824*4882a593Smuzhiyun 1825*4882a593Smuzhiyun&rkisp_mmu { 1826*4882a593Smuzhiyun status = "okay"; 1827*4882a593Smuzhiyun}; 1828*4882a593Smuzhiyun 1829*4882a593Smuzhiyun&rkisp_vir0 { 1830*4882a593Smuzhiyun status = "okay"; 1831*4882a593Smuzhiyun 1832*4882a593Smuzhiyun port { 1833*4882a593Smuzhiyun #address-cells = <1>; 1834*4882a593Smuzhiyun #size-cells = <0>; 1835*4882a593Smuzhiyun 1836*4882a593Smuzhiyun isp0_in: endpoint@0 { 1837*4882a593Smuzhiyun reg = <0>; 1838*4882a593Smuzhiyun remote-endpoint = <&csidphy1_out>; 1839*4882a593Smuzhiyun }; 1840*4882a593Smuzhiyun }; 1841*4882a593Smuzhiyun}; 1842*4882a593Smuzhiyun 1843*4882a593Smuzhiyun&csi2_dphy2 { 1844*4882a593Smuzhiyun status = "okay"; 1845*4882a593Smuzhiyun ports { 1846*4882a593Smuzhiyun #address-cells = <1>; 1847*4882a593Smuzhiyun #size-cells = <0>; 1848*4882a593Smuzhiyun port@0 { 1849*4882a593Smuzhiyun reg = <0>; 1850*4882a593Smuzhiyun #address-cells = <1>; 1851*4882a593Smuzhiyun #size-cells = <0>; 1852*4882a593Smuzhiyun 1853*4882a593Smuzhiyun mipi_in_ucam2: endpoint@1 { 1854*4882a593Smuzhiyun reg = <1>; 1855*4882a593Smuzhiyun remote-endpoint = <&cam2_ov5645_out>; 1856*4882a593Smuzhiyun data-lanes = <1 2>; 1857*4882a593Smuzhiyun }; 1858*4882a593Smuzhiyun }; 1859*4882a593Smuzhiyun port@1 { 1860*4882a593Smuzhiyun reg = <1>; 1861*4882a593Smuzhiyun #address-cells = <1>; 1862*4882a593Smuzhiyun #size-cells = <0>; 1863*4882a593Smuzhiyun 1864*4882a593Smuzhiyun csidphy2_out: endpoint@0 { 1865*4882a593Smuzhiyun reg = <0>; 1866*4882a593Smuzhiyun remote-endpoint = <&mipi_csi2_input>; 1867*4882a593Smuzhiyun }; 1868*4882a593Smuzhiyun }; 1869*4882a593Smuzhiyun }; 1870*4882a593Smuzhiyun}; 1871*4882a593Smuzhiyun 1872*4882a593Smuzhiyun&mipi_csi2_hw { 1873*4882a593Smuzhiyun status = "okay"; 1874*4882a593Smuzhiyun}; 1875*4882a593Smuzhiyun 1876*4882a593Smuzhiyun&mipi_csi2 { 1877*4882a593Smuzhiyun status = "okay"; 1878*4882a593Smuzhiyun ports { 1879*4882a593Smuzhiyun #address-cells = <1>; 1880*4882a593Smuzhiyun #size-cells = <0>; 1881*4882a593Smuzhiyun port@0 { 1882*4882a593Smuzhiyun reg = <0>; 1883*4882a593Smuzhiyun #address-cells = <1>; 1884*4882a593Smuzhiyun #size-cells = <0>; 1885*4882a593Smuzhiyun 1886*4882a593Smuzhiyun mipi_csi2_input: endpoint@1 { 1887*4882a593Smuzhiyun reg = <1>; 1888*4882a593Smuzhiyun remote-endpoint = <&csidphy2_out>; 1889*4882a593Smuzhiyun data-lanes = <1 2>; 1890*4882a593Smuzhiyun }; 1891*4882a593Smuzhiyun }; 1892*4882a593Smuzhiyun 1893*4882a593Smuzhiyun port@1 { 1894*4882a593Smuzhiyun reg = <1>; 1895*4882a593Smuzhiyun #address-cells = <1>; 1896*4882a593Smuzhiyun #size-cells = <0>; 1897*4882a593Smuzhiyun 1898*4882a593Smuzhiyun mipi_csi2_output: endpoint@0 { 1899*4882a593Smuzhiyun reg = <0>; 1900*4882a593Smuzhiyun remote-endpoint = <&cif_mipi_in>; 1901*4882a593Smuzhiyun data-lanes = <1 2>; 1902*4882a593Smuzhiyun }; 1903*4882a593Smuzhiyun }; 1904*4882a593Smuzhiyun }; 1905*4882a593Smuzhiyun}; 1906*4882a593Smuzhiyun 1907*4882a593Smuzhiyun&rkcif { 1908*4882a593Smuzhiyun status = "okay"; 1909*4882a593Smuzhiyun}; 1910*4882a593Smuzhiyun 1911*4882a593Smuzhiyun&rkcif_mmu { 1912*4882a593Smuzhiyun status = "okay"; 1913*4882a593Smuzhiyun}; 1914*4882a593Smuzhiyun 1915*4882a593Smuzhiyun&rkcif_mipi_lvds { 1916*4882a593Smuzhiyun status = "okay"; 1917*4882a593Smuzhiyun port { 1918*4882a593Smuzhiyun cif_mipi_in: endpoint { 1919*4882a593Smuzhiyun remote-endpoint = <&mipi_csi2_output>; 1920*4882a593Smuzhiyun data-lanes = <1 2>; 1921*4882a593Smuzhiyun }; 1922*4882a593Smuzhiyun }; 1923*4882a593Smuzhiyun}; 1924