1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree Source for the Kingfisher (ULCB extension) board 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2017 Renesas Electronics Corp. 6*4882a593Smuzhiyun * Copyright (C) 2017 Cogent Embedded, Inc. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/* 10*4882a593Smuzhiyun * SSI-PCM3168A 11*4882a593Smuzhiyun * aplay -D plughw:0,2 xxx.wav 12*4882a593Smuzhiyun * arecord -D plughw:0,3 xxx.wav 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun/ { 16*4882a593Smuzhiyun aliases { 17*4882a593Smuzhiyun serial1 = &hscif0; 18*4882a593Smuzhiyun serial2 = &scif1; 19*4882a593Smuzhiyun mmc2 = &sdhi3; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun clksndsel: clksndsel { 23*4882a593Smuzhiyun #clock-cells = <0>; 24*4882a593Smuzhiyun compatible = "gpio-mux-clock"; 25*4882a593Smuzhiyun clocks = <&cs2000>, <&audio_clk_a>; /* clk8snd, clksnd */ 26*4882a593Smuzhiyun select-gpios = <&gpio_exp_75 13 GPIO_ACTIVE_HIGH>; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun snd_3p3v: regulator-snd_3p3v { 30*4882a593Smuzhiyun compatible = "regulator-fixed"; 31*4882a593Smuzhiyun regulator-name = "snd-3.3v"; 32*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 33*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun snd_vcc5v: regulator-snd_vcc5v { 37*4882a593Smuzhiyun compatible = "regulator-fixed"; 38*4882a593Smuzhiyun regulator-name = "snd-vcc5v"; 39*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 40*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun wlan_en: regulator-wlan_en { 44*4882a593Smuzhiyun compatible = "regulator-fixed"; 45*4882a593Smuzhiyun regulator-name = "wlan-en-regulator"; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 48*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun gpio = <&gpio_exp_74 4 GPIO_ACTIVE_HIGH>; 51*4882a593Smuzhiyun startup-delay-us = <70000>; 52*4882a593Smuzhiyun enable-active-high; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun}; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun&can0 { 57*4882a593Smuzhiyun pinctrl-0 = <&can0_pins>; 58*4882a593Smuzhiyun pinctrl-names = "default"; 59*4882a593Smuzhiyun status = "okay"; 60*4882a593Smuzhiyun}; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun&can1 { 63*4882a593Smuzhiyun pinctrl-0 = <&can1_pins>; 64*4882a593Smuzhiyun pinctrl-names = "default"; 65*4882a593Smuzhiyun status = "okay"; 66*4882a593Smuzhiyun}; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun&ehci0 { 69*4882a593Smuzhiyun dr_mode = "otg"; 70*4882a593Smuzhiyun status = "okay"; 71*4882a593Smuzhiyun}; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun&hscif0 { 74*4882a593Smuzhiyun pinctrl-0 = <&hscif0_pins>; 75*4882a593Smuzhiyun pinctrl-names = "default"; 76*4882a593Smuzhiyun uart-has-rtscts; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun status = "okay"; 79*4882a593Smuzhiyun}; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun&hsusb { 82*4882a593Smuzhiyun dr_mode = "otg"; 83*4882a593Smuzhiyun status = "okay"; 84*4882a593Smuzhiyun}; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun&i2c2 { 87*4882a593Smuzhiyun i2cswitch2: i2c-switch@71 { 88*4882a593Smuzhiyun compatible = "nxp,pca9548"; 89*4882a593Smuzhiyun #address-cells = <1>; 90*4882a593Smuzhiyun #size-cells = <0>; 91*4882a593Smuzhiyun reg = <0x71>; 92*4882a593Smuzhiyun reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* Audio_SDA, Audio_SCL */ 95*4882a593Smuzhiyun i2c@7 { 96*4882a593Smuzhiyun #address-cells = <1>; 97*4882a593Smuzhiyun #size-cells = <0>; 98*4882a593Smuzhiyun reg = <7>; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun pcm3168a: audio-codec@44 { 101*4882a593Smuzhiyun #sound-dai-cells = <0>; 102*4882a593Smuzhiyun compatible = "ti,pcm3168a"; 103*4882a593Smuzhiyun reg = <0x44>; 104*4882a593Smuzhiyun clocks = <&clksndsel>; 105*4882a593Smuzhiyun clock-names = "scki"; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun VDD1-supply = <&snd_3p3v>; 108*4882a593Smuzhiyun VDD2-supply = <&snd_3p3v>; 109*4882a593Smuzhiyun VCCAD1-supply = <&snd_vcc5v>; 110*4882a593Smuzhiyun VCCAD2-supply = <&snd_vcc5v>; 111*4882a593Smuzhiyun VCCDA1-supply = <&snd_vcc5v>; 112*4882a593Smuzhiyun VCCDA2-supply = <&snd_vcc5v>; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun ports { 115*4882a593Smuzhiyun #address-cells = <1>; 116*4882a593Smuzhiyun #size-cells = <0>; 117*4882a593Smuzhiyun mclk-fs = <512>; 118*4882a593Smuzhiyun port@0 { 119*4882a593Smuzhiyun reg = <0>; 120*4882a593Smuzhiyun pcm3168a_endpoint_p: endpoint { 121*4882a593Smuzhiyun remote-endpoint = <&rsnd_for_pcm3168a_play>; 122*4882a593Smuzhiyun clocks = <&clksndsel>; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun port@1 { 126*4882a593Smuzhiyun reg = <1>; 127*4882a593Smuzhiyun pcm3168a_endpoint_c: endpoint { 128*4882a593Smuzhiyun remote-endpoint = <&rsnd_for_pcm3168a_capture>; 129*4882a593Smuzhiyun clocks = <&clksndsel>; 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun }; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun /* U11 */ 138*4882a593Smuzhiyun gpio_exp_74: gpio@74 { 139*4882a593Smuzhiyun compatible = "ti,tca9539"; 140*4882a593Smuzhiyun reg = <0x74>; 141*4882a593Smuzhiyun gpio-controller; 142*4882a593Smuzhiyun #gpio-cells = <2>; 143*4882a593Smuzhiyun interrupt-controller; 144*4882a593Smuzhiyun interrupt-parent = <&gpio6>; 145*4882a593Smuzhiyun interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun audio_out_off { 148*4882a593Smuzhiyun gpio-hog; 149*4882a593Smuzhiyun gpios = <0 GPIO_ACTIVE_HIGH>; /* P00 */ 150*4882a593Smuzhiyun output-high; 151*4882a593Smuzhiyun line-name = "Audio_Out_OFF"; 152*4882a593Smuzhiyun }; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun hub_pwen { 155*4882a593Smuzhiyun gpio-hog; 156*4882a593Smuzhiyun gpios = <6 GPIO_ACTIVE_HIGH>; 157*4882a593Smuzhiyun output-high; 158*4882a593Smuzhiyun line-name = "HUB pwen"; 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun hub_rst { 162*4882a593Smuzhiyun gpio-hog; 163*4882a593Smuzhiyun gpios = <7 GPIO_ACTIVE_HIGH>; 164*4882a593Smuzhiyun output-high; 165*4882a593Smuzhiyun line-name = "HUB rst"; 166*4882a593Smuzhiyun }; 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun otg_extlpn { 169*4882a593Smuzhiyun gpio-hog; 170*4882a593Smuzhiyun gpios = <9 GPIO_ACTIVE_HIGH>; 171*4882a593Smuzhiyun output-high; 172*4882a593Smuzhiyun line-name = "OTG EXTLPn"; 173*4882a593Smuzhiyun }; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun otg_offvbusn { 176*4882a593Smuzhiyun gpio-hog; 177*4882a593Smuzhiyun gpios = <8 GPIO_ACTIVE_HIGH>; 178*4882a593Smuzhiyun output-low; 179*4882a593Smuzhiyun line-name = "OTG OFFVBUSn"; 180*4882a593Smuzhiyun }; 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun sd-wifi-mux { 183*4882a593Smuzhiyun gpio-hog; 184*4882a593Smuzhiyun gpios = <5 GPIO_ACTIVE_HIGH>; 185*4882a593Smuzhiyun output-low; /* Connect WL1837 */ 186*4882a593Smuzhiyun line-name = "SD WiFi mux"; 187*4882a593Smuzhiyun }; 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun snd_rst { 190*4882a593Smuzhiyun gpio-hog; 191*4882a593Smuzhiyun gpios = <15 GPIO_ACTIVE_HIGH>; /* P17 */ 192*4882a593Smuzhiyun output-high; 193*4882a593Smuzhiyun line-name = "SND_RST"; 194*4882a593Smuzhiyun }; 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun /* U5 */ 198*4882a593Smuzhiyun gpio_exp_75: gpio@75 { 199*4882a593Smuzhiyun compatible = "ti,tca9539"; 200*4882a593Smuzhiyun reg = <0x75>; 201*4882a593Smuzhiyun gpio-controller; 202*4882a593Smuzhiyun #gpio-cells = <2>; 203*4882a593Smuzhiyun interrupt-controller; 204*4882a593Smuzhiyun interrupt-parent = <&gpio6>; 205*4882a593Smuzhiyun interrupts = <4 IRQ_TYPE_EDGE_FALLING>; 206*4882a593Smuzhiyun }; 207*4882a593Smuzhiyun}; 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun&i2c4 { 210*4882a593Smuzhiyun i2cswitch4: i2c-switch@71 { 211*4882a593Smuzhiyun compatible = "nxp,pca9548"; 212*4882a593Smuzhiyun #address-cells = <1>; 213*4882a593Smuzhiyun #size-cells = <0>; 214*4882a593Smuzhiyun reg = <0x71>; 215*4882a593Smuzhiyun reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; 216*4882a593Smuzhiyun }; 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun gpio_exp_76: gpio@76 { 219*4882a593Smuzhiyun compatible = "ti,tca9539"; 220*4882a593Smuzhiyun reg = <0x76>; 221*4882a593Smuzhiyun gpio-controller; 222*4882a593Smuzhiyun #gpio-cells = <2>; 223*4882a593Smuzhiyun interrupt-controller; 224*4882a593Smuzhiyun interrupt-parent = <&gpio7>; 225*4882a593Smuzhiyun interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 226*4882a593Smuzhiyun }; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun gpio_exp_77: gpio@77 { 229*4882a593Smuzhiyun compatible = "ti,tca9539"; 230*4882a593Smuzhiyun reg = <0x77>; 231*4882a593Smuzhiyun gpio-controller; 232*4882a593Smuzhiyun #gpio-cells = <2>; 233*4882a593Smuzhiyun interrupt-controller; 234*4882a593Smuzhiyun interrupt-parent = <&gpio5>; 235*4882a593Smuzhiyun interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 236*4882a593Smuzhiyun }; 237*4882a593Smuzhiyun}; 238*4882a593Smuzhiyun 239*4882a593Smuzhiyun&ohci0 { 240*4882a593Smuzhiyun dr_mode = "otg"; 241*4882a593Smuzhiyun status = "okay"; 242*4882a593Smuzhiyun}; 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun&pcie_bus_clk { 245*4882a593Smuzhiyun clock-frequency = <100000000>; 246*4882a593Smuzhiyun}; 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun&pciec0 { 249*4882a593Smuzhiyun status = "okay"; 250*4882a593Smuzhiyun}; 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun&pciec1 { 253*4882a593Smuzhiyun status = "okay"; 254*4882a593Smuzhiyun}; 255*4882a593Smuzhiyun 256*4882a593Smuzhiyun&pfc { 257*4882a593Smuzhiyun can0_pins: can0 { 258*4882a593Smuzhiyun groups = "can0_data_a"; 259*4882a593Smuzhiyun function = "can0"; 260*4882a593Smuzhiyun }; 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun can1_pins: can1 { 263*4882a593Smuzhiyun groups = "can1_data"; 264*4882a593Smuzhiyun function = "can1"; 265*4882a593Smuzhiyun }; 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun hscif0_pins: hscif0 { 268*4882a593Smuzhiyun groups = "hscif0_data", "hscif0_ctrl"; 269*4882a593Smuzhiyun function = "hscif0"; 270*4882a593Smuzhiyun }; 271*4882a593Smuzhiyun 272*4882a593Smuzhiyun scif1_pins: scif1 { 273*4882a593Smuzhiyun groups = "scif1_data_b", "scif1_ctrl"; 274*4882a593Smuzhiyun function = "scif1"; 275*4882a593Smuzhiyun }; 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun sdhi3_pins: sdhi3 { 278*4882a593Smuzhiyun groups = "sdhi3_data4", "sdhi3_ctrl"; 279*4882a593Smuzhiyun function = "sdhi3"; 280*4882a593Smuzhiyun power-source = <3300>; 281*4882a593Smuzhiyun }; 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun sound_pcm_pins: sound-pcm { 284*4882a593Smuzhiyun groups = "ssi349_ctrl", "ssi3_data", "ssi4_data"; 285*4882a593Smuzhiyun function = "ssi"; 286*4882a593Smuzhiyun }; 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun usb0_pins: usb0 { 289*4882a593Smuzhiyun groups = "usb0"; 290*4882a593Smuzhiyun function = "usb0"; 291*4882a593Smuzhiyun }; 292*4882a593Smuzhiyun}; 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun&rcar_sound { 295*4882a593Smuzhiyun pinctrl-0 = <&sound_pins 296*4882a593Smuzhiyun &sound_clk_pins 297*4882a593Smuzhiyun &sound_pcm_pins>; 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun ports { 300*4882a593Smuzhiyun /* rsnd_port0/1 are on salvator-common */ 301*4882a593Smuzhiyun rsnd_port2: port@2 { 302*4882a593Smuzhiyun reg = <2>; 303*4882a593Smuzhiyun rsnd_for_pcm3168a_play: endpoint { 304*4882a593Smuzhiyun remote-endpoint = <&pcm3168a_endpoint_p>; 305*4882a593Smuzhiyun 306*4882a593Smuzhiyun dai-format = "i2s"; 307*4882a593Smuzhiyun bitclock-master = <&rsnd_for_pcm3168a_play>; 308*4882a593Smuzhiyun frame-master = <&rsnd_for_pcm3168a_play>; 309*4882a593Smuzhiyun dai-tdm-slot-num = <8>; 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun playback = <&ssi3>; 312*4882a593Smuzhiyun }; 313*4882a593Smuzhiyun }; 314*4882a593Smuzhiyun rsnd_port3: port@3 { 315*4882a593Smuzhiyun reg = <3>; 316*4882a593Smuzhiyun rsnd_for_pcm3168a_capture: endpoint { 317*4882a593Smuzhiyun remote-endpoint = <&pcm3168a_endpoint_c>; 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun dai-format = "i2s"; 320*4882a593Smuzhiyun bitclock-master = <&rsnd_for_pcm3168a_capture>; 321*4882a593Smuzhiyun frame-master = <&rsnd_for_pcm3168a_capture>; 322*4882a593Smuzhiyun dai-tdm-slot-num = <6>; 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun capture = <&ssi4>; 325*4882a593Smuzhiyun }; 326*4882a593Smuzhiyun }; 327*4882a593Smuzhiyun }; 328*4882a593Smuzhiyun}; 329*4882a593Smuzhiyun 330*4882a593Smuzhiyun&scif1 { 331*4882a593Smuzhiyun pinctrl-0 = <&scif1_pins>; 332*4882a593Smuzhiyun pinctrl-names = "default"; 333*4882a593Smuzhiyun uart-has-rtscts; 334*4882a593Smuzhiyun 335*4882a593Smuzhiyun status = "okay"; 336*4882a593Smuzhiyun}; 337*4882a593Smuzhiyun 338*4882a593Smuzhiyun&sdhi3 { 339*4882a593Smuzhiyun pinctrl-0 = <&sdhi3_pins>; 340*4882a593Smuzhiyun pinctrl-names = "default"; 341*4882a593Smuzhiyun 342*4882a593Smuzhiyun vmmc-supply = <&wlan_en>; 343*4882a593Smuzhiyun vqmmc-supply = <&wlan_en>; 344*4882a593Smuzhiyun bus-width = <4>; 345*4882a593Smuzhiyun no-1-8-v; 346*4882a593Smuzhiyun non-removable; 347*4882a593Smuzhiyun cap-power-off-card; 348*4882a593Smuzhiyun keep-power-in-suspend; 349*4882a593Smuzhiyun max-frequency = <26000000>; 350*4882a593Smuzhiyun status = "okay"; 351*4882a593Smuzhiyun 352*4882a593Smuzhiyun #address-cells = <1>; 353*4882a593Smuzhiyun #size-cells = <0>; 354*4882a593Smuzhiyun wlcore: wlcore@2 { 355*4882a593Smuzhiyun compatible = "ti,wl1837"; 356*4882a593Smuzhiyun reg = <2>; 357*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 358*4882a593Smuzhiyun interrupts = <25 IRQ_TYPE_EDGE_FALLING>; 359*4882a593Smuzhiyun }; 360*4882a593Smuzhiyun}; 361*4882a593Smuzhiyun 362*4882a593Smuzhiyun&sound_card { 363*4882a593Smuzhiyun dais = <&rsnd_port0 /* ak4613 */ 364*4882a593Smuzhiyun &rsnd_port1 /* HDMI0 */ 365*4882a593Smuzhiyun &rsnd_port2 /* pcm3168a playback */ 366*4882a593Smuzhiyun &rsnd_port3 /* pcm3168a capture */ 367*4882a593Smuzhiyun >; 368*4882a593Smuzhiyun}; 369*4882a593Smuzhiyun 370*4882a593Smuzhiyun&ssi4 { 371*4882a593Smuzhiyun shared-pin; 372*4882a593Smuzhiyun}; 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun&usb2_phy0 { 375*4882a593Smuzhiyun pinctrl-0 = <&usb0_pins>; 376*4882a593Smuzhiyun pinctrl-names = "default"; 377*4882a593Smuzhiyun 378*4882a593Smuzhiyun status = "okay"; 379*4882a593Smuzhiyun}; 380*4882a593Smuzhiyun 381*4882a593Smuzhiyun&xhci0 { 382*4882a593Smuzhiyun status = "okay"; 383*4882a593Smuzhiyun}; 384