xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm64/renesas/r8a77970-v3msk.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Device Tree Source for the V3M Starter Kit board
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2017 Renesas Electronics Corp.
6*4882a593Smuzhiyun * Copyright (C) 2017 Cogent Embedded, Inc.
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun/dts-v1/;
10*4882a593Smuzhiyun#include "r8a77970.dtsi"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun/ {
13*4882a593Smuzhiyun	model = "Renesas V3M Starter Kit board";
14*4882a593Smuzhiyun	compatible = "renesas,v3msk", "renesas,r8a77970";
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun	aliases {
17*4882a593Smuzhiyun		serial0 = &scif0;
18*4882a593Smuzhiyun	};
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun	chosen {
21*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
22*4882a593Smuzhiyun	};
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun	hdmi-out {
25*4882a593Smuzhiyun		compatible = "hdmi-connector";
26*4882a593Smuzhiyun		type = "a";
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun		port {
29*4882a593Smuzhiyun			hdmi_con: endpoint {
30*4882a593Smuzhiyun				remote-endpoint = <&adv7511_out>;
31*4882a593Smuzhiyun			};
32*4882a593Smuzhiyun		};
33*4882a593Smuzhiyun	};
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun	lvds-decoder {
36*4882a593Smuzhiyun		compatible = "thine,thc63lvd1024";
37*4882a593Smuzhiyun		vcc-supply = <&vcc_d3_3v>;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun		ports {
40*4882a593Smuzhiyun			#address-cells = <1>;
41*4882a593Smuzhiyun			#size-cells = <0>;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun			port@0 {
44*4882a593Smuzhiyun				reg = <0>;
45*4882a593Smuzhiyun				thc63lvd1024_in: endpoint {
46*4882a593Smuzhiyun					remote-endpoint = <&lvds0_out>;
47*4882a593Smuzhiyun				};
48*4882a593Smuzhiyun			};
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun			port@2 {
51*4882a593Smuzhiyun				reg = <2>;
52*4882a593Smuzhiyun				thc63lvd1024_out: endpoint {
53*4882a593Smuzhiyun					remote-endpoint = <&adv7511_in>;
54*4882a593Smuzhiyun				};
55*4882a593Smuzhiyun			};
56*4882a593Smuzhiyun		};
57*4882a593Smuzhiyun	};
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun	memory@48000000 {
60*4882a593Smuzhiyun		device_type = "memory";
61*4882a593Smuzhiyun		/* first 128MB is reserved for secure area. */
62*4882a593Smuzhiyun		reg = <0x0 0x48000000 0x0 0x78000000>;
63*4882a593Smuzhiyun	};
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun	osc5_clk: osc5-clock {
66*4882a593Smuzhiyun		compatible = "fixed-clock";
67*4882a593Smuzhiyun		#clock-cells = <0>;
68*4882a593Smuzhiyun		clock-frequency = <148500000>;
69*4882a593Smuzhiyun	};
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun	vcc_d1_8v: regulator-0 {
72*4882a593Smuzhiyun		compatible = "regulator-fixed";
73*4882a593Smuzhiyun		regulator-name = "VCC_D1.8V";
74*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
75*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
76*4882a593Smuzhiyun		regulator-boot-on;
77*4882a593Smuzhiyun		regulator-always-on;
78*4882a593Smuzhiyun	};
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun	vcc_d3_3v: regulator-1 {
81*4882a593Smuzhiyun		compatible = "regulator-fixed";
82*4882a593Smuzhiyun		regulator-name = "VCC_D3.3V";
83*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
84*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
85*4882a593Smuzhiyun		regulator-boot-on;
86*4882a593Smuzhiyun		regulator-always-on;
87*4882a593Smuzhiyun	};
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun	vcc_vddq_vin0: regulator-2 {
90*4882a593Smuzhiyun		compatible = "regulator-fixed";
91*4882a593Smuzhiyun		regulator-name = "VCC_VDDQ_VIN0";
92*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
93*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
94*4882a593Smuzhiyun		regulator-boot-on;
95*4882a593Smuzhiyun		regulator-always-on;
96*4882a593Smuzhiyun	};
97*4882a593Smuzhiyun};
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun&avb {
100*4882a593Smuzhiyun	pinctrl-0 = <&avb_pins>;
101*4882a593Smuzhiyun	pinctrl-names = "default";
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun	renesas,no-ether-link;
104*4882a593Smuzhiyun	phy-handle = <&phy0>;
105*4882a593Smuzhiyun	phy-mode = "rgmii-id";
106*4882a593Smuzhiyun	status = "okay";
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun	phy0: ethernet-phy@0 {
109*4882a593Smuzhiyun		rxc-skew-ps = <1500>;
110*4882a593Smuzhiyun		reg = <0>;
111*4882a593Smuzhiyun		interrupt-parent = <&gpio1>;
112*4882a593Smuzhiyun		interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
113*4882a593Smuzhiyun	};
114*4882a593Smuzhiyun};
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun&du {
117*4882a593Smuzhiyun	clocks = <&cpg CPG_MOD 724>,
118*4882a593Smuzhiyun		 <&osc5_clk>;
119*4882a593Smuzhiyun	clock-names = "du.0", "dclkin.0";
120*4882a593Smuzhiyun	status = "okay";
121*4882a593Smuzhiyun};
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun&extal_clk {
124*4882a593Smuzhiyun	clock-frequency = <16666666>;
125*4882a593Smuzhiyun};
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun&extalr_clk {
128*4882a593Smuzhiyun	clock-frequency = <32768>;
129*4882a593Smuzhiyun};
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun&i2c0 {
132*4882a593Smuzhiyun	pinctrl-0 = <&i2c0_pins>;
133*4882a593Smuzhiyun	pinctrl-names = "default";
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun	status = "okay";
136*4882a593Smuzhiyun	clock-frequency = <400000>;
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun	hdmi@39{
139*4882a593Smuzhiyun		compatible = "adi,adv7511w";
140*4882a593Smuzhiyun		#sound-dai-cells = <0>;
141*4882a593Smuzhiyun		reg = <0x39>;
142*4882a593Smuzhiyun		interrupt-parent = <&gpio1>;
143*4882a593Smuzhiyun		interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
144*4882a593Smuzhiyun		avdd-supply = <&vcc_d1_8v>;
145*4882a593Smuzhiyun		dvdd-supply = <&vcc_d1_8v>;
146*4882a593Smuzhiyun		pvdd-supply = <&vcc_d1_8v>;
147*4882a593Smuzhiyun		bgvdd-supply = <&vcc_d1_8v>;
148*4882a593Smuzhiyun		dvdd-3v-supply = <&vcc_d3_3v>;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun		adi,input-depth = <8>;
151*4882a593Smuzhiyun		adi,input-colorspace = "rgb";
152*4882a593Smuzhiyun		adi,input-clock = "1x";
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun		ports {
155*4882a593Smuzhiyun			#address-cells = <1>;
156*4882a593Smuzhiyun			#size-cells = <0>;
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun			port@0 {
159*4882a593Smuzhiyun				reg = <0>;
160*4882a593Smuzhiyun				adv7511_in: endpoint {
161*4882a593Smuzhiyun					remote-endpoint = <&thc63lvd1024_out>;
162*4882a593Smuzhiyun				};
163*4882a593Smuzhiyun			};
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun			port@1 {
166*4882a593Smuzhiyun				reg = <1>;
167*4882a593Smuzhiyun				adv7511_out: endpoint {
168*4882a593Smuzhiyun					remote-endpoint = <&hdmi_con>;
169*4882a593Smuzhiyun				};
170*4882a593Smuzhiyun			};
171*4882a593Smuzhiyun		};
172*4882a593Smuzhiyun	};
173*4882a593Smuzhiyun};
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun&lvds0 {
176*4882a593Smuzhiyun	status = "okay";
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun	ports {
179*4882a593Smuzhiyun		port@1 {
180*4882a593Smuzhiyun			lvds0_out: endpoint {
181*4882a593Smuzhiyun				remote-endpoint = <&thc63lvd1024_in>;
182*4882a593Smuzhiyun			};
183*4882a593Smuzhiyun		};
184*4882a593Smuzhiyun	};
185*4882a593Smuzhiyun};
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun&mmc0 {
188*4882a593Smuzhiyun	pinctrl-0 = <&mmc_pins>;
189*4882a593Smuzhiyun	pinctrl-names = "default";
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun	vmmc-supply = <&vcc_d3_3v>;
192*4882a593Smuzhiyun	vqmmc-supply = <&vcc_vddq_vin0>;
193*4882a593Smuzhiyun	bus-width = <8>;
194*4882a593Smuzhiyun	non-removable;
195*4882a593Smuzhiyun	status = "okay";
196*4882a593Smuzhiyun};
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun&pfc {
199*4882a593Smuzhiyun	avb_pins: avb0 {
200*4882a593Smuzhiyun		groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
201*4882a593Smuzhiyun		function = "avb0";
202*4882a593Smuzhiyun	};
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun	i2c0_pins: i2c0 {
205*4882a593Smuzhiyun		groups = "i2c0";
206*4882a593Smuzhiyun		function = "i2c0";
207*4882a593Smuzhiyun	};
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun	mmc_pins: mmc_3_3v {
210*4882a593Smuzhiyun		groups = "mmc_data8", "mmc_ctrl";
211*4882a593Smuzhiyun		function = "mmc";
212*4882a593Smuzhiyun		power-source = <3300>;
213*4882a593Smuzhiyun	};
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun	qspi0_pins: qspi0 {
216*4882a593Smuzhiyun		groups = "qspi0_ctrl", "qspi0_data4";
217*4882a593Smuzhiyun		function = "qspi0";
218*4882a593Smuzhiyun	};
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun	scif0_pins: scif0 {
221*4882a593Smuzhiyun		groups = "scif0_data";
222*4882a593Smuzhiyun		function = "scif0";
223*4882a593Smuzhiyun	};
224*4882a593Smuzhiyun};
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun&rpc {
227*4882a593Smuzhiyun	pinctrl-0 = <&qspi0_pins>;
228*4882a593Smuzhiyun	pinctrl-names = "default";
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun	status = "okay";
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun	flash@0 {
233*4882a593Smuzhiyun		compatible = "spansion,s25fs512s", "jedec,spi-nor";
234*4882a593Smuzhiyun		reg = <0>;
235*4882a593Smuzhiyun		spi-max-frequency = <50000000>;
236*4882a593Smuzhiyun		spi-rx-bus-width = <4>;
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun		partitions {
239*4882a593Smuzhiyun			compatible = "fixed-partitions";
240*4882a593Smuzhiyun			#address-cells = <1>;
241*4882a593Smuzhiyun			#size-cells = <1>;
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun			bootparam@0 {
244*4882a593Smuzhiyun				reg = <0x00000000 0x040000>;
245*4882a593Smuzhiyun				read-only;
246*4882a593Smuzhiyun			};
247*4882a593Smuzhiyun			cr7@40000 {
248*4882a593Smuzhiyun				reg = <0x00040000 0x080000>;
249*4882a593Smuzhiyun				read-only;
250*4882a593Smuzhiyun			};
251*4882a593Smuzhiyun			cert_header_sa3@c0000 {
252*4882a593Smuzhiyun				reg = <0x000c0000 0x080000>;
253*4882a593Smuzhiyun				read-only;
254*4882a593Smuzhiyun			};
255*4882a593Smuzhiyun			bl2@140000 {
256*4882a593Smuzhiyun				reg = <0x00140000 0x040000>;
257*4882a593Smuzhiyun				read-only;
258*4882a593Smuzhiyun			};
259*4882a593Smuzhiyun			cert_header_sa6@180000 {
260*4882a593Smuzhiyun				reg = <0x00180000 0x040000>;
261*4882a593Smuzhiyun				read-only;
262*4882a593Smuzhiyun			};
263*4882a593Smuzhiyun			bl31@1c0000 {
264*4882a593Smuzhiyun				reg = <0x001c0000 0x460000>;
265*4882a593Smuzhiyun				read-only;
266*4882a593Smuzhiyun			};
267*4882a593Smuzhiyun			uboot@640000 {
268*4882a593Smuzhiyun				reg = <0x00640000 0x0c0000>;
269*4882a593Smuzhiyun				read-only;
270*4882a593Smuzhiyun			};
271*4882a593Smuzhiyun			uboot-env@700000 {
272*4882a593Smuzhiyun				reg = <0x00700000 0x040000>;
273*4882a593Smuzhiyun				read-only;
274*4882a593Smuzhiyun			};
275*4882a593Smuzhiyun			dtb@740000 {
276*4882a593Smuzhiyun				reg = <0x00740000 0x080000>;
277*4882a593Smuzhiyun			};
278*4882a593Smuzhiyun			kernel@7c0000 {
279*4882a593Smuzhiyun				reg = <0x007c0000 0x1400000>;
280*4882a593Smuzhiyun			};
281*4882a593Smuzhiyun			user@1bc0000 {
282*4882a593Smuzhiyun				reg = <0x01bc0000 0x2440000>;
283*4882a593Smuzhiyun			};
284*4882a593Smuzhiyun		};
285*4882a593Smuzhiyun	};
286*4882a593Smuzhiyun};
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun&scif0 {
289*4882a593Smuzhiyun	pinctrl-0 = <&scif0_pins>;
290*4882a593Smuzhiyun	pinctrl-names = "default";
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun	status = "okay";
293*4882a593Smuzhiyun};
294