1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright 2020, Compass Electronics Group, LLC 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/ { 9*4882a593Smuzhiyun memory@48000000 { 10*4882a593Smuzhiyun device_type = "memory"; 11*4882a593Smuzhiyun /* first 128MB is reserved for secure area. */ 12*4882a593Smuzhiyun reg = <0x0 0x48000000 0x0 0x78000000>; 13*4882a593Smuzhiyun }; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun memory@600000000 { 16*4882a593Smuzhiyun device_type = "memory"; 17*4882a593Smuzhiyun reg = <0x6 0x00000000 0x0 0x80000000>; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun osc_32k: osc_32k { 21*4882a593Smuzhiyun compatible = "fixed-clock"; 22*4882a593Smuzhiyun #clock-cells = <0>; 23*4882a593Smuzhiyun clock-frequency = <32768>; 24*4882a593Smuzhiyun clock-output-names = "osc_32k"; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun reg_1p8v: regulator0 { 28*4882a593Smuzhiyun compatible = "regulator-fixed"; 29*4882a593Smuzhiyun regulator-name = "fixed-1.8V"; 30*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 31*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 32*4882a593Smuzhiyun regulator-boot-on; 33*4882a593Smuzhiyun regulator-always-on; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun reg_3p3v: regulator1 { 37*4882a593Smuzhiyun compatible = "regulator-fixed"; 38*4882a593Smuzhiyun regulator-name = "fixed-3.3V"; 39*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 40*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 41*4882a593Smuzhiyun regulator-boot-on; 42*4882a593Smuzhiyun regulator-always-on; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun wlan_pwrseq: wlan_pwrseq { 46*4882a593Smuzhiyun compatible = "mmc-pwrseq-simple"; 47*4882a593Smuzhiyun reset-gpios = <&pca9654 1 GPIO_ACTIVE_LOW>; 48*4882a593Smuzhiyun clocks = <&osc_32k>; 49*4882a593Smuzhiyun clock-names = "ext_clock"; 50*4882a593Smuzhiyun post-power-on-delay-ms = <80>; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun}; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun&avb { 55*4882a593Smuzhiyun pinctrl-0 = <&avb_pins>; 56*4882a593Smuzhiyun pinctrl-names = "default"; 57*4882a593Smuzhiyun phy-mode = "rgmii-rxid"; 58*4882a593Smuzhiyun phy-handle = <&phy0>; 59*4882a593Smuzhiyun rx-internal-delay-ps = <1800>; 60*4882a593Smuzhiyun tx-internal-delay-ps = <2000>; 61*4882a593Smuzhiyun status = "okay"; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun phy0: ethernet-phy@0 { 64*4882a593Smuzhiyun reg = <0>; 65*4882a593Smuzhiyun interrupt-parent = <&gpio2>; 66*4882a593Smuzhiyun interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 67*4882a593Smuzhiyun reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun}; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun&extal_clk { 72*4882a593Smuzhiyun clock-frequency = <16666666>; 73*4882a593Smuzhiyun}; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun&extalr_clk { 76*4882a593Smuzhiyun clock-frequency = <32768>; 77*4882a593Smuzhiyun}; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun&gpio6 { 80*4882a593Smuzhiyun usb_hub_reset { 81*4882a593Smuzhiyun gpio-hog; 82*4882a593Smuzhiyun gpios = <10 GPIO_ACTIVE_HIGH>; 83*4882a593Smuzhiyun output-high; 84*4882a593Smuzhiyun line-name = "usb-hub-reset"; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun}; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun&hscif0 { 89*4882a593Smuzhiyun pinctrl-0 = <&hscif0_pins>; 90*4882a593Smuzhiyun pinctrl-names = "default"; 91*4882a593Smuzhiyun uart-has-rtscts; 92*4882a593Smuzhiyun status = "okay"; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun bluetooth { 95*4882a593Smuzhiyun compatible = "brcm,bcm43438-bt"; 96*4882a593Smuzhiyun shutdown-gpios = <&pca9654 2 GPIO_ACTIVE_HIGH>; 97*4882a593Smuzhiyun host-wakeup-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; 98*4882a593Smuzhiyun device-wakeup-gpios = <&pca9654 5 GPIO_ACTIVE_HIGH>; 99*4882a593Smuzhiyun clocks = <&osc_32k>; 100*4882a593Smuzhiyun clock-names = "extclk"; 101*4882a593Smuzhiyun max-speed = <4000000>; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun}; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun&hscif2 { 106*4882a593Smuzhiyun status = "okay"; 107*4882a593Smuzhiyun pinctrl-0 = <&hscif2_pins>; 108*4882a593Smuzhiyun pinctrl-names = "default"; 109*4882a593Smuzhiyun}; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun&i2c4 { 112*4882a593Smuzhiyun status = "okay"; 113*4882a593Smuzhiyun clock-frequency = <400000>; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun pca9654: gpio@20 { 116*4882a593Smuzhiyun compatible = "onnn,pca9654"; 117*4882a593Smuzhiyun reg = <0x20>; 118*4882a593Smuzhiyun gpio-controller; 119*4882a593Smuzhiyun #gpio-cells = <2>; 120*4882a593Smuzhiyun gpio-line-names = 121*4882a593Smuzhiyun "i2c4_20_0", 122*4882a593Smuzhiyun "wl_reg_on", 123*4882a593Smuzhiyun "bt_reg_on", 124*4882a593Smuzhiyun "i2c4_20_3", 125*4882a593Smuzhiyun "i2c4_20_4", 126*4882a593Smuzhiyun "bt_dev_wake", 127*4882a593Smuzhiyun "i2c4_20_6", 128*4882a593Smuzhiyun "i2c4_20_7"; 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun pca9654_lte: gpio@21 { 132*4882a593Smuzhiyun compatible = "onnn,pca9654"; 133*4882a593Smuzhiyun reg = <0x21>; 134*4882a593Smuzhiyun interrupt-parent = <&gpio5>; 135*4882a593Smuzhiyun interrupts = <25 IRQ_TYPE_EDGE_FALLING>; 136*4882a593Smuzhiyun interrupt-controller; 137*4882a593Smuzhiyun #interrupt-cells = <2>; 138*4882a593Smuzhiyun gpio-controller; 139*4882a593Smuzhiyun #gpio-cells = <2>; 140*4882a593Smuzhiyun gpio-line-names = 141*4882a593Smuzhiyun "i2c4_21_0", 142*4882a593Smuzhiyun "zoe_pwr_on", 143*4882a593Smuzhiyun "zoe_extint", 144*4882a593Smuzhiyun "zoe_reset_n", 145*4882a593Smuzhiyun "sara_reset", 146*4882a593Smuzhiyun "i2c4_21_5", 147*4882a593Smuzhiyun "sara_pwr_off", 148*4882a593Smuzhiyun "sara_networking_status"; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun eeprom@50 { 152*4882a593Smuzhiyun compatible = "microchip,24c64", "atmel,24c64"; 153*4882a593Smuzhiyun pagesize = <32>; 154*4882a593Smuzhiyun read-only; /* Manufacturing EEPROM programmed at factory */ 155*4882a593Smuzhiyun reg = <0x50>; 156*4882a593Smuzhiyun }; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun rtc@51 { 159*4882a593Smuzhiyun compatible = "nxp,pcf85263"; 160*4882a593Smuzhiyun reg = <0x51>; 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun versaclock5: versaclock_som@6a { 164*4882a593Smuzhiyun compatible = "idt,5p49v6965"; 165*4882a593Smuzhiyun reg = <0x6a>; 166*4882a593Smuzhiyun #clock-cells = <1>; 167*4882a593Smuzhiyun clocks = <&x304_clk>; 168*4882a593Smuzhiyun clock-names = "xin"; 169*4882a593Smuzhiyun /* du_dotclkin0, du_dotclkin2, usb_extal, avb_txcrefclk */ 170*4882a593Smuzhiyun assigned-clocks = <&versaclock5 1>, 171*4882a593Smuzhiyun <&versaclock5 2>, 172*4882a593Smuzhiyun <&versaclock5 3>, 173*4882a593Smuzhiyun <&versaclock5 4>; 174*4882a593Smuzhiyun assigned-clock-rates = <33333333>, <33333333>, <50000000>, <125000000>; 175*4882a593Smuzhiyun }; 176*4882a593Smuzhiyun}; 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun&pfc { 179*4882a593Smuzhiyun pinctrl-0 = <&scif_clk_pins>; 180*4882a593Smuzhiyun pinctrl-names = "default"; 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun avb_pins: avb { 183*4882a593Smuzhiyun mux { 184*4882a593Smuzhiyun groups = "avb_link", "avb_mdio", "avb_mii"; 185*4882a593Smuzhiyun function = "avb"; 186*4882a593Smuzhiyun }; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun pins_mdio { 189*4882a593Smuzhiyun groups = "avb_mdio"; 190*4882a593Smuzhiyun drive-strength = <24>; 191*4882a593Smuzhiyun }; 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun pins_mii_tx { 194*4882a593Smuzhiyun pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0", 195*4882a593Smuzhiyun "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3"; 196*4882a593Smuzhiyun drive-strength = <12>; 197*4882a593Smuzhiyun }; 198*4882a593Smuzhiyun }; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun scif2_pins: scif2 { 201*4882a593Smuzhiyun groups = "scif2_data_a"; 202*4882a593Smuzhiyun function = "scif2"; 203*4882a593Smuzhiyun }; 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun hscif0_pins: hscif0 { 206*4882a593Smuzhiyun groups = "hscif0_data", "hscif0_ctrl"; 207*4882a593Smuzhiyun function = "hscif0"; 208*4882a593Smuzhiyun }; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun hscif1_pins: hscif1 { 211*4882a593Smuzhiyun groups = "hscif1_data_a", "hscif1_ctrl_a"; 212*4882a593Smuzhiyun function = "hscif1"; 213*4882a593Smuzhiyun }; 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun hscif2_pins: hscif2 { 216*4882a593Smuzhiyun groups = "hscif2_data_a"; 217*4882a593Smuzhiyun function = "hscif2"; 218*4882a593Smuzhiyun }; 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun scif0_pins: scif0 { 221*4882a593Smuzhiyun groups = "scif0_data"; 222*4882a593Smuzhiyun function = "scif0"; 223*4882a593Smuzhiyun }; 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun scif5_pins: scif5 { 226*4882a593Smuzhiyun groups = "scif5_data_a"; 227*4882a593Smuzhiyun function = "scif5"; 228*4882a593Smuzhiyun }; 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun scif_clk_pins: scif_clk { 231*4882a593Smuzhiyun groups = "scif_clk_a"; 232*4882a593Smuzhiyun function = "scif_clk"; 233*4882a593Smuzhiyun }; 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun i2c0_pins: i2c0 { 236*4882a593Smuzhiyun groups = "i2c0"; 237*4882a593Smuzhiyun function = "i2c0"; 238*4882a593Smuzhiyun }; 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun sdhi2_pins: sd2 { 241*4882a593Smuzhiyun groups = "sdhi2_data4", "sdhi2_ctrl"; 242*4882a593Smuzhiyun function = "sdhi2"; 243*4882a593Smuzhiyun power-source = <1800>; 244*4882a593Smuzhiyun }; 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun sdhi3_pins: sd3 { 247*4882a593Smuzhiyun groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds"; 248*4882a593Smuzhiyun function = "sdhi3"; 249*4882a593Smuzhiyun power-source = <1800>; 250*4882a593Smuzhiyun }; 251*4882a593Smuzhiyun}; 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun&scif_clk { 254*4882a593Smuzhiyun clock-frequency = <14745600>; 255*4882a593Smuzhiyun}; 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun&scif2 { 258*4882a593Smuzhiyun pinctrl-0 = <&scif2_pins>; 259*4882a593Smuzhiyun pinctrl-names = "default"; 260*4882a593Smuzhiyun status = "okay"; 261*4882a593Smuzhiyun}; 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun&sdhi2 { 264*4882a593Smuzhiyun pinctrl-names = "default"; 265*4882a593Smuzhiyun pinctrl-0 = <&sdhi2_pins>; 266*4882a593Smuzhiyun bus-width = <4>; 267*4882a593Smuzhiyun vmmc-supply = <®_3p3v>; 268*4882a593Smuzhiyun vqmmc-supply = <®_1p8v>; 269*4882a593Smuzhiyun non-removable; 270*4882a593Smuzhiyun cap-power-off-card; 271*4882a593Smuzhiyun pm-ignore-notify; 272*4882a593Smuzhiyun keep-power-in-suspend; 273*4882a593Smuzhiyun mmc-pwrseq = <&wlan_pwrseq>; 274*4882a593Smuzhiyun status = "okay"; 275*4882a593Smuzhiyun #address-cells = <1>; 276*4882a593Smuzhiyun #size-cells = <0>; 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun brcmf: bcrmf@1 { 279*4882a593Smuzhiyun reg = <1>; 280*4882a593Smuzhiyun compatible = "brcm,bcm4329-fmac"; 281*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 282*4882a593Smuzhiyun interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 283*4882a593Smuzhiyun interrupt-names = "host-wake"; 284*4882a593Smuzhiyun }; 285*4882a593Smuzhiyun}; 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun&sdhi3 { 288*4882a593Smuzhiyun pinctrl-0 = <&sdhi3_pins>; 289*4882a593Smuzhiyun pinctrl-1 = <&sdhi3_pins>; 290*4882a593Smuzhiyun pinctrl-names = "default", "state_uhs"; 291*4882a593Smuzhiyun vmmc-supply = <®_3p3v>; 292*4882a593Smuzhiyun vqmmc-supply = <®_1p8v>; 293*4882a593Smuzhiyun bus-width = <8>; 294*4882a593Smuzhiyun mmc-hs200-1_8v; 295*4882a593Smuzhiyun non-removable; 296*4882a593Smuzhiyun fixed-emmc-driver-type = <1>; 297*4882a593Smuzhiyun status = "okay"; 298*4882a593Smuzhiyun}; 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun&usb2_clksel { 301*4882a593Smuzhiyun clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, 302*4882a593Smuzhiyun <&versaclock5 3>, <&usb3s0_clk>; 303*4882a593Smuzhiyun status = "okay"; 304*4882a593Smuzhiyun}; 305*4882a593Smuzhiyun 306*4882a593Smuzhiyun&usb3s0_clk { 307*4882a593Smuzhiyun clock-frequency = <100000000>; 308*4882a593Smuzhiyun}; 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun&vspb { 311*4882a593Smuzhiyun status = "okay"; 312*4882a593Smuzhiyun}; 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun&vspi0 { 315*4882a593Smuzhiyun status = "okay"; 316*4882a593Smuzhiyun}; 317