xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm64/realtek/rtd1293.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Realtek RTD1293 SoC
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2017-2019 Andreas Färber
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun#include "rtd129x.dtsi"
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun/ {
11*4882a593Smuzhiyun	compatible = "realtek,rtd1293";
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun	cpus {
14*4882a593Smuzhiyun		#address-cells = <2>;
15*4882a593Smuzhiyun		#size-cells = <0>;
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun		cpu0: cpu@0 {
18*4882a593Smuzhiyun			device_type = "cpu";
19*4882a593Smuzhiyun			compatible = "arm,cortex-a53";
20*4882a593Smuzhiyun			reg = <0x0 0x0>;
21*4882a593Smuzhiyun			next-level-cache = <&l2>;
22*4882a593Smuzhiyun		};
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun		cpu1: cpu@1 {
25*4882a593Smuzhiyun			device_type = "cpu";
26*4882a593Smuzhiyun			compatible = "arm,cortex-a53";
27*4882a593Smuzhiyun			reg = <0x0 0x1>;
28*4882a593Smuzhiyun			next-level-cache = <&l2>;
29*4882a593Smuzhiyun		};
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun		l2: l2-cache {
32*4882a593Smuzhiyun			compatible = "cache";
33*4882a593Smuzhiyun		};
34*4882a593Smuzhiyun	};
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun	timer {
37*4882a593Smuzhiyun		compatible = "arm,armv8-timer";
38*4882a593Smuzhiyun		interrupts = <GIC_PPI 13
39*4882a593Smuzhiyun			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
40*4882a593Smuzhiyun			     <GIC_PPI 14
41*4882a593Smuzhiyun			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
42*4882a593Smuzhiyun			     <GIC_PPI 11
43*4882a593Smuzhiyun			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
44*4882a593Smuzhiyun			     <GIC_PPI 10
45*4882a593Smuzhiyun			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
46*4882a593Smuzhiyun	};
47*4882a593Smuzhiyun};
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun&arm_pmu {
50*4882a593Smuzhiyun	interrupt-affinity = <&cpu0>, <&cpu1>;
51*4882a593Smuzhiyun};
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun&gic {
54*4882a593Smuzhiyun	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
55*4882a593Smuzhiyun};
56