1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun// Copyright (c) 2018, Linaro Limited 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun/dts-v1/; 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 7*4882a593Smuzhiyun#include "qcs404-evb.dtsi" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun model = "Qualcomm Technologies, Inc. QCS404 EVB 4000"; 11*4882a593Smuzhiyun compatible = "qcom,qcs404-evb-4000", "qcom,qcs404-evb", 12*4882a593Smuzhiyun "qcom,qcs404"; 13*4882a593Smuzhiyun}; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunðernet { 16*4882a593Smuzhiyun status = "okay"; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun snps,reset-gpio = <&tlmm 60 GPIO_ACTIVE_LOW>; 19*4882a593Smuzhiyun snps,reset-active-low; 20*4882a593Smuzhiyun snps,reset-delays-us = <0 10000 10000>; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun pinctrl-names = "default"; 23*4882a593Smuzhiyun pinctrl-0 = <ðernet_defaults>; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun phy-handle = <&phy1>; 26*4882a593Smuzhiyun phy-mode = "rgmii"; 27*4882a593Smuzhiyun mdio { 28*4882a593Smuzhiyun #address-cells = <0x1>; 29*4882a593Smuzhiyun #size-cells = <0x0>; 30*4882a593Smuzhiyun compatible = "snps,dwmac-mdio"; 31*4882a593Smuzhiyun phy1: phy@4 { 32*4882a593Smuzhiyun compatible = "ethernet-phy-ieee802.3-c22"; 33*4882a593Smuzhiyun device_type = "ethernet-phy"; 34*4882a593Smuzhiyun reg = <0x4>; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun}; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun&tlmm { 40*4882a593Smuzhiyun ethernet_defaults: ethernet-defaults { 41*4882a593Smuzhiyun int { 42*4882a593Smuzhiyun pins = "gpio61"; 43*4882a593Smuzhiyun function = "rgmii_int"; 44*4882a593Smuzhiyun bias-disable; 45*4882a593Smuzhiyun drive-strength = <2>; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun mdc { 48*4882a593Smuzhiyun pins = "gpio76"; 49*4882a593Smuzhiyun function = "rgmii_mdc"; 50*4882a593Smuzhiyun bias-pull-up; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun mdio { 53*4882a593Smuzhiyun pins = "gpio75"; 54*4882a593Smuzhiyun function = "rgmii_mdio"; 55*4882a593Smuzhiyun bias-pull-up; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun tx { 58*4882a593Smuzhiyun pins = "gpio67", "gpio66", "gpio65", "gpio64"; 59*4882a593Smuzhiyun function = "rgmii_tx"; 60*4882a593Smuzhiyun bias-pull-up; 61*4882a593Smuzhiyun drive-strength = <16>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun rx { 64*4882a593Smuzhiyun pins = "gpio73", "gpio72", "gpio71", "gpio70"; 65*4882a593Smuzhiyun function = "rgmii_rx"; 66*4882a593Smuzhiyun bias-disable; 67*4882a593Smuzhiyun drive-strength = <2>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun tx-ctl { 70*4882a593Smuzhiyun pins = "gpio68"; 71*4882a593Smuzhiyun function = "rgmii_ctl"; 72*4882a593Smuzhiyun bias-pull-up; 73*4882a593Smuzhiyun drive-strength = <16>; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun rx-ctl { 76*4882a593Smuzhiyun pins = "gpio74"; 77*4882a593Smuzhiyun function = "rgmii_ctl"; 78*4882a593Smuzhiyun bias-disable; 79*4882a593Smuzhiyun drive-strength = <2>; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun tx-ck { 82*4882a593Smuzhiyun pins = "gpio63"; 83*4882a593Smuzhiyun function = "rgmii_ck"; 84*4882a593Smuzhiyun bias-pull-up; 85*4882a593Smuzhiyun drive-strength = <16>; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun rx-ck { 88*4882a593Smuzhiyun pins = "gpio69"; 89*4882a593Smuzhiyun function = "rgmii_ck"; 90*4882a593Smuzhiyun bias-disable; 91*4882a593Smuzhiyun drive-strength = <2>; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun}; 95