xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm64/qcom/msm8992.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)

// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8994.h>

/ {
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	chosen { };

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x0>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
			L2_0: l2-cache {
				compatible = "cache";
				cache-level = <2>;
			};
		};

		CPU1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x1>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		CPU2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x2>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		CPU3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0 0x3>;
			next-level-cache = <&L2_0>;
			enable-method = "psci";
		};

		CPU4: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x0 0x100>;
			next-level-cache = <&L2_1>;
			enable-method = "psci";
			L2_1: l2-cache {
				compatible = "cache";
				cache-level = <2>;
			};
		};

		CPU5: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x0 0x101>;
			next-level-cache = <&L2_1>;
			enable-method = "psci";
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};

				core2 {
					cpu = <&CPU2>;
				};

				core3 {
					cpu = <&CPU3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&CPU4>;
				};

				core1 {
					cpu = <&CPU5>;
				};
			};
		};
	};

	clocks {
		xo_board: xo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
		};

		sleep_clk: sleep_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};
	};

	firmware {
		scm {
			compatible = "qcom,scm-msm8994", "qcom,scm";
		};
	};

	memory {
		device_type = "memory";
		/* We expect the bootloader to fill in the reg */
		reg = <0 0 0 0>;
	};

	pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "hvc";
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		smem_region: smem@6a00000 {
			reg = <0x0 0x6a00000 0x0 0x200000>;
			no-map;
		};
	};

	sfpb_mutex: hwmutex {
		compatible = "qcom,sfpb-mutex";
		syscon = <&sfpb_mutex_regs 0x0 0x100>;
		#hwlock-cells = <1>;
	};

	smem {
		compatible = "qcom,smem";
		memory-region = <&smem_region>;
		qcom,rpm-msg-ram = <&rpm_msg_ram>;
		hwlocks = <&sfpb_mutex 3>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xffffffff>;
		compatible = "simple-bus";

		intc: interrupt-controller@f9000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0xf9000000 0x1000>,
				<0xf9002000 0x1000>;
		};

		apcs: mailbox@f900d000 {
			compatible = "qcom,msm8994-apcs-kpss-global", "syscon";
			reg = <0xf900d000 0x2000>;
			#mbox-cells = <1>;
		};

		timer@f9020000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0xf9020000 0x1000>;

			frame@f9021000 {
				frame-number = <0>;
				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
						<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9021000 0x1000>,
					<0xf9022000 0x1000>;
			};

			frame@f9023000 {
				frame-number = <1>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9023000 0x1000>;
				status = "disabled";
			};

			frame@f9024000 {
				frame-number = <2>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9024000 0x1000>;
				status = "disabled";
			};

			frame@f9025000 {
				frame-number = <3>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9025000 0x1000>;
				status = "disabled";
			};

			frame@f9026000 {
				frame-number = <4>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9026000 0x1000>;
				status = "disabled";
			};

			frame@f9027000 {
				frame-number = <5>;
				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9027000 0x1000>;
				status = "disabled";
			};

			frame@f9028000 {
				frame-number = <6>;
				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9028000 0x1000>;
				status = "disabled";
			};
		};

		sdhc_1: sdhci@f9824900 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
			reg-names = "hc_mem", "core_mem";

			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
				<&gcc GCC_SDCC1_AHB_CLK>,
				<&xo_board>;
			clock-names = "core", "iface", "xo";

			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
					&sdc1_rclk_on>;
			pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
					&sdc1_rclk_off>;

			regulator-always-on;
			bus-width = <8>;
			non-removable;

			status = "disabled";
		};

		blsp1_uart2: serial@f991e000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0xf991e000 0x1000>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>;
			clock-names = "core", "iface";
			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
				<&gcc GCC_BLSP1_AHB_CLK>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp1_uart2_default>;
			pinctrl-1 = <&blsp1_uart2_sleep>;
			status = "disabled";
		};

		blsp_i2c2: i2c@f9924000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0xf9924000 0x500>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			clock-frequency = <400000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&i2c2_default>;
			pinctrl-1 = <&i2c2_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		/* Somebody was very creative with their numbering scheme downstream... */

		blsp_i2c13: i2c@f9927000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0xf9927000 0x500>;
			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				<&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			clock-frequency = <400000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&i2c13_default>;
			pinctrl-1 = <&i2c13_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_i2c6: i2c@f9928000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0xf9928000 0x500>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			clock-frequency = <400000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&i2c6_default>;
			pinctrl-1 = <&i2c6_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp2_uart2: serial@f995e000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0xf995e000 0x1000>;
			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_LOW>;
			clock-names = "core", "iface";
			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
				<&gcc GCC_BLSP2_AHB_CLK>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp2_uart2_default>;
			pinctrl-1 = <&blsp2_uart2_sleep>;
			status = "disabled";
		};

		blsp_i2c7: i2c@f9963000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0xf9963000 0x500>;
			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
				<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			clock-frequency = <400000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&i2c7_default>;
			pinctrl-1 = <&i2c7_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_i2c5: i2c@f9967000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0xf9967000 0x500>;
			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP2_AHB_CLK>,
				<&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			clock-frequency = <100000>;
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&i2c5_default>;
			pinctrl-1 = <&i2c5_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		gcc: clock-controller@fc400000 {
			compatible = "qcom,gcc-msm8994";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0xfc400000 0x2000>;
		};

		rpm_msg_ram: memory@fc428000 {
			compatible = "qcom,rpm-msg-ram";
			reg = <0xfc428000 0x4000>;
		};

		restart@fc4ab000 {
			compatible = "qcom,pshold";
			reg = <0xfc4ab000 0x4>;
		};

		spmi_bus: spmi@fc4c0000 {
			compatible = "qcom,spmi-pmic-arb";
			reg = <0xfc4cf000 0x1000>,
			      <0xfc4cb000 0x1000>,
			      <0xfc4ca000 0x1000>;
			reg-names = "core", "intr", "cnfg";
			interrupt-names = "periph_irq";
			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
		};

		sfpb_mutex_regs: syscon@fd484000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "syscon";
			reg = <0xfd484000 0x400>;
		};

		tlmm: pinctrl@fd510000 {
			compatible = "qcom,msm8994-pinctrl";
			reg = <0xfd510000 0x4000>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			gpio-ranges = <&tlmm 0 0 146>;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;

			blsp1_uart2_default: blsp1-uart2-default {
				function = "blsp_uart2";
				pins = "gpio4", "gpio5";
				drive-strength = <16>;
				bias-disable;
			};

			blsp1_uart2_sleep: blsp1-uart2-sleep {
				function = "gpio";
				pins = "gpio4", "gpio5";
				drive-strength = <2>;
				bias-pull-down;
			};

			blsp2_uart2_default: blsp2-uart2-default {
				function = "blsp_uart8";
				pins = "gpio45", "gpio46", "gpio47", "gpio48";
				drive-strength = <16>;
				bias-disable;
			};

			blsp2_uart2_sleep: blsp2-uart2-sleep {
				function = "gpio";
				pins = "gpio45", "gpio46", "gpio47", "gpio48";
				drive-strength = <2>;
				bias-pull-down;
			};

			sdc1_clk_on: clk-on {
				pins = "sdc1_clk";
				bias-disable;
				drive-strength = <6>;
			};

			sdc1_clk_off: clk-off {
				pins = "sdc1_clk";
				bias-disable;
				drive-strength = <2>;
			};

			sdc1_cmd_on: cmd-on {
				pins = "sdc1_cmd";
				bias-pull-up;
				drive-strength = <6>;
			};

			sdc1_cmd_off: cmd-off {
				pins = "sdc1_cmd";
				bias-pull-up;
				drive-strength = <2>;
			};

			sdc1_data_on: data-on {
				pins = "sdc1_data";
				bias-pull-up;
				drive-strength = <6>;
			};

			sdc1_data_off: data-off {
				pins = "sdc1_data";
				bias-pull-up;
				drive-strength = <2>;
			};

			sdc1_rclk_on: rclk-on {
				pins = "sdc1_rclk";
				bias-pull-down;
			};

			sdc1_rclk_off: rclk-off {
				pins = "sdc1_rclk";
				bias-pull-down;
			};

			i2c2_default: i2c2-default {
				function = "blsp_i2c2";
				pins = "gpio6", "gpio7";
				drive-strength = <2>;
				bias-disable;
			};

			i2c2_sleep: i2c2-sleep {
				function = "gpio";
				pins = "gpio6", "gpio7";
				drive-strength = <2>;
				bias-disable;
			};

			i2c5_default: i2c5-default {
				/* Don't be fooled! Nobody knows the reason why though... */
				function = "blsp_i2c11";
				pins = "gpio83", "gpio84";
				drive-strength = <2>;
				bias-disable;
			};

			i2c5_sleep: i2c5-sleep {
				function = "gpio";
				pins = "gpio83", "gpio84";
				drive-strength = <2>;
				bias-disable;
			};

			i2c6_default: i2c6-default {
				function = "blsp_i2c6";
				pins = "gpio28", "gpio27";
				drive-strength = <2>;
				bias-disable;
			};

			i2c6_sleep: i2c6-sleep {
				function = "gpio";
				pins = "gpio28", "gpio27";
				drive-strength = <2>;
				bias-disable;
			};

			i2c7_default: i2c7-default {
				function = "blsp_i2c7";
				pins = "gpio43", "gpio44";
				drive-strength = <2>;
				bias-disable;
			};

			i2c7_sleep: i2c7-sleep {
				function = "gpio";
				pins = "gpio43", "gpio44";
				drive-strength = <2>;
				bias-disable;
			};

			i2c13_default: i2c13-default {
				/* Not a typo either. */
				function = "blsp_i2c5";
				pins = "gpio23", "gpio24";
				drive-strength = <2>;
				bias-disable;
			};

			i2c13_sleep: i2c13-sleep {
				function = "gpio";
				pins = "gpio23", "gpio24";
				drive-strength = <2>;
				bias-disable;
			};
		};
	};

	smd_rpm: smd {
		compatible = "qcom,smd";
		rpm {
			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
			qcom,ipc = <&apcs 8 0>;
			qcom,smd-edge = <15>;
			qcom,local-pid = <0>;
			qcom,remote-pid = <6>;

			rpm_requests: rpm-requests {
				compatible = "qcom,rpm-msm8994";
				qcom,smd-channels = "rpm_requests";

				rpmcc: rpmcc {
					compatible = "qcom,rpmcc-msm8992";
					#clock-cells = <1>;
				};
			};
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	vreg_vph_pwr: vreg-vph-pwr {
		compatible = "regulator-fixed";
		status = "okay";
		regulator-name = "vph-pwr";

		regulator-min-microvolt = <3600000>;
		regulator-max-microvolt = <3600000>;

		regulator-always-on;
	};
};