1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree Source for MediaTek X20 Development Board 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2018, Linaro Ltd. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/dts-v1/; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun#include "mt6797.dtsi" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun model = "Mediatek X20 Development Board"; 15*4882a593Smuzhiyun compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797"; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun aliases { 18*4882a593Smuzhiyun serial0 = &uart1; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun memory@40000000 { 22*4882a593Smuzhiyun device_type = "memory"; 23*4882a593Smuzhiyun reg = <0 0x40000000 0 0x80000000>; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun chosen { 27*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun}; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun/* HDMI */ 32*4882a593Smuzhiyun&i2c1 { 33*4882a593Smuzhiyun pinctrl-names = "default"; 34*4882a593Smuzhiyun pinctrl-0 = <&i2c1_pins_a>; 35*4882a593Smuzhiyun status = "okay"; 36*4882a593Smuzhiyun}; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun/* HS - I2C2 */ 39*4882a593Smuzhiyun&i2c2 { 40*4882a593Smuzhiyun pinctrl-names = "default"; 41*4882a593Smuzhiyun pinctrl-0 = <&i2c2_pins_a>; 42*4882a593Smuzhiyun status = "okay"; 43*4882a593Smuzhiyun}; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun/* HS - I2C3 */ 46*4882a593Smuzhiyun&i2c3 { 47*4882a593Smuzhiyun pinctrl-names = "default"; 48*4882a593Smuzhiyun pinctrl-0 = <&i2c3_pins_a>; 49*4882a593Smuzhiyun status = "okay"; 50*4882a593Smuzhiyun}; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun/* LS - I2C0 */ 53*4882a593Smuzhiyun&i2c4 { 54*4882a593Smuzhiyun pinctrl-names = "default"; 55*4882a593Smuzhiyun pinctrl-0 = <&i2c4_pins_a>; 56*4882a593Smuzhiyun status = "okay"; 57*4882a593Smuzhiyun}; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun/* LS - I2C1 */ 60*4882a593Smuzhiyun&i2c5 { 61*4882a593Smuzhiyun pinctrl-names = "default"; 62*4882a593Smuzhiyun pinctrl-0 = <&i2c5_pins_a>; 63*4882a593Smuzhiyun status = "okay"; 64*4882a593Smuzhiyun}; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun/* POWER_VPROC */ 67*4882a593Smuzhiyun&i2c6 { 68*4882a593Smuzhiyun pinctrl-names = "default"; 69*4882a593Smuzhiyun pinctrl-0 = <&i2c6_pins_a>; 70*4882a593Smuzhiyun status = "okay"; 71*4882a593Smuzhiyun}; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun/* FAN53555 */ 74*4882a593Smuzhiyun&i2c7 { 75*4882a593Smuzhiyun pinctrl-names = "default"; 76*4882a593Smuzhiyun pinctrl-0 = <&i2c7_pins_a>; 77*4882a593Smuzhiyun status = "okay"; 78*4882a593Smuzhiyun}; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun&uart1 { 81*4882a593Smuzhiyun status = "okay"; 82*4882a593Smuzhiyun pinctrl-names = "default"; 83*4882a593Smuzhiyun pinctrl-0 = <&uart1_pins_a>; 84*4882a593Smuzhiyun}; 85